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Thu, 11 May 2023 10:56:40 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [RFC 1/7] hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output payload of identify memory device command Thread-Topic: [RFC 1/7] hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output payload of identify memory device command Thread-Index: AQHZhDHwaEF1ZZLYJUyUWkAyoCZzdw== Date: Thu, 11 May 2023 17:56:40 +0000 Message-ID: <20230511175609.2091136-2-fan.ni@samsung.com> In-Reply-To: <20230511175609.2091136-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLKsWRmVeSWpSXmKPExsWy7djX87qROrEpBt3/lCy6z29gtJg+9QKj xeqbaxgtGpoesVi07H7PZLH/6XMWi1ULr7FZnJ91isXi+cTnTBZLlzxitjjeu4PFgdvjwuQJ rB6LG1w9ds66y+7RcuQtkLfnJZPHxo//2T2eXNvM5LH59Qtmj6mz6z0+b5IL4IrisklJzcks Sy3St0vgylj0YCVLwSXeiiez1rE2MPZydzFyckgImEis+LCfpYuRi0NIYCWjxJdL8xghnFYm iffT9zHCVLVtPs8GkVjLKPFw2hQo5xOjxK+3F1ghnGWMEn8X3mUDaWETUJTY17UdzBYRMJY4 dngJM0gRs8BbFomPa96wgCSEBeokVk9aA7ZdRKCZUaJh4mWoDj2JXz/vghWxCKhKnLuxA+wQ XgFLideLmsBqOAWsJDY0n2ACsRkFxCS+n1oDZjMLiEvcejKfCeJwQYlFs/cwQ9hiEv92PWSD sOUlJv+YAWUrStz//pIdoldP4sbUKWwQtrbEsoWvmSH2CkqcnPmEBaJeUuLgihtgR0sITOaU +PnpIDtEwkXi0qqjUEOlJf7eXQZ0BAeQnSyx6iMXRDhHYv6SLVBzrCUW/lnPNIFRZRaSs2ch OWMWkjNmITljASPLKkbx0uLi3PTUYuO81HK94sTc4tK8dL3k/NxNjMAUd/rf4YIdjLdufdQ7 xMjEwXiIUYKDWUmE9+2S6BQh3pTEyqrUovz4otKc1OJDjNIcLErivIa2J5OFBNITS1KzU1ML UotgskwcnFINTFNWZ1a/Xap++KuCWPevysNzrt26Kfpj7paZa+Zt+XI2ufR11xk9BT/nvWze my/8WjTZfHP/xgvzXmwP2XFrWk7OPBffi1dffmVZzvs662NnVPOi9xe05Kts1j9o62i42syq FrPT78jPqIJFESLOS/ZwreRQvtB90lZhV+C8a6HMmiWvO09Jlry2ehXiYJ55weTEy9unyuxb FTbk/iz1+6q+/4PdWrGEGQyy82Y+0v5t4rA9UPhw6UqdSL39x12zC/d9c5vZtVTzc+mWmYUc UZaTNi2t/58m9d8h41T3gtcdkhz9DHLv2RM7NmziZZN8PyHo4l2ZabdKVM8tUr1076u4i/7/ rWFTp85YNP/KpEf8SizFGYmGWsxFxYkAP26LqOADAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrFIsWRmVeSWpSXmKPExsWS2cA0STdSJzbF4EQnj0X3+Q2MFtOnXmC0 WH1zDaNFQ9MjFouW3e+ZLPY/fc5isWrhNTaL87NOsVg8n/icyWLpkkfMFsd7d7A4cHtcmDyB 1WNxg6vHzll32T1ajrwF8va8ZPLY+PE/u8eTa5uZPDa/fsHsMXV2vcfnTXIBXFFcNimpOZll qUX6dglcGYserGQpuMRb8WTWOtYGxl7uLkZODgkBE4m2zefZuhi5OIQEVjNKzN17lBHC+cQo 8efnRWYIZxmjxObJXYwgLWwCihL7urazgdgiAsYSxw4vYQaxmQVes0h8uwg2VligTmL1pDUs IM0iAs2MEms2b2eHaNCT+PXzLguIzSKgKnHuxg6wobwClhKvFzWBDRUCsj/+3AlWzylgJbGh +QQTiM0oICbx/dQaJohl4hK3nsxngvhBQGLJnvPMELaoxMvH/1ghbHmJyT9msEHYihL3v79k h+jVk7gxdQobhK0tsWzha2aIGwQlTs58wgJRLylxcMUNlgmMErOQrJuFpH0WkvZZSNoXMLKs YhQvLS7OTa8oNspLLdcrTswtLs1L10vOz93ECEwOp/8djt7BePvWR71DjEwcjIcYJTiYlUR4 3y6JThHiTUmsrEotyo8vKs1JLT7EKM3BoiTO+zJqYryQQHpiSWp2ampBahFMlomDU6qBKU3z 77QVps+7Ld5dfTNX/3jHxRcfjy87uvA919LZpSdrzAJ/GXfEr8vNCr24jGHO/4naGjFxWgL5 fhVtfr0uDpHiGzTfuJ2a83VasuyKNVuuckVvyNvsXJ/1n60prDCw4NOaODGHJZYx6/sFjsmn 2b351bk5O2uZYl0Cd/e7Q03Z083nep+P42e/dv9i1UtVPYdl5gUTtuRY9gbMfRVXZPE+JlRx i8oUpzPtH92Ud8XyFSd8n9wj0vC78I7UAZm9U+OX3liof3Taia1Fp2Yxyx0QKNVS0py+PzeW /Zv21ZqVkjIvePQNZL85vtVcHHbzWYH27by85x2rTtY+rlx2pMJ4voexmNa+ABnpjMg7SizF GYmGWsxFxYkAF8AQj30DAAA= X-CMS-MailID: 20230511175641uscas1p2e2dd6a5b681f73870e33869af0247c06 CMS-TYPE: 301P X-CMS-RootMailID: 20230511175641uscas1p2e2dd6a5b681f73870e33869af0247c06 References: <20230511175609.2091136-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.11; envelope-from=fan.ni@samsung.com; helo=mailout1.w2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Fan Ni Based on CXL spec 3.0 Table 8-94 (Identify Memory Device Output Payload), dynamic capacity event log size should be part of output of the Identify command. Add dc_event_log_size to the output payload for the host to get the info. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 9f8e6722d7..7ff4fbdf22 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -21,6 +21,8 @@ #include "sysemu/hostmem.h" #define CXL_CAPACITY_MULTIPLIER (256 * MiB) +/* Experimental value: dynamic capacity event log size */ +#define CXL_DC_EVENT_LOG_SIZE 8 /* * How to add a new command, example. The command set FOO, with cmd BAR. @@ -519,8 +521,9 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, uint16_t inject_poison_limit; uint8_t poison_caps; uint8_t qos_telemetry_caps; + uint16_t dc_event_log_size; } QEMU_PACKED *id; - QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43); + QEMU_BUILD_BUG_ON(sizeof(*id) != 0x45); CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d); @@ -543,6 +546,7 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, st24_le_p(id->poison_list_max_mer, 256); /* No limit - so limited by main poison record limit */ stw_le_p(&id->inject_poison_limit, 0); + stw_le_p(&id->dc_event_log_size, CXL_DC_EVENT_LOG_SIZE); *len = sizeof(*id); return CXL_MBOX_SUCCESS; From patchwork Thu May 11 17:56:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 13238325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9EEEC7EE24 for ; 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Thu, 11 May 2023 17:56:41 +0000 (GMT) X-AuditID: cbfec36d-975ff70000004dd5-84-645d2c591473 Received: from SSI-EX4.ssi.samsung.com ( [105.128.2.146]) by ussmgxs1new.samsung.com (USCPEXMTA) with SMTP id 98.7F.38326.95C2D546; Thu, 11 May 2023 13:56:41 -0400 (EDT) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX4.ssi.samsung.com (105.128.2.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Thu, 11 May 2023 10:56:40 -0700 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Thu, 11 May 2023 10:56:40 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [RFC 2/7] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support Thread-Topic: [RFC 2/7] hw/cxl/cxl-mailbox-utils: Add dynamic capacity region representative and mailbox command support Thread-Index: AQHZhDHwZg5veepn5EaQyLC3G3XrlA== Date: Thu, 11 May 2023 17:56:40 +0000 Message-ID: <20230511175609.2091136-3-fan.ni@samsung.com> In-Reply-To: <20230511175609.2091136-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNKsWRmVeSWpSXmKPExsWy7djX87pROrEpBnf1LLrPb2C0mD71AqPF 6ptrGC0amh6xWLTsfs9ksf/pcxaLVQuvsVmcn3WKxeL5xOdMFkuXPGK2ON67g8WB2+PC5Ams HosbXD12zrrL7tFy5C2Qt+clk8fGj//ZPZ5c28zksfn1C2aPqbPrPT5vkgvgiuKySUnNySxL LdK3S+DK2HttL2vBbZWKRce3sTYwzpDrYuTkkBAwkZi1YTZbFyMXh5DASkaJaQ8msEM4rUwS 058+ZYGpurdzIxNEYi2jxOmWVcwQzidGicOL/kI5yxgl/i68ywbSwiagKLGvazuYLSJgLHHs 8BKwImaBtywSH9e8AZsrLFAqsanxKhNEUZXEzY0HoGw9iTMfT4PVsAioSpy7sYMRxOYVsJQ4 f6wFLM4pYCWxofkEWD2jgJjE91NrwGxmAXGJW0/mM0HcLSixaPYeZghbTOLfrodsELa8xOQf M6BsRYn731+yQ/TqSdyYOoUNwtaWWLbwNTPEXkGJkzOfQMNCUuLgihssIM9ICPRzShy+0sMI kXCRONQ6G8qWlrh6fSpQMweQnSyx6iMXRDhHYv6SLVBzrCUW/lnPNIFRZRaSs2chOWMWkjNm ITljASPLKkbx0uLi3PTUYsO81HK94sTc4tK8dL3k/NxNjMD0dvrf4dwdjDtufdQ7xMjEwXiI UYKDWUmE9+2S6BQh3pTEyqrUovz4otKc1OJDjNIcLErivIa2J5OFBNITS1KzU1MLUotgskwc nFINTGu99HqKg1ROf7cOeXt35wv+JN2t1QIHsu6wK+rq9u9/6Bo+cUpIt722e5l++JMj8axd LU+7+bgz284ZlreZF/SEK2/Y4x/RkLO9zGnV1UNvLNYe2Z9TcVew4PWT/Qd+r5xnPndFbZL4 pIqPFa1PvZrtAw9b2m2vL5wnVTdtb3RY5WwxtwVvqsqdnk7N8nutuV5gk8cswzO3jyw7/eH3 2XDrJjP2FoZH/hYuKyyXyITbHu417xTW/y389uPe6ns3WFZ2f9H1LDhTLyFjF39080uNNYmq CUe3B1RzHQjd9+Jg4cJfx33/xy9N2M12+MNmhkMdd5sKdiydpvVd/WxY1eqJO/3X3n/M9Svf bdIDByWW4oxEQy3mouJEAJiYx0TeAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBIsWRmVeSWpSXmKPExsWS2cA0STdSJzbFoKdF1qL7/AZGi+lTLzBa rL65htGioekRi0XL7vdMFvufPmexWLXwGpvF+VmnWCyeT3zOZLF0ySNmi+O9O1gcuD0uTJ7A 6rG4wdVj56y77B4tR94CeXteMnls/Pif3ePJtc1MHptfv2D2mDq73uPzJrkArigum5TUnMyy 1CJ9uwSujL3X9rIW3FapWHR8G2sD4wy5LkZODgkBE4l7OzcygdhCAqsZJZY0WHQxcgHZnxgl ut8dZYZwljFKbJ7cxQhSxSagKLGvazsbiC0iYCxx7PASZhCbWeA1i8S3i9wgtrBAqcSmxqtM EDVVEoc7JrNA2HoSZz6eBrNZBFQlzt3YATaTV8BS4vyxFhaIKywlPv7cyQ5icwpYSWxoPgE2 h1FATOL7qTVMELvEJW49mc8E8YGAxJI955khbFGJl4//sULY8hKTf8xgg7AVJe5/f8kO0asn cWPqFDYIW1ti2cLXzBA3CEqcnPmEBaJeUuLgihssExglZiFZNwtJ+ywk7bOQtC9gZFnFKF5a XJybXlFsmJdarlecmFtcmpeul5yfu4kRmBhO/zscuYPx6K2PeocYmTgYDzFKcDArifC+XRKd IsSbklhZlVqUH19UmpNafIhRmoNFSZxXyHVivJBAemJJanZqakFqEUyWiYNTqoEprXjJ2qpb QndW/51yItzw+XHe97YG+SeWG/7Zd/7F7PV9QUEVuq+Me69qCy8OKHOfJHK70XhD8KP338vf x9kZXdr2dK7tPraVlQkVoft+fji5ruUX5zr5Dx2fGd6V1p92PscbKvL9P0dzQeg2bYEHXgWR byu0nJTmf/kj9MykSCmvYnE0V0912t2vMu2G7Jo37i94X+HYYsccuKCZXeBSvcY5z/kXQy26 1lTNbA46seaau52UxedLaQmvE17Pt7d8v8av/3+sivTFjzddeiOMxSSbXvJPc/i+wGmfKre2 TIlj22uNCqs1VQf8OkRLvlVKK3q4/PX7JRTElvpA4nRperelwcaPlzubpjEGtiuxFGckGmox FxUnAgCLUE87ewMAAA== X-CMS-MailID: 20230511175641uscas1p165a19a1416facf6603bf1a417121f0dc CMS-TYPE: 301P X-CMS-RootMailID: 20230511175641uscas1p165a19a1416facf6603bf1a417121f0dc References: <20230511175609.2091136-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.11; envelope-from=fan.ni@samsung.com; helo=mailout1.w2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Fan Ni Per cxl spec 3.0, add dynamic capacity region representative based on Table 8-126 and extend the cxl type3 device definition to include dc region information. Also, based on info in 8.2.9.8.9.1, add 'Get Dynamic Capacity Configuration' mailbox support. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 68 +++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 16 +++++++++ 2 files changed, 84 insertions(+) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 7ff4fbdf22..61c77e52d8 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -81,6 +81,8 @@ enum { #define GET_POISON_LIST 0x0 #define INJECT_POISON 0x1 #define CLEAR_POISON 0x2 + DCD_CONFIG = 0x48, /*8.2.9.8.9*/ + #define GET_DC_REGION_CONFIG 0x0 PHYSICAL_SWITCH = 0x51 #define IDENTIFY_SWITCH_DEVICE 0x0 }; @@ -935,6 +937,70 @@ static CXLRetCode cmd_media_clear_poison(struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } +/* + * cxl spec 3.0: 8.2.9.8.9.2 + * Get Dynamic Capacity Configuration + **/ +static CXLRetCode cmd_dcd_get_dyn_cap_config(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, + uint16_t *len) +{ + struct get_dyn_cap_config_in_pl { + uint8_t region_cnt; + uint8_t start_region_id; + } QEMU_PACKED; + + struct get_dyn_cap_config_out_pl { + uint8_t num_regions; + uint8_t rsvd1[7]; + struct { + uint64_t base; + uint64_t decode_len; + uint64_t region_len; + uint64_t block_size; + uint32_t dsmadhandle; + uint8_t flags; + uint8_t rsvd2[3]; + } QEMU_PACKED records[]; + } QEMU_PACKED; + + struct get_dyn_cap_config_in_pl *in = (void *)cmd->payload; + struct get_dyn_cap_config_out_pl *out = (void *)cmd->payload; + struct CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); + uint16_t record_count = 0, i = 0; + uint16_t out_pl_len; + + if (in->start_region_id >= ct3d->dc.num_regions) + record_count = 0; + else if (ct3d->dc.num_regions - in->start_region_id < in->region_cnt) + record_count = ct3d->dc.num_regions - in->start_region_id; + else + record_count = in->region_cnt; + + out_pl_len = sizeof(*out) + record_count * sizeof(out->records[0]); + assert(out_pl_len <= CXL_MAILBOX_MAX_PAYLOAD_SIZE); + + memset(out, 0, out_pl_len); + out->num_regions = record_count; + for (; i < record_count; i++) { + stq_le_p(&out->records[i].base, + ct3d->dc.regions[in->start_region_id+i].base); + stq_le_p(&out->records[i].decode_len, + ct3d->dc.regions[in->start_region_id+i].decode_len); + stq_le_p(&out->records[i].region_len, + ct3d->dc.regions[in->start_region_id+i].len); + stq_le_p(&out->records[i].block_size, + ct3d->dc.regions[in->start_region_id+i].block_size); + stl_le_p(&out->records[i].dsmadhandle, + ct3d->dc.regions[in->start_region_id+i].dsmadhandle); + out->records[i].flags + = ct3d->dc.regions[in->start_region_id+i].flags; + } + + *len = out_pl_len; + return CXL_MBOX_SUCCESS; +} + #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_DATA_CHANGE (1 << 2) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -973,6 +1039,8 @@ static struct cxl_cmd cxl_cmd_set[256][256] = { cmd_media_inject_poison, 8, 0 }, [MEDIA_AND_POISON][CLEAR_POISON] = { "MEDIA_AND_POISON_CLEAR_POISON", cmd_media_clear_poison, 72, 0 }, + [DCD_CONFIG][GET_DC_REGION_CONFIG] = { "DCD_GET_DC_REGION_CONFIG", + cmd_dcd_get_dyn_cap_config, 2, 0 }, }; static struct cxl_cmd cxl_cmd_set_sw[256][256] = { diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index e285369693..8a04e53e90 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -383,6 +383,17 @@ typedef struct CXLPoison { typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; #define CXL_POISON_LIST_LIMIT 256 +#define DCD_MAX_REGION_NUM 8 + +typedef struct CXLDCD_Region { + uint64_t base; + uint64_t decode_len; /* in multiples of 256MB */ + uint64_t len; + uint64_t block_size; + uint32_t dsmadhandle; + uint8_t flags; +} CXLDCD_Region; + struct CXLType3Dev { /* Private */ PCIDevice parent_obj; @@ -414,6 +425,11 @@ struct CXLType3Dev { unsigned int poison_list_cnt; bool poison_list_overflowed; uint64_t poison_list_overflow_ts; + + struct dynamic_capacity { + uint8_t num_regions; // 1-8 + struct CXLDCD_Region regions[DCD_MAX_REGION_NUM]; + } dc; }; #define TYPE_CXL_TYPE3 "cxl-type3" From patchwork Thu May 11 17:56:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 13238291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7306C77B7F for ; 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Thu, 11 May 2023 17:56:41 +0000 (GMT) X-AuditID: cbfec36f-249ff7000000a673-92-645d2c597ee0 Received: from SSI-EX2.ssi.samsung.com ( [105.128.2.145]) by ussmgxs3new.samsung.com (USCPEXMTA) with SMTP id D9.48.64580.95C2D546; Thu, 11 May 2023 13:56:41 -0400 (EDT) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX2.ssi.samsung.com (105.128.2.227) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Thu, 11 May 2023 10:56:40 -0700 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Thu, 11 May 2023 10:56:40 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [RFC 3/7] hw/mem/cxl_type3: Add a parameter to pass number of DC regions the device supports in qemu command line Thread-Topic: [RFC 3/7] hw/mem/cxl_type3: Add a parameter to pass number of DC regions the device supports in qemu command line Thread-Index: AQHZhDHwgPX9k8X0Wk2f5wJohcsLYA== Date: Thu, 11 May 2023 17:56:40 +0000 Message-ID: <20230511175609.2091136-4-fan.ni@samsung.com> In-Reply-To: <20230511175609.2091136-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNKsWRmVeSWpSXmKPExsWy7djXc7qROrEpBs+fW1p0n9/AaDF96gVG i9U31zBaNDQ9YrFo2f2eyWL/0+csFqsWXmOzOD/rFIvF84nPmSyWLnnEbHG8dweLA7fHhckT WD0WN7h67Jx1l92j5chbIG/PSyaPjR//s3s8ubaZyWPz6xfMHlNn13t83iQXwBXFZZOSmpNZ llqkb5fAlfFg6znGgjeCFV3nj7A1MB7m62Lk5JAQMJFYdnoDaxcjF4eQwEpGic5dixkhnFYm iddfl7DDVP19vQ3MFhJYyyhx8kY2RNEnRolrs/awQzjLGCX+LrzLBlLFJqAosa9rO5gtImAs cezwEmaQImaBtywSH9e8YQFJCAvUSOyed5kFJCEi0Mgo8eboP1aIDj2J/Y33wfaxCKhKnLux gxHE5hWwlJhwt5EZxOYUsJLY0HyCCcRmFBCT+H5qDZjNLCAucevJfCaIuwUlFs3ewwxhi0n8 2/WQDcKWl5j8YwaUrShx//tLdohePYkbU6ewQdjaEssWvmaG2CsocXLmExaIekmJgytugB0t ITCZU6Jr3jqgozmAHBeJF/t4IWqkJaavAXkMJJwsseojF0Q4R2L+ki1QY6wlFv5ZzzSBUWUW kqtnIbliFpIrZiG5YgEjyypG8dLi4tz01GKjvNRyveLE3OLSvHS95PzcTYzA9Hb63+H8HYzX b33UO8TIxMF4iFGCg1lJhPftkugUId6UxMqq1KL8+KLSnNTiQ4zSHCxK4ryGtieThQTSE0tS s1NTC1KLYLJMHJxSDUzyEr+3L817oWTFe0Dhn0dfNbul2fSfzjzyiUUeT234fZ3aClcIvDSf xasfWHYq8gQLK5/RNseKo7X5PiySJzOsRG8KbA6Y12Ku71hZa/Xbd1v2tjdi57SbVWQ2Sovf zRJ5b544I+qHzG5GSxf9vGcyKznWX7934WfgmsLfSc5uXN6qs2xePlPacyM4zj7as110iuG3 NP/cnnWNT8JUhI89uigqu3feOYPI8Nr2gv9vF9yU33fgTfjyy2IW3xTbdvlVrgt/Xhh6+9qh u3KPr0nPuBS3jE2Oa3L2iRvanRqtP99v3zZvdSDPucyy96snscZo7kn1VddZsExbMPXmVc1v 5X+al1df89yxUGMbixJLcUaioRZzUXEiANoiPT7eAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrFIsWRmVeSWpSXmKPExsWS2cA0UTdSJzbF4PQ6BYvu8xsYLaZPvcBo sfrmGkaLhqZHLBYtu98zWex/+pzFYtXCa2wW52edYrF4PvE5k8XSJY+YLY737mBx4Pa4MHkC q8fiBlePnbPusnu0HHkL5O15yeSx8eN/do8n1zYzeWx+/YLZY+rseo/Pm+QCuKK4bFJSczLL Uov07RK4Mh5sPcdY8Eawouv8EbYGxsN8XYycHBICJhJ/X29j72Lk4hASWM0osXr3ckYI5xOj xMf759kgnGWMEpsndzGCtLAJKErs69rOBmKLCBhLHDu8hBnEZhZ4zSLx7SI3iC0sUCOxe95l FpBmEYFGRolHT+4xQjToSexvvM8OYrMIqEqcu7EDLM4rYCkx4W4j2CAhIPvjz51gNZwCVhIb mk8wgdiMAmIS30+tYYJYJi5x68l8JogfBCSW7DnPDGGLSrx8/I8VwpaXmPxjBhuErShx//tL dohePYkbU6ewQdjaEssWvmaGuEFQ4uTMJywQ9ZISB1fcYJnAKDELybpZSNpnIWmfhaR9ASPL Kkbx0uLi3PSKYuO81HK94sTc4tK8dL3k/NxNjMDkcPrf4ZgdjPdufdQ7xMjEwXiIUYKDWUmE 9+2S6BQh3pTEyqrUovz4otKc1OJDjNIcLErivB6xE+OFBNITS1KzU1MLUotgskwcnFINTAGJ DKI6f9QnsU0pZ74pzXTsivHrUL4VnHdF/uu4iVYf0n1wXWRH7IZ9TgsLfH8VP7yWVerz+fXx 7p1KbWWMDkHhBszb8woy25sO7l7LrDhdemn0AdldfsZMSiFrPzxu3CbddTV/yZTzT7z4wxsy L69g5dumEP/y2u2Uip6nQr7/TKZ1GZpwqkhfWpYqle6/e+a8utW6311i7kneU37AkPz7S9c8 FQVTNyUGsZ/CRRH/jvGVaaq1LTeMK5kq/98gpuv6ttPv/07xCEjbMC2HfYOiU5tvWcdzA2+J tc0Xknnf8+wTFdx/IWS5Y/SWFYKPzQLPuZye9TWGT6RLkV+5gv+8b7v5xe+bJJdOiElXYinO SDTUYi4qTgQAyB8Y830DAAA= X-CMS-MailID: 20230511175641uscas1p13ee26532e3a1de36f6081f970190eeed CMS-TYPE: 301P X-CMS-RootMailID: 20230511175641uscas1p13ee26532e3a1de36f6081f970190eeed References: <20230511175609.2091136-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.12; envelope-from=fan.ni@samsung.com; helo=mailout2.w2.samsung.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Fan Ni Add a property 'num-dc-regions' to ct3_props to allow users to create DC regions. With the change, users can control the number of DC regions the device supports. To make it easier, other parameters of the region like region base, length, and block size are hard coded. If desired, these parameters can be added easily. Signed-off-by: Fan Ni --- hw/mem/cxl_type3.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 2b483d3d8e..b9c375d9b4 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -684,6 +684,34 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, } } +/* + * Create a dc region to test "Get Dynamic Capacity Configuration" command. + */ +static int cxl_create_toy_regions(CXLType3Dev *ct3d) +{ + int i; + uint64_t region_base = ct3d->hostvmem?ct3d->hostvmem->size + + ct3d->hostpmem->size:ct3d->hostpmem->size; + uint64_t region_len = 1024*1024*1024; + uint64_t decode_len = 4; /* 4*256MB */ + uint64_t blk_size = 2*1024*1024; + struct CXLDCD_Region *region; + + for (i = 0; i < ct3d->dc.num_regions; i++) { + region = &ct3d->dc.regions[i]; + region->base = region_base; + region->decode_len = decode_len; + region->len = region_len; + region->block_size = blk_size; + /* dsmad_handle is set when creating cdat table entries */ + region->flags = 0; + + region_base += region->len; + } + + return 0; +} + static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { DeviceState *ds = DEVICE(ct3d); @@ -752,6 +780,9 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) g_free(p_name); } + if (cxl_create_toy_regions(ct3d)) + return false; + return true; } @@ -1036,6 +1067,7 @@ static Property ct3_props[] = { DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), DEFINE_PROP_UINT16("spdm", CXLType3Dev, spdm_port, 0), + DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0), DEFINE_PROP_END_OF_LIST(), }; From patchwork Thu May 11 17:56:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 13238293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3D0CC7EE24 for ; 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Thu, 11 May 2023 17:56:41 +0000 (GMT) X-AuditID: cbfec36d-bdbfe70000004dd5-85-645d2c5a5174 Received: from SSI-EX2.ssi.samsung.com ( [105.128.2.145]) by ussmgxs3new.samsung.com (USCPEXMTA) with SMTP id 9A.48.64580.95C2D546; Thu, 11 May 2023 13:56:41 -0400 (EDT) Received: from SSI-EX2.ssi.samsung.com (105.128.2.227) by SSI-EX2.ssi.samsung.com (105.128.2.227) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.1.2375.24; Thu, 11 May 2023 10:56:40 -0700 Received: from SSI-EX2.ssi.samsung.com ([105.128.2.227]) by SSI-EX2.ssi.samsung.com ([105.128.2.227]) with mapi id 15.01.2375.024; Thu, 11 May 2023 10:56:40 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [RFC 4/7] hw/mem/cxl_type3: Add DC extent representative to cxl type3 device Thread-Topic: [RFC 4/7] hw/mem/cxl_type3: Add DC extent representative to cxl type3 device Thread-Index: AQHZhDHwR5sIHyogW0GjyQHnw1WJeg== Date: Thu, 11 May 2023 17:56:40 +0000 Message-ID: <20230511175609.2091136-5-fan.ni@samsung.com> In-Reply-To: <20230511175609.2091136-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA02Sf0yMcRzH932e5+6ezo6npD6y9QuzhUvDPOXnDHtotpRhynKuR+Hu6K6I Pzg/Gi7Wkchz1i+x5JS7jHT9UJk4djVWSy1W4rpdxy4jzIXuOVv/vd7fz/v7+by/n31JPMAq CCH3qbJYtUqmiBSKiYfPvtkW7lywK23RudypdF7HfURfK+xE9N23RkRrTw0S9BnLF4xu/mgn 6KqybiHdwVkJ2n7JjtG3KgZxuv1iHbFmCtNZoBcwN7Xrmcdcv4g589T1TzU4MMbk/iNihrpr MabWOYwzhYYTzFdzaIJ4p3hFGqvYd5hVR6/aLc7oebfhUFF0jq7JINKi1nk6RJJALQH79y06 JCYDqDsInrs8OC9yMTD8bBbqkJ/X9EFvI/jCPQRWx2WMF6MIurkGES9uI/CU9XuvCKkIaNI9 8nIgtRietVV4++KUiwC3cYSYKEyntsNNj1vEm1LgXttZAc9SsBSd93oIai7YeurQBEuoWDBc yPeyHxUH908/xyYYUUEwZjV6GaeCoXeoBONz+0O5oQHnOQjG6wd87wmDgh9FPo6A92MOEX9X Cj2FV4Q8z4fbZU6cn+sPL64PEbx/JrRU9nh3AVSeH1QbTvoarYNP5gHf4FlwzfiG4Dcshyq3 mD9WQEnFA1+f5VD2uwbTozncpNjcpBjcpBjcpBiliKhCwdkajTKd1cSo2CNSjUypyValS+UH lWb077u9HG9T1qG6Xre0FWEkakVA4pGBEldFclqAJE129BirPpiqzlawmlY0iyQigyUxK1/I A6h0WRZ7gGUPser/VYz0C9FiSyTVwVufiC0HnF2LxYr1C6NU6tJ2bltKgfTXqdCUZLg6UD2/ 0dK3pbnxJ7Z0Wvj0oXyUGa4+mWs6MmhKCuVmRq24xJREd7kiEhTFs/sqN/rr3+61xyZmrBz+ 44nvXiQzy8fW7s5c13I8Icspr7+higsqfjWDW/a12jbF1askH7T05nUKornG/dyvnCTLaFif 9uzm0iv11s8eR3Lt+J72J5UdF9sHzNvDQuKKd5y4XEMsO6y/a0lEOoeryPam/FNXYKVjo57N Xm2KTVUMF7Q19V+vyakp2bTp3OYFynDniNGdlNm8plgYOhoiCG8aeWXc25BvKh0NO54ROPg6 vio1ktBkyGKicLVG9hfLNra63QMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBIsWRmVeSWpSXmKPExsWS2cA0UTdSJzbF4MsbQ4vu8xsYLaZPvcBo sfrmGkaLhqZHLBYtu98zWex/+pzFYtXCa2wW52edYrF4PvE5k8XSJY+YLY737mBx4Pa4MHkC q8fiBlePnbPusnu0HHkL5O15yeSx8eN/do8n1zYzeWx+/YLZY+rseo/Pm+QCuKK4bFJSczLL Uov07RK4Mm7ccyuYoV/RtW82ewPjIfUuRk4OCQETiccTzrF0MXJxCAmsZpQ43L2aEcL5xCjx 8f55NghnGaPE5sldjCAtbAKKEvu6trOB2CICxhLHDi9hBrGZBV6zSHy7yA1iCwuES5y/+oAR oiZGoq+9iQnC1pPYPaOTBcRmEVCVOHdjB1gNr4ClxOyefjBbCMj++HMnO4jNKWAlsaH5BFgv o4CYxPdTa5ggdolL3HoynwniBQGJJXvOM0PYohIvH/9jhbDlJSb/mMEGYStK3P/+kh2iV0/i xtQpbBC2tsSyha+ZIW4QlDg58wkLRL2kxMEVN1gmMErMQrJuFpL2WUjaZyFpX8DIsopRvLS4 ODe9otg4L7Vcrzgxt7g0L10vOT93EyMwMZz+dzhmB+O9Wx/1DjEycTAeYpTgYFYS4X27JDpF iDclsbIqtSg/vqg0J7X4EKM0B4uSOK9H7MR4IYH0xJLU7NTUgtQimCwTB6dUA5NAn3KvKs+E yrqqNVJT96RzmKY/adTRatY+tDAnqyrr65n2so0Tjp1d/7rWUdJdszO/7pr5f6+c6a94Sktk VlmVbZ26IPmDsJRQ3xL3meyhDHxJV1+dM+S04bCqY3KZeWVzV9Ce6I03M2smKBj/XLOXQ2kj V+SeXQmNIR+Mr83tMbKMnVt+dtKXH19P57K9F3PZ1ib2o9DOPoHVw8Zzu2xUwQrBqkSGj9Uy 7YErO0Ki17D4365XTFHQj7RLWyDdFPrZlr0r3iDh1+xtW9sVuBalRyurCnx1rZj33fLVjfA9 08TL5NP3efOpKuv2ecxw6V/w9/bWWN4Fug4/bj6qrnfgWftGqmy577Nn39KVWIozEg21mIuK EwESj5NeewMAAA== X-CMS-MailID: 20230511175641uscas1p2b70d27b1f20dc2dd54a0530170117530 CMS-TYPE: 301P X-CMS-RootMailID: 20230511175641uscas1p2b70d27b1f20dc2dd54a0530170117530 References: <20230511175609.2091136-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.11; envelope-from=fan.ni@samsung.com; helo=mailout1.w2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Fan Ni Add dynamic capacity extent information to the definition of CXLType3Dev and add get DC extent list mailbox command based on CXL.spec.3.0:.8.2.9.8.9.2. With this command, we can create dc regions as below: region=$(cat /sys/bus/cxl/devices/decoder0.0/create_dc_region) echo $region> /sys/bus/cxl/devices/decoder0.0/create_dc_region echo 256 > /sys/bus/cxl/devices/$region/interleave_granularity echo 1 > /sys/bus/cxl/devices/$region/interleave_ways echo "dc" >/sys/bus/cxl/devices/decoder2.0/mode echo 0x30000000 >/sys/bus/cxl/devices/decoder2.0/dpa_size echo 0x30000000 > /sys/bus/cxl/devices/$region/size echo "decoder2.0" > /sys/bus/cxl/devices/$region/target0 echo 1 > /sys/bus/cxl/devices/$region/commit echo $region > /sys/bus/cxl/drivers/cxl_region/bind Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 73 ++++++++++++++++++++++++++++++++++++- hw/mem/cxl_type3.c | 1 + include/hw/cxl/cxl_device.h | 23 ++++++++++++ 3 files changed, 96 insertions(+), 1 deletion(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 61c77e52d8..ed2ac154cb 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -83,6 +83,7 @@ enum { #define CLEAR_POISON 0x2 DCD_CONFIG = 0x48, /*8.2.9.8.9*/ #define GET_DC_REGION_CONFIG 0x0 + #define GET_DYN_CAP_EXT_LIST 0x1 PHYSICAL_SWITCH = 0x51 #define IDENTIFY_SWITCH_DEVICE 0x0 }; @@ -938,7 +939,7 @@ static CXLRetCode cmd_media_clear_poison(struct cxl_cmd *cmd, } /* - * cxl spec 3.0: 8.2.9.8.9.2 + * cxl spec 3.0: 8.2.9.8.9.1 * Get Dynamic Capacity Configuration **/ static CXLRetCode cmd_dcd_get_dyn_cap_config(struct cxl_cmd *cmd, @@ -1001,6 +1002,73 @@ static CXLRetCode cmd_dcd_get_dyn_cap_config(struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } +/* + * cxl spec 3.0: 8.2.9.8.9.2 + * Get Dynamic Capacity Extent List (Opcode 4810h) + **/ +static CXLRetCode cmd_dcd_get_dyn_cap_ext_list(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, + uint16_t *len) +{ + struct get_dyn_cap_ext_list_in_pl { + uint32_t extent_cnt; + uint32_t start_extent_id; + } QEMU_PACKED; + + struct get_dyn_cap_ext_list_out_pl { + uint32_t count; + uint32_t total_extents; + uint32_t generation_num; + uint8_t rsvd[4]; + struct { + uint64_t start_dpa; + uint64_t len; + uint8_t tag[0x10]; + uint16_t shared_seq; + uint8_t rsvd[6]; + } QEMU_PACKED records[]; + } QEMU_PACKED; + + struct get_dyn_cap_ext_list_in_pl *in = (void *)cmd->payload; + struct get_dyn_cap_ext_list_out_pl *out = (void *)cmd->payload; + struct CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); + uint16_t record_count = 0, i = 0, record_done = 0; + CXLDCDExtentList *extent_list = &ct3d->dc.extents; + CXLDCD_Extent *ent; + uint16_t out_pl_len; + + if (in->start_extent_id > ct3d->dc.total_extent_count) + return CXL_MBOX_INVALID_INPUT; + + if (ct3d->dc.total_extent_count - in->start_extent_id < in->extent_cnt) + record_count = ct3d->dc.total_extent_count - in->start_extent_id; + else + record_count = in->extent_cnt; + + out_pl_len = sizeof(*out) + record_count * sizeof(out->records[0]); + assert(out_pl_len <= CXL_MAILBOX_MAX_PAYLOAD_SIZE); + + memset(out, 0, out_pl_len); + stl_le_p(&out->count, record_count); + stl_le_p(&out->total_extents, ct3d->dc.total_extent_count); + stl_le_p(&out->generation_num, ct3d->dc.ext_list_gen_seq); + + QTAILQ_FOREACH(ent, extent_list, node) { + if (i++ < in->start_extent_id) + continue; + stq_le_p(&out->records[i].start_dpa, ent->start_dpa); + stq_le_p(&out->records[i].len, ent->len); + memcpy(&out->records[i].tag, ent->tag, 0x10); + stw_le_p(&out->records[i].shared_seq, ent->shared_seq); + record_done++; + if (record_done == record_count) + break; + } + + *len = out_pl_len; + return CXL_MBOX_SUCCESS; +} + #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_DATA_CHANGE (1 << 2) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -1041,6 +1109,9 @@ static struct cxl_cmd cxl_cmd_set[256][256] = { cmd_media_clear_poison, 72, 0 }, [DCD_CONFIG][GET_DC_REGION_CONFIG] = { "DCD_GET_DC_REGION_CONFIG", cmd_dcd_get_dyn_cap_config, 2, 0 }, + [DCD_CONFIG][GET_DYN_CAP_EXT_LIST] = { + "DCD_GET_DYNAMIC_CAPACITY_EXTENT_LIST", cmd_dcd_get_dyn_cap_ext_list, + 8, 0 }, }; static struct cxl_cmd cxl_cmd_set_sw[256][256] = { diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index b9c375d9b4..23954711b5 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -708,6 +708,7 @@ static int cxl_create_toy_regions(CXLType3Dev *ct3d) region_base += region->len; } + QTAILQ_INIT(&ct3d->dc.extents); return 0; } diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 8a04e53e90..20ad5e7411 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -385,6 +385,25 @@ typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; #define DCD_MAX_REGION_NUM 8 +typedef struct CXLDCD_Extent_raw { + uint64_t start_dpa; + uint64_t len; + uint8_t tag[0x10]; + uint16_t shared_seq; + uint8_t rsvd[0x6]; +} QEMU_PACKED CXLDCExtent_raw; + +typedef struct CXLDCD_Extent { + uint64_t start_dpa; + uint64_t len; + uint8_t tag[0x10]; + uint16_t shared_seq; + uint8_t rsvd[0x6]; + + QTAILQ_ENTRY(CXLDCD_Extent) node; +} CXLDCD_Extent; +typedef QTAILQ_HEAD(, CXLDCD_Extent) CXLDCDExtentList; + typedef struct CXLDCD_Region { uint64_t base; uint64_t decode_len; /* in multiples of 256MB */ @@ -429,6 +448,10 @@ struct CXLType3Dev { struct dynamic_capacity { uint8_t num_regions; // 1-8 struct CXLDCD_Region regions[DCD_MAX_REGION_NUM]; + CXLDCDExtentList extents; + + uint32_t total_extent_count; + uint32_t ext_list_gen_seq; } dc; }; From patchwork Thu May 11 17:56:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fan Ni X-Patchwork-Id: 13238292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B83E2C77B7F for ; Thu, 11 May 2023 17:58:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pxAX8-0003lo-Me; Thu, 11 May 2023 13:56:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxAX4-0003en-QK for qemu-devel@nongnu.org; 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Thu, 11 May 2023 10:56:41 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [RFC 5/7] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response Thread-Topic: [RFC 5/7] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response Thread-Index: AQHZhDHwpHEBWsJ1h0+7w9AQAuHaPg== Date: Thu, 11 May 2023 17:56:40 +0000 Message-ID: <20230511175609.2091136-6-fan.ni@samsung.com> In-Reply-To: <20230511175609.2091136-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNKsWRmVeSWpSXmKPExsWy7djX87pROrEpBj8mCVh0n9/AaDF96gVG i9U31zBaNDQ9YrFo2f2eyWL/0+csFqsWXmOzOD/rFIvF84nPmSyWLnnEbHG8dweLA7fHhckT WD0WN7h67Jx1l92j5chbIG/PSyaPjR//s3s8ubaZyWPz6xfMHlNn13t83iQXwBXFZZOSmpNZ llqkb5fAlbG5ZQNrwTznivajZ9gaGBeZdTFyckgImEg8utvC3MXIxSEksJJRYvqfVcwgCSGB ViaJT5v0YIp625+zQxStZZQ4umUilPOJUWLt2x+sEM4yRon33/eAtbMJKErs69rOBmKLCBhL HDu8BGwHs8BbFomPa96wgCSEBUoknt1axgJRVCmxYlcfVIOexLbevWCDWARUJc7d2MEIYvMK WEp823SaHcTmFLCS2NB8ggnEZhQQk/h+ag2YzSwgLnHryXwmiLsFJRbNhjhIAqjm366HbBC2 vMTkHzOgbEWJ+99fskP06kncmDqFDcLWlli28DUzxF5BiZMzn7BA1EtKHFxxgwXkGQmBfk6J +UuPQyVcJHZuOAC1WFri791lQDYHkJ0sseojF0Q4R2L+ki1Q5dYSC/+sZ5rAqDILydmzkJwx C8kZs5CcsYCRZRWjeGlxcW56arFhXmq5XnFibnFpXrpecn7uJkZgejv973DuDsYdtz7qHWJk 4mA8xCjBwawkwvt2SXSKEG9KYmVValF+fFFpTmrxIUZpDhYlcV5D25PJQgLpiSWp2ampBalF MFkmDk6pBiYP9SsMyy5vC9Q92spiah0npXf6x2rRY5KRm3inGe/5eGbukmv6ObWeoQdW6cWf qb3sfKlyxrNH/S1/n/762fWC43D0ikvV2YHvHpmdDv92s2BudfuTAL45mU3cDB8XNTyXuiD5 0Oj1JI0VGwIVhI84lXJcmKob1xX7TH2Z64VTE7nO73vwxpgzkLtejzk5y/zpRB2l+Q/0Zplv 3cOmeV3Tfu5CNebIOq8jiUFZ0o/9cuICn28oEJ2Wt94v7dNEg1vh9yMnVL+QP7ryBFvqj1qf rkiz824zDy/9qmeU0Kq5cqbR/v+RDPvKRO/+yn3492Px42mfl7ieulBwct1Xx80Zv63mLbTU nRd/Zl7On1nLlViKMxINtZiLihMBYvfvw94DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJIsWRmVeSWpSXmKPExsWS2cA0UTdSJzbF4NV0I4vu8xsYLaZPvcBo sfrmGkaLhqZHLBYtu98zWex/+pzFYtXCa2wW52edYrF4PvE5k8XSJY+YLY737mBx4Pa4MHkC q8fiBlePnbPusnu0HHkL5O15yeSx8eN/do8n1zYzeWx+/YLZY+rseo/Pm+QCuKK4bFJSczLL Uov07RK4Mja3bGAtmOdc0X70DFsD4yKzLkZODgkBE4ne9ufsXYxcHEICqxklfnyYBOV8YpTo 6Z/CCuEsY5Ro3LqOFaSFTUBRYl/XdjYQW0TAWOLY4SXMIDazwGsWiW8XuUFsYYESiWe3lrFA 1FRK/L//hBHC1pPY1rsXrJ5FQFXi3I0dYHFeAUuJb5tOs4PYQkD2x587wWxOASuJDc0nmEBs RgExie+n1jBB7BKXuPVkPhPECwISS/acZ4awRSVePv7HCmHLS0z+MYMNwlaUuP/9JTtEr57E jalT2CBsbYllC18zQ9wgKHFy5hMWiHpJiYMrbrBMYJSYhWTdLCTts5C0z0LSvoCRZRWjeGlx cW56RbFRXmq5XnFibnFpXrpecn7uJkZgajj973D0Dsbbtz7qHWJk4mA8xCjBwawkwvt2SXSK EG9KYmVValF+fFFpTmrxIUZpDhYlcd6XURPjhQTSE0tSs1NTC1KLYLJMHJxSDUysp4OWLPoe ffTE+/ZJ3zeaizH+Nm+8nni+OWfd0y+RaYYf6rb0XHxy3YJB1TzkzuHJhcr5W/Z7aq6W/s/h acB2LSvy5Ju10Wum2PEF/1rSxB70VivGasGOC6lnVE6yVqkmt7BMOBxhW976SKhAbdLnh58X MjwrXuHk+dpfMlOJx2K1bzJX/BajyTUrp0Zc0Dt3q7NB8cKCzT9n7r6bUMAvZP5shk2giIFN Kt8Oh5ow91+LW512LWN8yzvFRvrjxMuPqr8u17a6nDqbyVG348R1Jkk/6c1PDu8IUWINqtyZ vrDLtbPI/nGxebGNcMYV9pArNzMfbo/KfV1Sa7LCeMPETSHBBxVqNL/y1XD7ZCmxFGckGmox FxUnAgAMiTOtfAMAAA== X-CMS-MailID: 20230511175642uscas1p1a998a2d4a20c370f0172db93d537ed39 CMS-TYPE: 301P X-CMS-RootMailID: 20230511175642uscas1p1a998a2d4a20c370f0172db93d537ed39 References: <20230511175609.2091136-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.12; envelope-from=fan.ni@samsung.com; helo=mailout2.w2.samsung.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Fan Ni Per CXL spec 3.0, we implemented the two mailbox commands: Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and Release Dynamic Capacity Response (Opcode 4803h) 8.2.9.8.9.4. Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 223 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 3 +- 2 files changed, 225 insertions(+), 1 deletion(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index ed2ac154cb..7212934627 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -84,6 +84,8 @@ enum { DCD_CONFIG = 0x48, /*8.2.9.8.9*/ #define GET_DC_REGION_CONFIG 0x0 #define GET_DYN_CAP_EXT_LIST 0x1 + #define ADD_DYN_CAP_RSP 0x2 + #define RELEASE_DYN_CAP 0x3 PHYSICAL_SWITCH = 0x51 #define IDENTIFY_SWITCH_DEVICE 0x0 }; @@ -1069,6 +1071,221 @@ static CXLRetCode cmd_dcd_get_dyn_cap_ext_list(struct cxl_cmd *cmd, return CXL_MBOX_SUCCESS; } +static inline int test_bits(const unsigned long *addr, int nr, int size) +{ + unsigned long res = find_next_zero_bit(addr, size + nr, nr); + + if (res >= nr + size) + return 1; + else + return 0; +} + +static uint8_t find_region_id(struct CXLType3Dev *dev, uint64_t dpa + , uint64_t len) +{ + int8_t i = dev->dc.num_regions-1; + + while (i > 0 && dpa < dev->dc.regions[i].base) + i--; + + if (dpa < dev->dc.regions[i].base + || dpa + len > dev->dc.regions[i].base + dev->dc.regions[i].len) + return dev->dc.num_regions; + + return i; +} + +static CXLRetCode detect_malformed_extent_list(CXLType3Dev *dev, void *data) +{ + struct updated_dc_extent_list_in_pl { + uint32_t num_entries_updated; + uint8_t rsvd[4]; + struct { + uint64_t start_dpa; + uint64_t len; + uint8_t rsvd[8]; + } QEMU_PACKED updated_entries[]; + } QEMU_PACKED; + + struct updated_dc_extent_list_in_pl *in = data; + unsigned long *blk_bitmap; + uint64_t min_block_size = dev->dc.regions[0].block_size; + struct CXLDCD_Region *region = &dev->dc.regions[0]; + uint32_t i; + uint64_t dpa, len; + uint8_t rid; + + for (i = 1; i < dev->dc.num_regions; i++) { + region = &dev->dc.regions[i]; + if (min_block_size > region->block_size) + min_block_size = region->block_size; + } + blk_bitmap = bitmap_new((region->len + region->base + - dev->dc.regions[0].base) / min_block_size); + g_assert(blk_bitmap); + bitmap_zero(blk_bitmap, (region->len + region->base + - dev->dc.regions[0].base) / min_block_size); + + for (i = 0; i < in->num_entries_updated; i++) { + dpa = in->updated_entries[i].start_dpa; + len = in->updated_entries[i].len; + + rid = find_region_id(dev, dpa, len); + if (rid == dev->dc.num_regions) { + g_free(blk_bitmap); + return CXL_MBOX_INVALID_PA; + } + region = &dev->dc.regions[rid]; + if (dpa % region->block_size || len % region->block_size) { + g_free(blk_bitmap); + return CXL_MBOX_INVALID_EXTENT_LIST; + } + /* the dpa range already covered by some other extents in the list */ + if (test_bits(blk_bitmap, dpa/min_block_size, len/min_block_size)) { + g_free(blk_bitmap); + return CXL_MBOX_INVALID_EXTENT_LIST; + } + bitmap_set(blk_bitmap, dpa/min_block_size, len/min_block_size); + } + + g_free(blk_bitmap); + return CXL_MBOX_SUCCESS; +} + +/* + * cxl spec 3.0: 8.2.9.8.9.3 + * Add Dynamic Capacity Response (opcode 4802h) + * Assuming extent list is updated when a extent is added, when receiving + * the response, verify and ensure the extent is utilized by the host, and + * update extent list as needed. + **/ +static CXLRetCode cmd_dcd_add_dyn_cap_rsp(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, + uint16_t *len_unused) +{ + struct add_dyn_cap_ext_list_in_pl { + uint32_t num_entries_updated; + uint8_t rsvd[4]; + struct { + uint64_t start_dpa; + uint64_t len; + uint8_t rsvd[8]; + } QEMU_PACKED updated_entries[]; + } QEMU_PACKED; + + struct add_dyn_cap_ext_list_in_pl *in = (void *)cmd->payload; + struct CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); + CXLDCDExtentList *extent_list = &ct3d->dc.extents; + CXLDCD_Extent *ent; + uint32_t i; + uint64_t dpa, len; + CXLRetCode rs; + + if (in->num_entries_updated == 0) + return CXL_MBOX_SUCCESS; + + rs = detect_malformed_extent_list(ct3d, in); + if (rs != CXL_MBOX_SUCCESS) + return rs; + + for (i = 0; i < in->num_entries_updated; i++) { + dpa = in->updated_entries[i].start_dpa; + len = in->updated_entries[i].len; + + /* Todo: check following + * One or more of the updated extent lists contain Starting DPA + * or Lengths that are out of range of a current extent list + * maintained by the device. + **/ + + QTAILQ_FOREACH(ent, extent_list, node) { + if (ent->start_dpa == dpa && ent->len == len) + return CXL_MBOX_INVALID_PA; + if (ent->start_dpa <= dpa + && dpa + len <= ent->start_dpa + ent->len) { + ent->start_dpa = dpa; + ent->len = len; + break; + } else if ((dpa < ent->start_dpa + ent->len + && dpa + len > ent->start_dpa + ent->len) + || (dpa < ent->start_dpa && dpa + len > ent->start_dpa)) + return CXL_MBOX_INVALID_EXTENT_LIST; + } + // a new extent added + if (!ent) { + ent = g_new0(CXLDCD_Extent, 1); + assert(ent); + ent->start_dpa = dpa; + ent->len = len; + memset(ent->tag, 0, 0x10); + ent->shared_seq = 0; + QTAILQ_INSERT_TAIL(extent_list, ent, node); + } + } + + return CXL_MBOX_SUCCESS; +} + +/* + * Spec 3.0: 8.2.9.8.9.4 + * Release Dynamic Capacity (opcode 4803h) + **/ +static CXLRetCode cmd_dcd_release_dcd_capacity(struct cxl_cmd *cmd, + CXLDeviceState *cxl_dstate, + uint16_t *len_unused) +{ + struct release_dcd_cap_in_pl { + uint32_t num_entries_updated; + uint8_t rsvd[4]; + struct { + uint64_t start_dpa; + uint64_t len; + uint8_t rsvd[8]; + } QEMU_PACKED updated_entries[]; + } QEMU_PACKED; + + struct release_dcd_cap_in_pl *in = (void *)cmd->payload; + struct CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); + CXLDCDExtentList *extent_list = &ct3d->dc.extents; + CXLDCD_Extent *ent; + uint32_t i; + uint64_t dpa, len; + CXLRetCode rs; + + if (in->num_entries_updated == 0) + return CXL_MBOX_INVALID_INPUT; + + rs = detect_malformed_extent_list(ct3d, in); + if (rs != CXL_MBOX_SUCCESS) + return rs; + + /* Todo: check following + * One or more of the updated extent lists contain Starting DPA + * or Lengths that are out of range of a current extent list + * maintained by the device. + **/ + + for (i = 0; i < in->num_entries_updated; i++) { + dpa = in->updated_entries[i].start_dpa; + len = in->updated_entries[i].len; + + QTAILQ_FOREACH(ent, extent_list, node) { + if (ent->start_dpa == dpa && ent->len == len) + break; + else if ((dpa < ent->start_dpa + ent->len + && dpa + len > ent->start_dpa + ent->len) + || (dpa < ent->start_dpa && dpa + len > ent->start_dpa)) + return CXL_MBOX_INVALID_EXTENT_LIST; + } + /* found the entry, release it */ + if (ent) + QTAILQ_REMOVE(extent_list, ent, node); + } + + return CXL_MBOX_SUCCESS; +} + #define IMMEDIATE_CONFIG_CHANGE (1 << 1) #define IMMEDIATE_DATA_CHANGE (1 << 2) #define IMMEDIATE_POLICY_CHANGE (1 << 3) @@ -1112,6 +1329,12 @@ static struct cxl_cmd cxl_cmd_set[256][256] = { [DCD_CONFIG][GET_DYN_CAP_EXT_LIST] = { "DCD_GET_DYNAMIC_CAPACITY_EXTENT_LIST", cmd_dcd_get_dyn_cap_ext_list, 8, 0 }, + [DCD_CONFIG][ADD_DYN_CAP_RSP] = { + "ADD_DCD_DYNAMIC_CAPACITY_RESPONSE", cmd_dcd_add_dyn_cap_rsp, + ~0, IMMEDIATE_DATA_CHANGE }, + [DCD_CONFIG][RELEASE_DYN_CAP] = { + "RELEASE_DCD_DYNAMIC_CAPACITY", cmd_dcd_release_dcd_capacity, + ~0, IMMEDIATE_DATA_CHANGE }, }; static struct cxl_cmd cxl_cmd_set_sw[256][256] = { diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 20ad5e7411..c0c8fcc24b 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -131,7 +131,8 @@ typedef enum { CXL_MBOX_INCORRECT_PASSPHRASE = 0x14, CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15, CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16, - CXL_MBOX_MAX = 0x17 + CXL_MBOX_INVALID_EXTENT_LIST = 0x17, + CXL_MBOX_MAX = 0x18 } CXLRetCode; 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Thu, 11 May 2023 10:56:41 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [RFC 6/7] Add qmp interfaces to add/release dynamic capacity extents Thread-Topic: [RFC 6/7] Add qmp interfaces to add/release dynamic capacity extents Thread-Index: AQHZhDHweOj1egr3rka/i5lzMWKESQ== Date: Thu, 11 May 2023 17:56:40 +0000 Message-ID: <20230511175609.2091136-7-fan.ni@samsung.com> In-Reply-To: <20230511175609.2091136-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrDKsWRmVeSWpSXmKPExsWy7djXc7pROrEpBu+vSFp0n9/AaDF96gVG i9U31zBaNDQ9YrFo2f2eyWL/0+csFqsWXmOzOD/rFIvF84nPmSyWLnnEbHG8dweLA7fHhckT WD0WN7h67Jx1l92j5chbIG/PSyaPjR//s3s8ubaZyWPz6xfMHlNn13t83iQXwBXFZZOSmpNZ llqkb5fAlfFr0Tm2gu1WFQt+tzE3MP7T62Lk5JAQMJG43XaQrYuRi0NIYCWjxJltT9khnFYm iXdzZ7LBVN1Y8B0qsZZR4v+9FcwQzidGiabTL1khnGWMEu+/72EGaWETUJTY17UdrF1EwFji 2OElYB3MAm9ZJD6uecMCkhAW8JeY3nuaHaIoROLP78OsELaeRNeEv2A1LAKqEudu7GAEsXkF LCX6DnxlArE5BawkNjSfALMZBcQkvp9aA2YzC4hL3HoynwnibkGJRbMhDpIAqvm36yHUP/IS k3/MgLIVJe5/f8kO0asncWPqFDYIW1ti2cLXzBB7BSVOznzCAlEvKXFwxQ0WkGckBPo5JebM OgE1yEWip7uFHcKWlrh6fSpQMweQnSyx6iMXRDhHYv6SLVBzrCUW/lnPNIFRZRaSs2chOWMW kjNmITljASPLKkbx0uLi3PTUYuO81HK94sTc4tK8dL3k/NxNjMAEd/rf4YIdjLdufdQ7xMjE wXiIUYKDWUmE9+2S6BQh3pTEyqrUovz4otKc1OJDjNIcLErivIa2J5OFBNITS1KzU1MLUotg skwcnFINTJGSdY3TFNOzL9n1L9TYuMuW62/TsdsbAllsNhYmBrEVh1+8dP9Yv5JOUYDQYs0Z /lsNZJ07s3nf7/H2dQrdKsFxTnYl332ucp8f0/eJSTVtXTmTK+6oxBL5OY/OXJNl6L86S1k2 3tuAYYt+4wr7Fdxf3jImLk/+f7xT97apzuTabftadtv0n+n8OY0p8vdh+UCXFyr+VgccNHZ7 3Vi53Of8ZrOKTaLhcXs574mtTVHp1Juzy6Hydcg7KauEu4/mcyzpnrZFeeWf1A/vOm9m3ink rLfh/sun8YnVIO9ozhH+bVzHQqafKngUWT/nwT6ODvWQf26vZm9gXy7XJNcRExm+rqNatKpS ZnPTNh5hJZbijERDLeai4kQAxEcGL98DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJIsWRmVeSWpSXmKPExsWS2cA0STdKJzbF4P5EFovu8xsYLaZPvcBo sfrmGkaLhqZHLBYtu98zWex/+pzFYtXCa2wW52edYrF4PvE5k8XSJY+YLY737mBx4Pa4MHkC q8fiBlePnbPusnu0HHkL5O15yeSx8eN/do8n1zYzeWx+/YLZY+rseo/Pm+QCuKK4bFJSczLL Uov07RK4Mn4tOsdWsN2qYsHvNuYGxn96XYycHBICJhI3Fnxn72Lk4hASWM0osXVnMyuE84lR 4t7SgywQzjJGicat61hBWtgEFCX2dW1nA7FFBIwljh1ewgxiMwu8ZpH4dpEbxBYW8JXo3b2G BaImROLWlqPMELaeRNeEv2BxFgFViXM3djCC2LwClhJ9B74ygdhCQPbHnzvZQWxOASuJDc0n wOKMAmIS30+tYYLYJS5x68l8JogXBCSW7DnPDGGLSrx8/I8VwpaXmPxjBhuErShx//tLdohe PYkbU6ewQdjaEssWvmaGuEFQ4uTMJywQ9ZISB1fcYJnAKDELybpZSNpnIWmfhaR9ASPLKkbx 0uLi3PSKYsO81HK94sTc4tK8dL3k/NxNjMDUcPrf4cgdjEdvfdQ7xMjEwXiIUYKDWUmE9+2S 6BQh3pTEyqrUovz4otKc1OJDjNIcLErivEKuE+OFBNITS1KzU1MLUotgskwcnFINTPJfu1Qs cjmjYovv9ZWWLQ0L2sPrsuFGZPGZUxmLo/Xy51s12WjFfpR682qlxdRfZZlJz9vPHG82PaSp LO175VVraZVOsaOVWXSJiv93J6EwqZKZ4mdDJl7eeuTqEZdvQfNvvfNmb9ug3LZT5n/5dklt s+r7c+ys+PZYtX56UOydejLD2qQ8Ra6Pz9ZOW26WUExrvqOM2+J+/7X5sSnrVx0wyo1jljgp 8mXH9EupysYfnabzB/bPsJZXY1yw9IpZmfSPfTJ3LY3ucM01cU3Yq/Jqzm/VmMzEihoeo23v 3M09RCq4++MTNzgxC5Vs+LzwdfLOyqNzmiP2fZSU1737rWXCQfvKU4ddJB099iuxFGckGmox FxUnAgD6twOCfAMAAA== X-CMS-MailID: 20230511175642uscas1p27cf2915c8184225bfd581fb6f6dfb2d9 CMS-TYPE: 301P X-CMS-RootMailID: 20230511175642uscas1p27cf2915c8184225bfd581fb6f6dfb2d9 References: <20230511175609.2091136-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.12; envelope-from=fan.ni@samsung.com; helo=mailout2.w2.samsung.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Fan Ni Since fabric manager emulation is not supported yet, the change implements the functions to add/release dynamic capacity extents as QMP interfaces. 1. Add dynamic capacity extents: For example, the command to add two continuous extents (each is 128MB long) to region 0 (starting at dpa offset 0) looks like below: { "execute": "qmp_capabilities" } { "execute": "cxl-add-dynamic-capacity-event", "arguments": { "path": "/machine/peripheral/cxl-pmem0", "region-id" : 0, "num-extent": 2, "dpa":0, "extent-len": 128 } } 2. Release dynamic capacity extents: For example, the command to release an extent of size 128MB from region 0 (starting at dpa offset 0) look like below: { "execute": "cxl-release-dynamic-capacity-event", "arguments": { "path": "/machine/peripheral/cxl-pmem0", "region-id" : 0, "num-extent": 1 , "dpa":0, "extent-len": 128 } } Signed-off-by: Fan Ni --- hw/mem/cxl_type3.c | 127 ++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_events.h | 16 +++++ qapi/cxl.json | 44 +++++++++++++ 3 files changed, 187 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 23954711b5..70d47d43b9 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1651,6 +1651,133 @@ void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log, } } +static const QemuUUID dynamic_capacity_uuid = { + .data = UUID(0xca95afa7, 0xf183, 0x4018, 0x8c, 0x2f, + 0x95, 0x26, 0x8e, 0x10, 0x1a, 0x2a), +}; + +static void qmp_cxl_process_dynamic_capacity_event(const char *path, CxlEventLog log, + uint8_t flags, uint8_t type, uint16_t hid, uint8_t rid, uint32_t extent_cnt, + CXLDCExtent_raw *extents, Error **errp) +{ + Object *obj = object_resolve_path(path, NULL); + CXLEventDynamicCapacity dCap; + CXLEventRecordHdr *hdr = &dCap.hdr; + CXLDeviceState *cxlds; + CXLType3Dev *dcd; + int i; + + if (!obj) { + error_setg(errp, "Unable to resolve path"); + return; + } + if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) { + error_setg(errp, "Path not point to a valid CXL type3 device"); + return; + } + + dcd = CXL_TYPE3(obj); + cxlds = &dcd->cxl_dstate; + memset(&dCap, 0, sizeof(dCap)); + + if (!dcd->dc.num_regions) { + error_setg(errp, "No dynamic capacity support from the device"); + return; + } + + /* + * 8.2.9.1.5 + * All Dynamic Capacity event records shall set the Event Record + * Severity field in the Common Event Record Format to Informational + * Event. All Dynamic Capacity related events shall be logged in the + * Dynamic Capacity Event Log. + */ + assert(flags & (1<dc.regions[rid].base; + memcpy(&dCap.dynamic_capacity_extent, &extents[i] + , sizeof(CXLDCExtent_raw)); + + if (cxl_event_insert(cxlds, CXL_EVENT_TYPE_DYNAMIC_CAP, + (CXLEventRecordRaw *)&dCap)) { + ; + } + cxl_event_irq_assert(dcd); + } +} + +#define MEM_BLK_SIZE_MB 128 +void qmp_cxl_add_dynamic_capacity_event(const char *path, uint8_t region_id, + uint32_t num_exent, uint64_t dpa, uint64_t extent_len_MB, Error **errp) +{ + uint8_t flags = 1 << CXL_EVENT_TYPE_INFO; + CXLDCExtent_raw *extents; + int i; + + if (extent_len_MB < MEM_BLK_SIZE_MB) { + error_setg(errp, + "extent size cannot be smaller than memory block size (%dMB)", + MEM_BLK_SIZE_MB); + return; + } + + extents = g_new0(CXLDCExtent_raw, num_exent); + for (i = 0; i < num_exent; i++) { + extents[i].start_dpa = dpa; + extents[i].len = extent_len_MB*1024*1024; + memset(extents[i].tag, 0, 0x10); + extents[i].shared_seq = 0; + dpa += extents[i].len; + } + + qmp_cxl_process_dynamic_capacity_event(path, CXL_EVENT_LOG_INFORMATIONAL, + flags, 0x0, 0, region_id, num_exent, extents, errp); + + g_free(extents); +} + +void qmp_cxl_release_dynamic_capacity_event(const char *path, uint8_t region_id, + uint32_t num_exent, uint64_t dpa, uint64_t extent_len_MB, Error **errp) +{ + uint8_t flags = 1 << CXL_EVENT_TYPE_INFO; + CXLDCExtent_raw *extents; + int i; + + if (extent_len_MB < MEM_BLK_SIZE_MB) { + error_setg(errp, + "extent size cannot be smaller than memory block size (%dMB)", + MEM_BLK_SIZE_MB); + return; + } + + extents = g_new0(CXLDCExtent_raw, num_exent); + for (i = 0; i < num_exent; i++) { + extents[i].start_dpa = dpa; + extents[i].len = extent_len_MB*1024*1024; + memset(extents[i].tag, 0, 0x10); + extents[i].shared_seq = 0; + dpa += extents[i].len; + } + + qmp_cxl_process_dynamic_capacity_event(path, CXL_EVENT_LOG_INFORMATIONAL, + flags, 0x1, 0, region_id, num_exent, extents, errp); + + g_free(extents); +} + static void ct3_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); diff --git a/include/hw/cxl/cxl_events.h b/include/hw/cxl/cxl_events.h index 089ba2091f..dd00458d1d 100644 --- a/include/hw/cxl/cxl_events.h +++ b/include/hw/cxl/cxl_events.h @@ -165,4 +165,20 @@ typedef struct CXLEventMemoryModule { uint8_t reserved[0x3d]; } QEMU_PACKED CXLEventMemoryModule; +/* + * Dynamic Capacity Event Record + * CXL Rev 3.0 Section 8.2.9.2.1.5: Table 8-47 + * All fields little endian. + */ +typedef struct CXLEventDynamicCapacity { + CXLEventRecordHdr hdr; + uint8_t type; + uint8_t reserved1; + uint16_t host_id; + uint8_t updated_region_id; + uint8_t reserved2[3]; + uint8_t dynamic_capacity_extent[0x28]; /* defined in cxl_device.h */ + uint8_t reserved[0x20]; +} QEMU_PACKED CXLEventDynamicCapacity; + #endif /* CXL_EVENTS_H */ diff --git a/qapi/cxl.json b/qapi/cxl.json index 8b3d30cd71..c9a9a45ce4 100644 --- a/qapi/cxl.json +++ b/qapi/cxl.json @@ -264,3 +264,47 @@ 'type': 'CxlCorErrorType' } } + +## +# @cxl-add-dynamic-capacity-event: +# +# Command to add dynamic capacity extent event +# +# @path: CXL DCD canonical QOM path +# @region-id: region id +# @num-extent: number of extents to add, test only +# @dpa: start dpa for the operation +# @extent-len: extent size in MB +# +# Since: 8.0 +## +{ 'command': 'cxl-add-dynamic-capacity-event', + 'data': { 'path': 'str', + 'region-id': 'uint8', + 'num-extent': 'uint32', + 'dpa':'uint64', + 'extent-len': 'uint64' + } +} + +## +# @cxl-release-dynamic-capacity-event: +# +# Command to add dynamic capacity extent event +# +# @path: CXL DCD canonical QOM path +# @region-id: region id +# @num-extent: number of extents to add, test only +# @dpa: start dpa for the operation +# @extent-len: extent size in MB +# +# Since: 8.0 +## +{ 'command': 'cxl-release-dynamic-capacity-event', + 'data': { 'path': 'str', + 'region-id': 'uint8', + 'num-extent': 'uint32', + 'dpa':'uint64', + 'extent-len': 'uint64' + } +} From patchwork Thu May 11 17:56:40 2023 Content-Type: text/plain; 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Thu, 11 May 2023 10:56:41 -0700 From: Fan Ni To: "qemu-devel@nongnu.org" CC: "jonathan.cameron@huawei.com" , "linux-cxl@vger.kernel.org" , "gregory.price@memverge.com" , "hchkuo@avery-design.com.tw" , "cbrowy@avery-design.com" , "ira.weiny@intel.com" , "dan.j.williams@intel.com" , Adam Manzanares , "dave@stgolabs.net" , "nmtadam.samsung@gmail.com" , "nifan@outlook.com" , Fan Ni Subject: [RFC 7/7] hw/mem/cxl_type3: add read/write support to dynamic capacity Thread-Topic: [RFC 7/7] hw/mem/cxl_type3: add read/write support to dynamic capacity Thread-Index: AQHZhDHw5brNkJs1s0eH0nh3056ZGw== Date: Thu, 11 May 2023 17:56:40 +0000 Message-ID: <20230511175609.2091136-8-fan.ni@samsung.com> In-Reply-To: <20230511175609.2091136-1-fan.ni@samsung.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.25.1 x-originating-ip: [105.128.2.176] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHKsWRmVeSWpSXmKPExsWy7djX87pROrEpBt8emlh0n9/AaDF96gVG i9U31zBaNDQ9YrFo2f2eyWL/0+csFqsWXmOzOD/rFIvF84nPmSyWLnnEbHG8dweLA7fHhckT WD0WN7h67Jx1l92j5chbIG/PSyaPjR//s3s8ubaZyWPz6xfMHlNn13t83iQXwBXFZZOSmpNZ llqkb5fAlfF3ahN7wabVjBWzVkxka2B80cLYxcjJISFgIvHr4B6mLkYuDiGBlYwSV+dMY4Nw WpkkNm5fxgxTdarzMStEYi2jxIITB6GqPjFKfLu/HcpZxijx/vsesBY2AUWJfV0gCU4OEQFj iWOHlzCDFDELvGWR+LjmDQtIQlggUGLFhGOMEEVhEp+On2eGsPUkFh7YBxZnEVCVOHdjB5jN K2Apcf/Yd3YQm1PASmJD8wkmEJtRQEzi+6k1YDazgLjErSfzmSDuFpRYNHsP1A9iEv92PWSD sOUlJv+YAWUrStz//pIdoldP4sbUKWwQtrbEsoWvmSH2CkqcnPmEBaJeUuLgihssIM9ICPRz SlxYfoEVIuEicWtLHzRYpSWmr7kMVMQBZCdLrPrIBRHOkZi/ZAvUHGuJhX/WM01gVJmF5OxZ SM6YheSMWUjOWMDIsopRvLS4ODc9tdgoL7Vcrzgxt7g0L10vOT93EyMwyZ3+dzh/B+P1Wx/1 DjEycTAeYpTgYFYS4X27JDpFiDclsbIqtSg/vqg0J7X4EKM0B4uSOK+h7clkIYH0xJLU7NTU gtQimCwTB6dUAxPjw98Nfc2JQg7nzj5asmn5qVkuBfI+iqrChjfnPZdaHVgf6jFjXePJv9uz tbcdV/xpnqetPuPyQ12GE2Z29WXccrmhQofmLDtvVqgp0R5eKvu8n+vXrb7XV22eB6xcfizP sGCltvPH8EnTIw7JK39WVWcPqzT4pXbt6//+ur9Xdl03Dc9t/8Pi4zQjOKG3va2qxFaP/WJn 5zkP4Q7BWo3CRUkvf0ksWf4xcep0Rgbr/98SUrvFCmstzqouXlri6SaQH2v2gGNG2l0Gc+WN xbnPP+w+vPTGZtNPM6p375+5VE7ryqUnutEP1sy9O3P6vRkaAd1R669O+ralqYNTPYaFe/LG xjdzKgt8fLJqipRYijMSDbWYi4oTAeiFzs3hAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsWS2cA0UTdKJzbF4N03fovu8xsYLaZPvcBo sfrmGkaLhqZHLBYtu98zWex/+pzFYtXCa2wW52edYrF4PvE5k8XSJY+YLY737mBx4Pa4MHkC q8fiBlePnbPusnu0HHkL5O15yeSx8eN/do8n1zYzeWx+/YLZY+rseo/Pm+QCuKK4bFJSczLL Uov07RK4Mv5ObWIv2LSasWLWiolsDYwvWhi7GDk5JARMJE51PmbtYuTiEBJYzShx/8wTKOcT o8T/lu1MEM4yRonGretYQVrYBBQl9nVtZwOxRQSMJY4dXsIMYjMLvGaR+HaRG8QWFgiUWDHh GCNETZhE85b/zBC2nsTCA/vA4iwCqhLnbuwAs3kFLCXuH/vODmILAdkff+4EszkFrCQ2NJ9g ArEZBcQkvp9awwSxS1zi1pP5TBAvCEgs2XOeGcIWlXj5+B8rhC0vMfnHDDYIW1Hi/veX7BC9 ehI3pk5hg7C1JZYtfM0McYOgxMmZT1gg6iUlDq64wTKBUWIWknWzkLTPQtI+C0n7AkaWVYzi pcXFuekVxcZ5qeV6xYm5xaV56XrJ+bmbGIHp4fS/wzE7GO/d+qh3iJGJg/EQowQHs5II79sl 0SlCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeT1iJ8YLCaQnlqRmp6YWpBbBZJk4OKUamHQvrPr7 5l+ckXRTid9TTsMn944JcVh/0LDNU2U+pbpP1UONd3KbjqNYpIalueHkv9PklLRnuP1S/8Gr ZTxHV1Nmq/gHi6CKa1Oq3UrLFTddNzkSlfOqWk8hTvtFPoO456m1DkLPmb41TPux41jEwTjd CaoBRZdstX1ME6RCG9NbrlWsTqm43t5ypPP6tJ35Mml2Vav2f03cwad77pP1gtcNxwvrW9Zs 4ovym1r3XXEO391cNnNzqxn72Duyj83c+en1x3nfG/i5dGT+h/Q9yeZ0VWfP+Zzye6fd/eA9 vgISe5RNxNYfqDUoevb8dUBP6ykJibtid1KzePzNnBn+77cP8k/R26IkJPN2jaUSS3FGoqEW c1FxIgDylzB5fgMAAA== X-CMS-MailID: 20230511175642uscas1p2c037608a1dd26b19cf970f97ce434c6d CMS-TYPE: 301P X-CMS-RootMailID: 20230511175642uscas1p2c037608a1dd26b19cf970f97ce434c6d References: <20230511175609.2091136-1-fan.ni@samsung.com> Received-SPF: pass client-ip=211.189.100.11; envelope-from=fan.ni@samsung.com; helo=mailout1.w2.samsung.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Fan Ni Before the change, read from or write to dynamic capacity of the memory device is not support as 1) no host backed file/memory is provided for it; 2) no address space is created for the dynamic capacity. With the change, add code to support following: 1. add a new property to type3 device "dc-memdev" to point to host memory backend for dynamic capacity; 2. add a bitmap for each region to track whether a block is host backed, which will be used for address check when read/write dynamic capacity; 3. add namespace for dynamic capacity for read/write support; 4. create cdat entries for each dynamic capacity region; Signed-off-by: Fan Ni --- hw/cxl/cxl-mailbox-utils.c | 21 ++- hw/mem/cxl_type3.c | 336 +++++++++++++++++++++++++++++------- include/hw/cxl/cxl_device.h | 8 +- 3 files changed, 298 insertions(+), 67 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 7212934627..efe61e67fb 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -391,9 +391,11 @@ static CXLRetCode cmd_firmware_update_get_info(struct cxl_cmd *cmd, char fw_rev4[0x10]; } QEMU_PACKED *fw_info; QEMU_BUILD_BUG_ON(sizeof(*fw_info) != 0x50); + CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); if ((cxl_dstate->vmem_size < CXL_CAPACITY_MULTIPLIER) || - (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER)) { + (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) || + (ct3d->dc.total_dynamic_capicity < CXL_CAPACITY_MULTIPLIER)) { return CXL_MBOX_INTERNAL_ERROR; } @@ -534,7 +536,9 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(ct3d); if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER)) || - (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))) { + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER)) || + (!QEMU_IS_ALIGNED(ct3d->dc.total_dynamic_capicity, + CXL_CAPACITY_MULTIPLIER))) { return CXL_MBOX_INTERNAL_ERROR; } @@ -543,7 +547,8 @@ static CXLRetCode cmd_identify_memory_device(struct cxl_cmd *cmd, snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); - stq_le_p(&id->total_capacity, cxl_dstate->mem_size / CXL_CAPACITY_MULTIPLIER); + stq_le_p(&id->total_capacity, + cxl_dstate->static_mem_size / CXL_CAPACITY_MULTIPLIER); stq_le_p(&id->persistent_capacity, cxl_dstate->pmem_size / CXL_CAPACITY_MULTIPLIER); stq_le_p(&id->volatile_capacity, cxl_dstate->vmem_size / CXL_CAPACITY_MULTIPLIER); stl_le_p(&id->lsa_size, cvc->get_lsa_size(ct3d)); @@ -568,9 +573,12 @@ static CXLRetCode cmd_ccls_get_partition_info(struct cxl_cmd *cmd, uint64_t next_pmem; } QEMU_PACKED *part_info = (void *)cmd->payload; QEMU_BUILD_BUG_ON(sizeof(*part_info) != 0x20); + CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate); if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER)) || - (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))) { + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER)) || + (!QEMU_IS_ALIGNED(ct3d->dc.total_dynamic_capicity, + CXL_CAPACITY_MULTIPLIER))) { return CXL_MBOX_INTERNAL_ERROR; } @@ -881,9 +889,8 @@ static CXLRetCode cmd_media_clear_poison(struct cxl_cmd *cmd, struct clear_poison_pl *in = (void *)cmd->payload; dpa = ldq_le_p(&in->dpa); - if (dpa + 64 > cxl_dstate->mem_size) { - return CXL_MBOX_INVALID_PA; - } + if (dpa + 64 > cxl_dstate->static_mem_size && ct3d->dc.num_regions == 0) + return CXL_MBOX_INVALID_PA; QLIST_FOREACH(ent, poison_list, node) { /* diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 70d47d43b9..334660bd0f 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -33,8 +33,8 @@ enum { }; static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, - int dsmad_handle, MemoryRegion *mr, - bool is_pmem, uint64_t dpa_base) + int dsmad_handle, uint8_t flags, + uint64_t dpa_base, uint64_t size) { g_autofree CDATDsmas *dsmas = NULL; g_autofree CDATDslbis *dslbis0 = NULL; @@ -53,9 +53,9 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, .length = sizeof(*dsmas), }, .DSMADhandle = dsmad_handle, - .flags = is_pmem ? CDAT_DSMAS_FLAG_NV : 0, + .flags = flags, .DPA_base = dpa_base, - .DPA_length = int128_get64(mr->size), + .DPA_length = size, }; /* For now, no memory side cache, plausiblish numbers */ @@ -137,9 +137,9 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, * NV: Reserved - the non volatile from DSMAS matters * V: EFI_MEMORY_SP */ - .EFI_memory_type_attr = is_pmem ? 2 : 1, + .EFI_memory_type_attr = flags ? 2 : 1, .DPA_offset = 0, - .DPA_length = int128_get64(mr->size), + .DPA_length = size, }; /* Header always at start of structure */ @@ -158,14 +158,15 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) g_autofree CDATSubHeader **table = NULL; CXLType3Dev *ct3d = priv; MemoryRegion *volatile_mr = NULL, *nonvolatile_mr = NULL; + MemoryRegion *dc_mr = NULL; int dsmad_handle = 0; int cur_ent = 0; int len = 0; int rc, i; + uint64_t vmr_size = 0, pmr_size = 0; - if (!ct3d->hostpmem && !ct3d->hostvmem) { - return 0; - } + if (!ct3d->hostpmem && !ct3d->hostvmem && !ct3d->dc.num_regions) + return 0; if (ct3d->hostvmem) { volatile_mr = host_memory_backend_get_memory(ct3d->hostvmem); @@ -173,6 +174,7 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) return -EINVAL; } len += CT3_CDAT_NUM_ENTRIES; + vmr_size = volatile_mr->size; } if (ct3d->hostpmem) { @@ -181,7 +183,19 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) return -EINVAL; } len += CT3_CDAT_NUM_ENTRIES; - } + pmr_size = nonvolatile_mr->size; + } + + if (ct3d->dc.num_regions) { + if (ct3d->dc.host_dc) { + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc); + if (!dc_mr) + return -EINVAL; + len += CT3_CDAT_NUM_ENTRIES * ct3d->dc.num_regions; + } else { + return -EINVAL; + } + } table = g_malloc0(len * sizeof(*table)); if (!table) { @@ -189,23 +203,45 @@ static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) } /* Now fill them in */ - if (volatile_mr) { - rc = ct3_build_cdat_entries_for_mr(table, dsmad_handle++, volatile_mr, - false, 0); - if (rc < 0) { - return rc; - } - cur_ent = CT3_CDAT_NUM_ENTRIES; - } + if (volatile_mr) { + rc = ct3_build_cdat_entries_for_mr(table, dsmad_handle++, + 0, 0, vmr_size); + if (rc < 0) + return rc; + cur_ent = CT3_CDAT_NUM_ENTRIES; + } + + if (nonvolatile_mr) { + rc = ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_handle++, + CDAT_DSMAS_FLAG_NV, vmr_size, pmr_size); + if (rc < 0) + goto error_cleanup; + cur_ent += CT3_CDAT_NUM_ENTRIES; + } + + if (dc_mr) { + uint64_t region_base = vmr_size + pmr_size; + + /* + * Currently we create cdat entries for each region, should we only + * create dsmas table instead?? + * We assume all dc regions are non-volatile for now. + * + */ + for (i = 0; i < ct3d->dc.num_regions; i++) { + rc = ct3_build_cdat_entries_for_mr(&(table[cur_ent]) + , dsmad_handle++ + , CDAT_DSMAS_FLAG_NV|CDAT_DSMAS_FLAG_DYNAMIC_CAP + , region_base, ct3d->dc.regions[i].len); + if (rc < 0) + goto error_cleanup; + ct3d->dc.regions[i].dsmadhandle = dsmad_handle-1; + + cur_ent += CT3_CDAT_NUM_ENTRIES; + region_base += ct3d->dc.regions[i].len; + } + } - if (nonvolatile_mr) { - rc = ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_handle++, - nonvolatile_mr, true, (volatile_mr ? volatile_mr->size : 0)); - if (rc < 0) { - goto error_cleanup; - } - cur_ent += CT3_CDAT_NUM_ENTRIES; - } assert(len == cur_ent); *cdat_table = g_steal_pointer(&table); @@ -706,6 +742,11 @@ static int cxl_create_toy_regions(CXLType3Dev *ct3d) /* dsmad_handle is set when creating cdat table entries */ region->flags = 0; + region->blk_bitmap = bitmap_new(region->len / region->block_size); + if (!region->blk_bitmap) + return -1; + bitmap_zero(region->blk_bitmap, region->len / region->block_size); + region_base += region->len; } QTAILQ_INIT(&ct3d->dc.extents); @@ -713,11 +754,24 @@ static int cxl_create_toy_regions(CXLType3Dev *ct3d) return 0; } +static void cxl_destroy_toy_regions(CXLType3Dev *ct3d) +{ + int i; + struct CXLDCD_Region *region; + + for (i = 0; i < ct3d->dc.num_regions; i++) { + region = &ct3d->dc.regions[i]; + if (region->blk_bitmap) + g_free(region->blk_bitmap); + } +} + static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { DeviceState *ds = DEVICE(ct3d); - if (!ct3d->hostmem && !ct3d->hostvmem && !ct3d->hostpmem) { + if (!ct3d->hostmem && !ct3d->hostvmem && !ct3d->hostpmem + && !ct3d->dc.num_regions) { error_setg(errp, "at least one memdev property must be set"); return false; } else if (ct3d->hostmem && ct3d->hostpmem) { @@ -754,7 +808,7 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) } address_space_init(&ct3d->hostvmem_as, vmr, v_name); ct3d->cxl_dstate.vmem_size = vmr->size; - ct3d->cxl_dstate.mem_size += vmr->size; + ct3d->cxl_dstate.static_mem_size += vmr->size; g_free(v_name); } @@ -777,12 +831,47 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) } address_space_init(&ct3d->hostpmem_as, pmr, p_name); ct3d->cxl_dstate.pmem_size = pmr->size; - ct3d->cxl_dstate.mem_size += pmr->size; + ct3d->cxl_dstate.static_mem_size += pmr->size; g_free(p_name); } - if (cxl_create_toy_regions(ct3d)) - return false; + ct3d->dc.total_dynamic_capicity = 0; + if (ct3d->dc.host_dc) { + MemoryRegion *dc_mr; + char *dc_name; + uint64_t total_region_size = 0; + int i; + + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc); + if (!dc_mr) { + error_setg(errp, "dynamic capacity must have backing device"); + return false; + } + /* FIXME: set dc as nonvolatile for now */ + memory_region_set_nonvolatile(dc_mr, true); + memory_region_set_enabled(dc_mr, true); + host_memory_backend_set_mapped(ct3d->dc.host_dc, true); + if (ds->id) { + dc_name = g_strdup_printf("cxl-dcd-dpa-dc-space:%s", ds->id); + } else { + dc_name = g_strdup("cxl-dcd-dpa-dc-space"); + } + address_space_init(&ct3d->dc.host_dc_as, dc_mr, dc_name); + + if (cxl_create_toy_regions(ct3d)) { + return false; + } + + for (i = 0; i < ct3d->dc.num_regions; i++) { + total_region_size += ct3d->dc.regions[i].len; + } + /* Make sure the host backend is large enough to cover all dc range */ + assert(total_region_size <= dc_mr->size); + assert(dc_mr->size % (256*1024*1024) == 0); + + ct3d->dc.total_dynamic_capicity = total_region_size; + g_free(dc_name); + } return true; } @@ -890,6 +979,10 @@ err_release_cdat: err_free_special_ops: g_free(regs->special_ops); err_address_space_free: + if (ct3d->dc.host_dc) { + cxl_destroy_toy_regions(ct3d); + address_space_destroy(&ct3d->dc.host_dc_as); + } if (ct3d->hostpmem) { address_space_destroy(&ct3d->hostpmem_as); } @@ -909,6 +1002,10 @@ static void ct3_exit(PCIDevice *pci_dev) cxl_doe_cdat_release(cxl_cstate); spdm_sock_fini(ct3d->doe_spdm.socket); g_free(regs->special_ops); + if (ct3d->dc.host_dc) { + cxl_destroy_toy_regions(ct3d); + address_space_destroy(&ct3d->dc.host_dc_as); + } if (ct3d->hostpmem) { address_space_destroy(&ct3d->hostpmem_as); } @@ -917,6 +1014,100 @@ static void ct3_exit(PCIDevice *pci_dev) } } +static void set_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, + uint64_t len) +{ + int i; + CXLDCD_Region *region = NULL; + + if (dpa < ct3d->dc.regions[0].base + || dpa >= ct3d->dc.regions[0].base + ct3d->dc.total_dynamic_capicity) + return; + + /* + * spec 3.0 9.13.3: Regions are used in increasing-DPA order, with + * Region 0 being used for the lowest DPA of Dynamic Capacity and + * Region 7 for the highest DPA. + * So we check from the last region to find where the dpa belongs. + * access across multiple regions is not allowed. + **/ + for (i = ct3d->dc.num_regions-1; i >= 0; i--) { + region = &ct3d->dc.regions[i]; + if (dpa >= region->base) + break; + } + + bitmap_set(region->blk_bitmap, (dpa-region->base)/region->block_size, + len/region->block_size); +} + +static bool test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, + uint64_t len) +{ + int i; + CXLDCD_Region *region = NULL; + uint64_t nbits; + long nr; + + if (dpa < ct3d->dc.regions[0].base + || dpa >= ct3d->dc.regions[0].base + ct3d->dc.total_dynamic_capicity) + return false; + + /* + * spec 3.0 9.13.3: Regions are used in increasing-DPA order, with + * Region 0 being used for the lowest DPA of Dynamic Capacity and + * Region 7 for the highest DPA. + * So we check from the last region to find where the dpa belongs. + * access across multiple regions is not allowed. + **/ + for (i = ct3d->dc.num_regions-1; i >= 0; i--) { + region = &ct3d->dc.regions[i]; + if (dpa >= region->base) + break; + } + + nr = (dpa-region->base)/region->block_size; + nbits = (len + region->block_size-1)/region->block_size; + if (find_next_zero_bit(region->blk_bitmap, nr+nbits, nr) + >= nr+nbits) + return true; + + return false; +} + +static void clear_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, + uint64_t len) +{ + int i; + CXLDCD_Region *region = NULL; + uint64_t nbits; + long nr; + + if (dpa < ct3d->dc.regions[0].base + || dpa >= ct3d->dc.regions[0].base + ct3d->dc.total_dynamic_capicity) + return; + + /* + * spec 3.0 9.13.3: Regions are used in increasing-DPA order, with + * Region 0 being used for the lowest DPA of Dynamic Capacity and + * Region 7 for the highest DPA. + * So we check from the last region to find where the dpa belongs. + * access across multiple regions is not allowed. + **/ + for (i = ct3d->dc.num_regions-1; i >= 0; i--) { + region = &ct3d->dc.regions[i]; + if (dpa >= region->base) + break; + } + + nr = (dpa-region->base) / region->block_size; + nbits = (len + region->block_size-1) / region->block_size; + for (i = 0; i < nbits; i++) { + clear_bit(nr, region->blk_bitmap); + nr++; + } +} + static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *dpa) { uint32_t *cache_mem = ct3d->cxl_cstate.crb.cache_mem_registers; @@ -973,16 +1164,24 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, AddressSpace **as, uint64_t *dpa_offset) { - MemoryRegion *vmr = NULL, *pmr = NULL; + MemoryRegion *vmr = NULL, *pmr = NULL, *dc_mr = NULL; + uint64_t vmr_size = 0, pmr_size = 0, dc_size = 0; if (ct3d->hostvmem) { vmr = host_memory_backend_get_memory(ct3d->hostvmem); + vmr_size = int128_get64(vmr->size); } if (ct3d->hostpmem) { pmr = host_memory_backend_get_memory(ct3d->hostpmem); + pmr_size = int128_get64(pmr->size); } + if (ct3d->dc.host_dc) { + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc); + /* Do we want dc_size to be dc_mr->size or not?? */ + dc_size = ct3d->dc.total_dynamic_capicity; + } - if (!vmr && !pmr) { + if (!vmr && !pmr && !dc_mr) { return -ENODEV; } @@ -990,20 +1189,22 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, return -EINVAL; } - if (*dpa_offset > int128_get64(ct3d->cxl_dstate.mem_size)) { + if (*dpa_offset >= vmr_size + pmr_size + dc_size || + (*dpa_offset >= vmr_size + pmr_size && ct3d->dc.num_regions == 0)) { return -EINVAL; } - if (vmr) { - if (*dpa_offset < int128_get64(vmr->size)) { - *as = &ct3d->hostvmem_as; - } else { - *as = &ct3d->hostpmem_as; - *dpa_offset -= vmr->size; - } - } else { - *as = &ct3d->hostpmem_as; - } + if (*dpa_offset < vmr_size) + *as = &ct3d->hostvmem_as; + else if (*dpa_offset < vmr_size + pmr_size) { + *as = &ct3d->hostpmem_as; + *dpa_offset -= vmr_size; + } else { + if (!test_region_block_backed(ct3d, *dpa_offset, size)) + return -ENODEV; + *as = &ct3d->dc.host_dc_as; + *dpa_offset -= (vmr_size + pmr_size); + } return 0; } @@ -1069,6 +1270,8 @@ static Property ct3_props[] = { DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), DEFINE_PROP_UINT16("spdm", CXLType3Dev, spdm_port, 0), DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0), + DEFINE_PROP_LINK("dc-memdev", CXLType3Dev, dc.host_dc, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_END_OF_LIST(), }; @@ -1135,34 +1338,41 @@ static void set_lsa(CXLType3Dev *ct3d, const void *buf, uint64_t size, static bool set_cacheline(CXLType3Dev *ct3d, uint64_t dpa_offset, uint8_t *data) { - MemoryRegion *vmr = NULL, *pmr = NULL; + MemoryRegion *vmr = NULL, *pmr = NULL, *dc_mr = NULL; AddressSpace *as; + uint64_t vmr_size = 0, pmr_size = 0, dc_size = 0; if (ct3d->hostvmem) { vmr = host_memory_backend_get_memory(ct3d->hostvmem); + vmr_size = int128_get64(vmr->size); } if (ct3d->hostpmem) { pmr = host_memory_backend_get_memory(ct3d->hostpmem); + pmr_size = int128_get64(pmr->size); } + if (ct3d->dc.host_dc) { + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc); + dc_size = ct3d->dc.total_dynamic_capicity; + } - if (!vmr && !pmr) { + if (!vmr && !pmr && !dc_mr) { return false; } - if (dpa_offset + 64 > int128_get64(ct3d->cxl_dstate.mem_size)) { - return false; - } + if (dpa_offset >= vmr_size + pmr_size + dc_size) + return false; + if (dpa_offset + 64 >= vmr_size + pmr_size && ct3d->dc.num_regions == 0) + return false; - if (vmr) { - if (dpa_offset <= int128_get64(vmr->size)) { - as = &ct3d->hostvmem_as; - } else { - as = &ct3d->hostpmem_as; - dpa_offset -= vmr->size; - } - } else { - as = &ct3d->hostpmem_as; - } + if (dpa_offset < vmr_size) { + as = &ct3d->hostvmem_as; + } else if (dpa_offset < vmr_size + pmr_size) { + as = &ct3d->hostpmem_as; + dpa_offset -= vmr->size; + } else { + as = &ct3d->dc.host_dc_as; + dpa_offset -= (vmr_size + pmr_size); + } address_space_write(as, dpa_offset, MEMTXATTRS_UNSPECIFIED, &data, 64); return true; @@ -1711,6 +1921,14 @@ static void qmp_cxl_process_dynamic_capacity_event(const char *path, CxlEventLog memcpy(&dCap.dynamic_capacity_extent, &extents[i] , sizeof(CXLDCExtent_raw)); + if (dCap.type == 0x0) + set_region_block_backed(dcd, extents[i].start_dpa, extents[i].len); + else if (dCap.type == 0x1) + clear_region_block_backed(dcd, extents[i].start_dpa, + extents[i].len); + else + error_setg(errp, "DC event not support yet, no bitmap op"); + if (cxl_event_insert(cxlds, CXL_EVENT_TYPE_DYNAMIC_CAP, (CXLEventRecordRaw *)&dCap)) { ; diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index c0c8fcc24b..d9b6776e2c 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -211,7 +211,7 @@ typedef struct cxl_device_state { } timestamp; /* memory region size, HDM */ - uint64_t mem_size; + uint64_t static_mem_size; uint64_t pmem_size; uint64_t vmem_size; @@ -412,6 +412,7 @@ typedef struct CXLDCD_Region { uint64_t block_size; uint32_t dsmadhandle; uint8_t flags; + unsigned long *blk_bitmap; } CXLDCD_Region; struct CXLType3Dev { @@ -447,12 +448,17 @@ struct CXLType3Dev { uint64_t poison_list_overflow_ts; struct dynamic_capacity { + HostMemoryBackend *host_dc; + AddressSpace host_dc_as; + + uint8_t num_hosts; //Table 7-55 uint8_t num_regions; // 1-8 struct CXLDCD_Region regions[DCD_MAX_REGION_NUM]; CXLDCDExtentList extents; uint32_t total_extent_count; uint32_t ext_list_gen_seq; + uint64_t total_dynamic_capicity; // 256M aligned } dc; };