From patchwork Thu May 11 17:58:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13238300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F543C77B7F for ; Thu, 11 May 2023 17:59:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238051AbjEKR7m (ORCPT ); Thu, 11 May 2023 13:59:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239131AbjEKR70 (ORCPT ); Thu, 11 May 2023 13:59:26 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45C016195 for ; Thu, 11 May 2023 10:58:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683827939; x=1715363939; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zmtKCxzEB2eCaiYSIvfweDYzrtmXFJA4u3jy5WAlwrg=; b=N80Ew5PLASsoq4Lnl77c6/GaWxsJK6UsblEABqccEXk9ErrxiFpKJU8A GuqU5e1MApJ0PnNaYsblKsNxJiucv9uHnIx71BbUeQZbc1LiWFMKEUi1I jGLo9ONVQv999mnwEdblt+6cHAiyuo82wVpVtgP9ZJCXC03hy2Ya1RZQM rITptRyu0DTVvk8QKE4MEQJCbQK2g9IThkhMT9gbHs5+/W6DSKIvNr++B BhX1SqOMhPInMCHYCK6rQf2xKLeL+jDbLDG+9MseTSgHCLN6vmN8vxisw RFkb2/Ro/d53aKOLCc5odxKYhRk8eeq98qfy3adRFAF4du2A2sRumTaps w==; X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="349422772" X-IronPort-AV: E=Sophos;i="5.99,268,1677571200"; d="scan'208";a="349422772" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 10:58:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730470597" X-IronPort-AV: E=Sophos;i="5.99,268,1677571200"; d="scan'208";a="730470597" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.95.11]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 10:58:49 -0700 Subject: [PATCH v2 1/4] cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Ira Weiny , Jonathan Cameron , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Thu, 11 May 2023 10:58:48 -0700 Message-ID: <168382792890.3510737.9466824452406784924.stgit@djiang5-mobl3> In-Reply-To: <168382784460.3510737.9571643715488757272.stgit@djiang5-mobl3> References: <168382784460.3510737.9571643715488757272.stgit@djiang5-mobl3> User-Agent: StGit/1.5 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Export the QoS Throttling Group ID from the CXL Fixed Memory Window Structure (CFMWS) under the root decoder sysfs attributes as qos_class. CXL rev3.0 9.17.1.3 CXL Fixed Memory Window Structure (CFMWS) cxl cli will use this id to match with the _DSM retrieved id for a hot-plugged CXL memory device DPA memory range to make sure that the DPA range is under the right CFMWS window. Reviewed-by: Davidlohr Bueso Reviewed-by: Ira Weiny Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- v5: - Documentation rewrite. (Dan) - Rename attrib to qos_class - Move qtg_id to root decoder v4: - Change kernel version for documentation to v6.5 v2: - Add explanation commit header (Jonathan) --- Documentation/ABI/testing/sysfs-bus-cxl | 15 +++++++++++++++ drivers/cxl/acpi.c | 3 +++ drivers/cxl/core/port.c | 11 +++++++++++ drivers/cxl/cxl.h | 3 +++ 4 files changed, 32 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 3acf2f17a73f..2f24e42ef36d 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -310,6 +310,21 @@ Description: provided it is currently idle / not bound to a driver. +What: /sys/bus/cxl/devices/decoderX.Y/qos_class +Date: May, 2023 +KernelVersion: v6.5 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) For CXL host platforms that support "QoS Telemmetry" this + root-decoder-only attribute conveys a platform specific cookie + that identifies a QoS performance class for the CXL Window. + This class-id can be compared against a similar "qos_class" + published for each memory-type that an endpoint supports. While + it is not required that endpoints map their local memory-class + to a matching platform class, mismatches are not recommended and + there are platform specific side-effects that may result. + + What: /sys/bus/cxl/devices/regionZ/uuid Date: May, 2022 KernelVersion: v6.0 diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 7e1765b09e04..e063df2bf876 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -289,6 +289,9 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg, } } } + + cxlrd->qos_class = cfmws->qtg_id; + rc = cxl_decoder_add(cxld, target_map); err_xormap: if (rc) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 4d1f9c5b5029..a0130aeb8d42 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -276,6 +276,15 @@ static ssize_t interleave_ways_show(struct device *dev, static DEVICE_ATTR_RO(interleave_ways); +static ssize_t qos_class_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev); + + return sysfs_emit(buf, "%d\n", cxlrd->qos_class); +} +static DEVICE_ATTR_RO(qos_class); + static struct attribute *cxl_decoder_base_attrs[] = { &dev_attr_start.attr, &dev_attr_size.attr, @@ -295,6 +304,7 @@ static struct attribute *cxl_decoder_root_attrs[] = { &dev_attr_cap_type2.attr, &dev_attr_cap_type3.attr, &dev_attr_target_list.attr, + &dev_attr_qos_class.attr, SET_CXL_REGION_ATTR(create_pmem_region) SET_CXL_REGION_ATTR(create_ram_region) SET_CXL_REGION_ATTR(delete_region) @@ -1625,6 +1635,7 @@ struct cxl_root_decoder *cxl_root_decoder_alloc(struct cxl_port *port, } atomic_set(&cxlrd->region_id, rc); + cxlrd->qos_class = CXL_QOS_CLASS_INVALID; return cxlrd; } EXPORT_SYMBOL_NS_GPL(cxl_root_decoder_alloc, CXL); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 044a92d9813e..4577d808ac6d 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -300,6 +300,7 @@ enum cxl_decoder_type { */ #define CXL_DECODER_MAX_INTERLEAVE 16 +#define CXL_QOS_CLASS_INVALID -1 /** * struct cxl_decoder - Common CXL HDM Decoder Attributes @@ -411,6 +412,7 @@ typedef struct cxl_dport *(*cxl_calc_hb_fn)(struct cxl_root_decoder *cxlrd, * @calc_hb: which host bridge covers the n'th position by granularity * @platform_data: platform specific configuration data * @range_lock: sync region autodiscovery by address range + * @qos_class: QoS performance class cookie * @cxlsd: base cxl switch decoder */ struct cxl_root_decoder { @@ -419,6 +421,7 @@ struct cxl_root_decoder { cxl_calc_hb_fn calc_hb; void *platform_data; struct mutex range_lock; + int qos_class; struct cxl_switch_decoder cxlsd; }; From patchwork Thu May 11 17:58:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13238307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2B08C7EE24 for ; Thu, 11 May 2023 18:00:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238840AbjEKSAE (ORCPT ); Thu, 11 May 2023 14:00:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239162AbjEKR7x (ORCPT ); Thu, 11 May 2023 13:59:53 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BC15A5EF for ; Thu, 11 May 2023 10:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683827973; x=1715363973; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CzsWt8T9nmEYJ5DD59h6yT2X4Rmm2yYVBltFO1nWdW4=; b=dGdGglLA6Z9yHB/y2Er8QzzdFGlvpzoh8buNMphnX41CUAcGhXhdNh5d RNEfTB86P0fQCt6UIR+/ONi1vxLvYMZbHJkvTgTZ4gOqNMYs/rgOdNPIp 3/097K7raBFN21y1XwrVRtHxDrWaxZxJ7UMs4ipjurMJalSWk8EPNMQOi F5QVVlz0dkPTZbLqtt7KrSvad9Ci+NzrBz78JeeHMDlLhXQaKiCeIwSrw hFje45qAEx1Ahhe35ji/732R+8KdavBvaS92UJMSFc8rH197OMkVUMo3I Hyr0UdORZm45nbdtj3TLackSOczaESOiEkL54d5FDhaQqhShIxrPb9B1C A==; X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="335091958" X-IronPort-AV: E=Sophos;i="5.99,268,1677571200"; d="scan'208";a="335091958" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 10:58:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="693904303" X-IronPort-AV: E=Sophos;i="5.99,268,1677571200"; d="scan'208";a="693904303" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.95.11]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 10:58:55 -0700 Subject: [PATCH v2 2/4] cxl: add missing return to cdat read error path From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Thu, 11 May 2023 10:58:55 -0700 Message-ID: <168382793506.3510737.4792518576623749076.stgit@djiang5-mobl3> In-Reply-To: <168382784460.3510737.9571643715488757272.stgit@djiang5-mobl3> References: <168382784460.3510737.9571643715488757272.stgit@djiang5-mobl3> User-Agent: StGit/1.5 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add a return to the error path when cxl_cdat_read_table() fails. Current code continues with the table pointer points to freed memory. Fixes: 4f8a8f10c2f5 ("cxl/pci: Simplify CDAT retrieval error path") Signed-off-by: Dave Jiang Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index bdbd907884ce..f332fe7af92b 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -571,6 +571,7 @@ void read_cdat_data(struct cxl_port *port) /* Don't leave table data allocated on error */ devm_kfree(dev, cdat_table); dev_err(dev, "CDAT data read error\n"); + return; } port->cdat.table = cdat_table + sizeof(__le32); From patchwork Thu May 11 17:59:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13238308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9457EC7EE25 for ; Thu, 11 May 2023 18:00:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238932AbjEKSAG (ORCPT ); Thu, 11 May 2023 14:00:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239183AbjEKR74 (ORCPT ); Thu, 11 May 2023 13:59:56 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 806E6A5EA for ; Thu, 11 May 2023 10:59:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683827975; x=1715363975; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NAX+K0/JcSAtlxkbvAEWD+I2/IMBx2Y0Ktj63jlEBrg=; b=FRASFHwNpkR0tuWnPffogD90MMQGC2sQXyRkX3zFTyoC7tU820YaZ/g3 5TkPWTHFlPvmUSvUiSJOhGh9psWHdpADCDAxxmWdd3n047Inmc52giDft ezaoPSDmK76jWXhGcCo8DOwrvwJ90KyBzGWaTOWOVxuaQCSIFLC6hVfc6 Rgau0uxeHB7UgBBAsEhuiYwyMxIFeoXqB3incA9tJl8sD/hMmQ+dHNtxr oERKpCclGQtS3zWZ7Mmq7Ydg5DQSLhFDaaBUdg0OtChpHVMkGcfrdCmY8 wcFrxCDdNr7jE7xyY/CBXGPjWk9fziPptGa8+x5Hj5zbgO0G7pQvWS0Vq Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="335092006" X-IronPort-AV: E=Sophos;i="5.99,268,1677571200"; d="scan'208";a="335092006" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 10:59:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="693904335" X-IronPort-AV: E=Sophos;i="5.99,268,1677571200"; d="scan'208";a="693904335" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.95.11]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 10:59:01 -0700 Subject: [PATCH v2 3/4] cxl: Add checksum verification to CDAT from CXL From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Ira Weiny , Jonathan Cameron , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Thu, 11 May 2023 10:59:01 -0700 Message-ID: <168382794106.3510737.6205740820012769763.stgit@djiang5-mobl3> In-Reply-To: <168382784460.3510737.9571643715488757272.stgit@djiang5-mobl3> References: <168382784460.3510737.9571643715488757272.stgit@djiang5-mobl3> User-Agent: StGit/1.5 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org A CDAT table is available from a CXL device. The table is read by the driver and cached in software. With the CXL subsystem needing to parse the CDAT table, the checksum should be verified. Add checksum verification after the CDAT table is read from device. Reviewed-by: Ira Weiny Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- Post patch series split: v2: - Split out fix for cdat_read() error path return. (Davidlohr) - Make port->cdat consistent. (Davidlohr) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index f332fe7af92b..64ae45ae7ad6 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -528,6 +528,16 @@ static int cxl_cdat_read_table(struct device *dev, return 0; } +static unsigned char cdat_checksum(void *buf, size_t size) +{ + unsigned char sum, *data = buf; + size_t i; + + for (sum = 0, i = 0; i < size; i++) + sum += data[i]; + return sum; +} + /** * read_cdat_data - Read the CDAT data on this port * @port: Port to read data from @@ -574,7 +584,15 @@ void read_cdat_data(struct cxl_port *port) return; } - port->cdat.table = cdat_table + sizeof(__le32); + cdat_table = cdat_table + sizeof(__le32); + if (cdat_checksum(cdat_table, cdat_length)) { + /* Don't leave table data allocated on error */ + devm_kfree(dev, cdat_table); + dev_err(dev, "CDAT data checksum error\n"); + return; + } + + port->cdat.table = cdat_table; port->cdat.length = cdat_length; } EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); From patchwork Thu May 11 17:59:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13238309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DCE5C77B7F for ; Thu, 11 May 2023 18:00:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238516AbjEKSAN (ORCPT ); Thu, 11 May 2023 14:00:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238643AbjEKSAI (ORCPT ); Thu, 11 May 2023 14:00:08 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AE579039 for ; Thu, 11 May 2023 10:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683827980; x=1715363980; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j5x6f3r1ok48eBoxa/HxDk1jjDqrLmKG+KkhKxfWp7Y=; b=W2Ncw5ruYp9u81AxSSvjTTTt18SndyzCmVABdPwOHhYfhjzYg7NMzdFF FPK+1TfsF6b6Oo27xvshzbnTdekMFjp8vBKnNCHg1ksO3VAyhZRPVly9K dz7qabUFW2vUaSajFgYRwMzK0c3uJU/nVzjfSVgak4lkd8zj5GYsDK3gn 4B0s55rPT5CBzK3vhXug9sT7DfjSbCKtKIFF9PHH1kK5adli93eWSI+hF m0o+aKK6MXwMclw7xG1UElvId2nRrtschxH910fVTi19zHssoM9kvBDu7 +FLQ1TSevuYOj71MH/a1x3tdO6tfMJk8lfxUJGV24HXgdtqFjnPD8EG4I g==; X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="335092065" X-IronPort-AV: E=Sophos;i="5.99,268,1677571200"; d="scan'208";a="335092065" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 10:59:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="693904350" X-IronPort-AV: E=Sophos;i="5.99,268,1677571200"; d="scan'208";a="693904350" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.212.95.11]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 10:59:07 -0700 Subject: [PATCH v2 4/4] cxl: Add support for reading CXL switch CDAT table From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Davidlohr Bueso , Ira Weiny , Jonathan Cameron , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com Date: Thu, 11 May 2023 10:59:07 -0700 Message-ID: <168382794705.3510737.14861252708548327842.stgit@djiang5-mobl3> In-Reply-To: <168382784460.3510737.9571643715488757272.stgit@djiang5-mobl3> References: <168382784460.3510737.9571643715488757272.stgit@djiang5-mobl3> User-Agent: StGit/1.5 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add read_cdat_data() call in cxl_switch_port_probe() to allow reading of CDAT data for CXL switches. read_cdat_data() needs to be adjusted for the retrieving of the PCIe device depending on if the passed in port is endpoint or switch. Reviewed-by: Davidlohr Bueso Reviewed-by: Ira Weiny Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang --- v2: - Set pdev to NULL first (Davidlohr) Before split: v5: - Rebase after fix [1]. (Dan) [1]: http://lore.kernel.org/r/168213190748.708404.16215095414060364800.stgit@dwillia2-xfh.jf.intel.com v4: - Remove cxl_test wrapper. (Ira) --- drivers/cxl/core/pci.c | 22 +++++++++++++++++----- drivers/cxl/port.c | 3 +++ 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 64ae45ae7ad6..58051154ab1a 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -546,18 +546,30 @@ static unsigned char cdat_checksum(void *buf, size_t size) */ void read_cdat_data(struct cxl_port *port) { - struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport); - struct device *host = cxlmd->dev.parent; + struct device *uport = port->uport; struct device *dev = &port->dev; struct pci_doe_mb *cdat_doe; + struct pci_dev *pdev = NULL; + struct cxl_memdev *cxlmd; size_t cdat_length; void *cdat_table; int rc; - if (!dev_is_pci(host)) + if (is_cxl_memdev(uport)) { + struct device *host; + + cxlmd = to_cxl_memdev(uport); + host = cxlmd->dev.parent; + if (dev_is_pci(host)) + pdev = to_pci_dev(host); + } else if (dev_is_pci(uport)) { + pdev = to_pci_dev(uport); + } + + if (!pdev) return; - cdat_doe = pci_find_doe_mailbox(to_pci_dev(host), - PCI_DVSEC_VENDOR_ID_CXL, + + cdat_doe = pci_find_doe_mailbox(pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DOE_PROTOCOL_TABLE_ACCESS); if (!cdat_doe) { dev_dbg(dev, "No CDAT mailbox\n"); diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 22a7ab2bae7c..a49f5eb149f1 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -62,6 +62,9 @@ static int cxl_switch_port_probe(struct cxl_port *port) struct cxl_hdm *cxlhdm; int rc; + /* Cache the data early to ensure is_visible() works */ + read_cdat_data(port); + rc = devm_cxl_port_enumerate_dports(port); if (rc < 0) return rc;