From patchwork Fri May 12 21:17:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13239834 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C94DC7EE25 for ; Fri, 12 May 2023 21:18:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240350AbjELVSE (ORCPT ); Fri, 12 May 2023 17:18:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240263AbjELVSD (ORCPT ); Fri, 12 May 2023 17:18:03 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FB0361B5 for ; Fri, 12 May 2023 14:17:32 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4f24cfb8539so8228255e87.3 for ; Fri, 12 May 2023 14:17:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683926250; x=1686518250; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RzC/S26FfX2KBobwpdwOfCvN/amobbf96cFrDJ/wC6A=; b=Nso9rJDJ6ec93LDQc07gjyLuWRCgV+NYsjBRmmozpwS5/Uwa4bPRu/NUffOUcOWM1E lggONYhXu1HbznRV4FZeh6UtFuZ/i/z+YNfFbURG332QQ9dLr/f/jH7Ya/OOvZsTjvJR 5xduyE1vRkKQUXfnyjjnu3IVLOmPJHKly/6ip6z01OdSs6P0SCid4/gFX1ZwHgM84/jx iP3TRYSiU3jm+7Za3gWponlvjqal3U957jANf6Ld73JHKXWpxaNHYhmlLUN8P4k/D3Mr NFCe+jj8q/T0amV4xp8kerOU6WwgCgXSoMQvu/r4DuJ7bFJNoFCkos6wYHM+MOFiX0wc r8QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683926250; x=1686518250; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RzC/S26FfX2KBobwpdwOfCvN/amobbf96cFrDJ/wC6A=; b=K7k6VlnlrLoY+RPPRBwJioqdZndspDuWx1noqmcbyRplia2Unem/V2ejtDQYh06BaS Cg7qUkW+216OEoHKI6uoJx1XyFORjiRcusrMWDtWEwp6Dcnzx9AoyeaClE1cRh3Lrpxl o9cvM/dtL6dpnipAu6qOdaPshtV1xGZAGHf9mHLcm3oMF3iwQKZnMgWuMUq9g7kE7T5g Ix20Al7zmFGhBc+IdpyHCxbNYolGOXqrchUKIkEn2RdS6iaUwvhUmA9iohyWLvRU43hh iCDjKwZb/6qP0DkYs29ADQNc0PI9EShLmKDZT4bdOk30V9mvkizyEsxoSM8cDFrJWN62 1a6A== X-Gm-Message-State: AC+VfDywkHJnnESykDiSsQib3/8ilir4Gin3q/2TDIlYBQ6prSdNdNJy UJEw4ELlFewESEcKdKZZJimJIg== X-Google-Smtp-Source: ACHHUZ4N9TANITxQE6BSQ6d1lPsMv+zeDT9j59wfWA2uFPb0lLHvTdh5DmhMxDQAoNiPrY7RwVdHgA== X-Received: by 2002:ac2:488c:0:b0:4f0:2ce:34ea with SMTP id x12-20020ac2488c000000b004f002ce34eamr3938380lfc.44.1683926249684; Fri, 12 May 2023 14:17:29 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id w4-20020ac254a4000000b004edafe3f8dbsm1590363lfk.11.2023.05.12.14.17.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 14:17:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 Date: Sat, 13 May 2023 00:17:18 +0300 Message-Id: <20230512211727.3445575-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> References: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Describe parent clocks used by the LCC on the MDM9615 platform. It is the list as the one for msm8960/apq8064, with only difference being pxo/cxo replacement. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,lcc.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.yaml b/Documentation/devicetree/bindings/clock/qcom,lcc.yaml index 8c783823e93c..55985e562a34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,lcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,lcc.yaml @@ -76,6 +76,40 @@ allOf: - clocks - clock-names + - if: + properties: + compatible: + contains: + enum: + - qcom,lcc-mdm9615 + then: + properties: + clocks: + items: + - description: Board CXO source + - description: PLL 4 Vote clock + - description: MI2S codec clock + - description: Mic I2S codec clock + - description: Mic I2S spare clock + - description: Speaker I2S codec clock + - description: Speaker I2S spare clock + - description: PCM codec clock + + clock-names: + items: + - const: cxo + - const: pll4_vote + - const: mi2s_codec_clk + - const: codec_i2s_mic_codec_clk + - const: spare_i2s_mic_codec_clk + - const: codec_i2s_spkr_codec_clk + - const: spare_i2s_spkr_codec_clk + - const: pcm_codec_clk + + required: + - clocks + - clock-names + examples: - | clock-controller@28000000 { From patchwork Fri May 12 21:17:19 2023 Content-Type: text/plain; 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Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/lcc-mdm9615.c | 2 +- include/dt-bindings/clock/qcom,lcc-mdm9615.h | 44 -------------------- 2 files changed, 1 insertion(+), 45 deletions(-) delete mode 100644 include/dt-bindings/clock/qcom,lcc-mdm9615.h diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c index 8d243e880d95..c17caffdc349 100644 --- a/drivers/clk/qcom/lcc-mdm9615.c +++ b/drivers/clk/qcom/lcc-mdm9615.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include "common.h" #include "clk-regmap.h" diff --git a/include/dt-bindings/clock/qcom,lcc-mdm9615.h b/include/dt-bindings/clock/qcom,lcc-mdm9615.h deleted file mode 100644 index 299338ee1d88..000000000000 --- a/include/dt-bindings/clock/qcom,lcc-mdm9615.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong - */ - -#ifndef _DT_BINDINGS_CLK_LCC_MDM9615_H -#define _DT_BINDINGS_CLK_LCC_MDM9615_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SLIMBUS_SRC 9 -#define AUDIO_SLIMBUS_CLK 10 -#define SPS_SLIMBUS_CLK 11 -#define CODEC_I2S_MIC_OSR_SRC 12 -#define CODEC_I2S_MIC_OSR_CLK 13 -#define CODEC_I2S_MIC_DIV_CLK 14 -#define CODEC_I2S_MIC_BIT_DIV_CLK 15 -#define CODEC_I2S_MIC_BIT_CLK 16 -#define SPARE_I2S_MIC_OSR_SRC 17 -#define SPARE_I2S_MIC_OSR_CLK 18 -#define SPARE_I2S_MIC_DIV_CLK 19 -#define SPARE_I2S_MIC_BIT_DIV_CLK 20 -#define SPARE_I2S_MIC_BIT_CLK 21 -#define CODEC_I2S_SPKR_OSR_SRC 22 -#define CODEC_I2S_SPKR_OSR_CLK 23 -#define CODEC_I2S_SPKR_DIV_CLK 24 -#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 -#define CODEC_I2S_SPKR_BIT_CLK 26 -#define SPARE_I2S_SPKR_OSR_SRC 27 -#define SPARE_I2S_SPKR_OSR_CLK 28 -#define SPARE_I2S_SPKR_DIV_CLK 29 -#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 -#define SPARE_I2S_SPKR_BIT_CLK 31 - -#endif From patchwork Fri May 12 21:17:20 2023 Content-Type: text/plain; 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Split the qcom,gcc-mdm9615 to the separate schema file. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,gcc-mdm9615.yaml | 47 +++++++++++++++++++ .../bindings/clock/qcom,gcc-other.yaml | 3 -- 2 files changed, 47 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml new file mode 100644 index 000000000000..69162ac4a0da --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MDM9615 + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MDM9615. + + See also:: + include/dt-bindings/clock/qcom,gcc-mdm9615.h + include/dt-bindings/reset/qcom,gcc-mdm9615.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,gcc-mdm9615 + + clocks: + maxItems: 2 + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + reg = <0x00900000 0x4000>; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&cxo_board>, <&lcc PLL4>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml index ae01e7749534..b6e260755a21 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml @@ -19,8 +19,6 @@ description: | include/dt-bindings/reset/qcom,gcc-ipq6018.h include/dt-bindings/clock/qcom,gcc-msm8953.h include/dt-bindings/clock/qcom,gcc-mdm9607.h - include/dt-bindings/clock/qcom,gcc-mdm9615.h - include/dt-bindings/reset/qcom,gcc-mdm9615.h allOf: - $ref: qcom,gcc.yaml# @@ -31,7 +29,6 @@ properties: - qcom,gcc-ipq6018 - qcom,gcc-mdm9607 - qcom,gcc-msm8953 - - qcom,gcc-mdm9615 required: - compatible From patchwork Fri May 12 21:17:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13239839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68789C7EE45 for ; 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Fri, 12 May 2023 14:17:32 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id w4-20020ac254a4000000b004edafe3f8dbsm1590363lfk.11.2023.05.12.14.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 14:17:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 04/10] clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents Date: Sat, 13 May 2023 00:17:21 +0300 Message-Id: <20230512211727.3445575-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> References: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-mdm9615.c | 42 +++++++++++++++++----------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 8bed02a748ab..fb5c1244fb97 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -207,7 +207,7 @@ static struct clk_rcg gsbi1_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -258,7 +258,7 @@ static struct clk_rcg gsbi2_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -309,7 +309,7 @@ static struct clk_rcg gsbi3_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -360,7 +360,7 @@ static struct clk_rcg gsbi4_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -411,7 +411,7 @@ static struct clk_rcg gsbi5_uart_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -474,7 +474,7 @@ static struct clk_rcg gsbi1_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -523,7 +523,7 @@ static struct clk_rcg gsbi2_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -572,7 +572,7 @@ static struct clk_rcg gsbi3_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -621,7 +621,7 @@ static struct clk_rcg gsbi4_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -670,7 +670,7 @@ static struct clk_rcg gsbi5_qup_src = { .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -725,7 +725,7 @@ static struct clk_rcg gp0_src = { .hw.init = &(struct clk_init_data){ .name = "gp0_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, }, @@ -774,7 +774,7 @@ static struct clk_rcg gp1_src = { .hw.init = &(struct clk_init_data){ .name = "gp1_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -823,7 +823,7 @@ static struct clk_rcg gp2_src = { .hw.init = &(struct clk_init_data){ .name = "gp2_src", .parent_names = gcc_cxo, - .num_parents = 1, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -875,7 +875,7 @@ static struct clk_rcg prng_src = { .hw.init = &(struct clk_init_data){ .name = "prng_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, }, @@ -937,7 +937,7 @@ static struct clk_rcg sdc1_src = { .hw.init = &(struct clk_init_data){ .name = "sdc1_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, } @@ -985,7 +985,7 @@ static struct clk_rcg sdc2_src = { .hw.init = &(struct clk_init_data){ .name = "sdc2_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, } @@ -1038,7 +1038,7 @@ static struct clk_rcg usb_hs1_xcvr_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1087,7 +1087,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1142,7 +1142,7 @@ static struct clk_rcg usb_hs1_system_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hs1_system_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1197,7 +1197,7 @@ static struct clk_rcg usb_hsic_system_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_system_src", .parent_names = gcc_cxo_pll8, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, @@ -1252,7 +1252,7 @@ static struct clk_rcg usb_hsic_hsic_src = { .hw.init = &(struct clk_init_data){ .name = "usb_hsic_hsic_src", .parent_names = gcc_cxo_pll14, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_cxo_pll14), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, }, From patchwork Fri May 12 21:17:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13239841 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58B82C7EE2E for ; Fri, 12 May 2023 21:18:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240326AbjELVSK (ORCPT ); Fri, 12 May 2023 17:18:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240417AbjELVSI (ORCPT ); Fri, 12 May 2023 17:18:08 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1965B61B4 for ; Fri, 12 May 2023 14:17:40 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4f11d267d8bso11692313e87.2 for ; Fri, 12 May 2023 14:17:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683926253; x=1686518253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=syiDzOsg6XJ4uXn4QKeAjfrg2I2yS6EiIwWVe3QYC4w=; b=DfJ5S5ceTi7oPQlB7mZgaNUdPnoyHIQVNfkztLUDT+85YTmQDS9uv8Nw6OzftPw6ex axgGerrw1in3MFAIGDSSAf3bSFSvWG8Ljof1Gs6cLtEyr6LXXtyS5n/kzZnkjcOoNg18 CjAzrEo6SWcKbZO6Tp7mzTx2fcwiH5S6mno+dYvvUK0Fc/+NrMIdxGrF83qusJWULDWJ 0algqOXpebvxkt/pgTl93zEUD3VS+hjJnTNwdlQJqS1bQ9tvcvBVDOAYxok5FbVHK+PC 2n4UM+nPEax0BM8j7u60si2fz4IV5ZXWjQ5HkGBF3F1qITJmMxjhBrrqynWxnbKpwTYm 7/8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683926253; x=1686518253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=syiDzOsg6XJ4uXn4QKeAjfrg2I2yS6EiIwWVe3QYC4w=; b=B1SC4RPx9/qekj9CcgPzgoapGoNnUUDfXWbdfK7SIr9okHkjETZRTpnuwI7cH98LSp fcZd3ZSRdiHC5khkxryicaZCsGypcADOb1rNKQNiI4xsuQZe1vr37PXhN+9cyAaGmxSx znNqk+ZSr5T8Rq7sA/oJ6V51yQV0reKcUWWE0qWl9uOHlb/In1J9nnOI1PTLybsbLfwa TxEZXpgIr+F+3eJfeuvTs/N02sslxi/SRRxEPtoIy05QCUFL0SU0j4nsBW66UE+sPw5t /vGnVXrLFq0xdNGW0MKV7ckb5phKnToPQckYqJ09BLf3wwL++SwAI0HyBMMU2ZpnrL8N i2kw== X-Gm-Message-State: AC+VfDyRdVHvtkLRlAJ7VUgk1I8up/8pAJsOOjt/zX4Dmg9ksvbcl2+m 8Itvoi3Zd7wZA0vtBs1ZDkZ7gQ== X-Google-Smtp-Source: ACHHUZ5+twwR+D+moPybDSGPRlR068A+WUkERVv/70oJILlrizt0o+StmA4U5UyFeyzoywzXYdRvQg== X-Received: by 2002:ac2:4255:0:b0:4f1:2ebf:5370 with SMTP id m21-20020ac24255000000b004f12ebf5370mr3806218lfl.23.1683926253000; Fri, 12 May 2023 14:17:33 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id w4-20020ac254a4000000b004edafe3f8dbsm1590363lfk.11.2023.05.12.14.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 14:17:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 05/10] clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 Date: Sat, 13 May 2023 00:17:22 +0300 Message-Id: <20230512211727.3445575-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> References: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The two LCC drivers, msm8960 and mdm9615 are almost the same. The only difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615 uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 14 +- drivers/clk/qcom/Makefile | 1 - drivers/clk/qcom/lcc-mdm9615.c | 572 --------------------------------- drivers/clk/qcom/lcc-msm8960.c | 19 +- 4 files changed, 18 insertions(+), 588 deletions(-) delete mode 100644 drivers/clk/qcom/lcc-mdm9615.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 12be3e2371b3..72ee4d46aa81 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -238,10 +238,10 @@ config MSM_GCC_8960 i2c, USB, SD/eMMC, SATA, PCIe, etc. config MSM_LCC_8960 - tristate "APQ8064/MSM8960 LPASS Clock Controller" - select MSM_GCC_8960 + tristate "APQ8064/MSM8960/MDM9650 LPASS Clock Controller" help - Support for the LPASS clock controller on apq8064/msm8960 devices. + Support for the LPASS clock controller on apq8064/msm8960/mdm9650 + devices. Say Y if you want to use audio devices such as i2s, pcm, SLIMBus, etc. @@ -259,14 +259,6 @@ config MDM_GCC_9615 Say Y if you want to use peripheral devices such as UART, SPI, i2c, USB, SD/eMMC, etc. -config MDM_LCC_9615 - tristate "MDM9615 LPASS Clock Controller" - select MDM_GCC_9615 - help - Support for the LPASS clock controller on mdm9615 devices. - Say Y if you want to use audio devices such as i2s, pcm, - SLIMBus, etc. - config MSM_MMCC_8960 tristate "MSM8960 Multimedia Clock Controller" select MSM_GCC_8960 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9ff4c373ad95..13bd35f17a61 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o -obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o diff --git a/drivers/clk/qcom/lcc-mdm9615.c b/drivers/clk/qcom/lcc-mdm9615.c deleted file mode 100644 index c17caffdc349..000000000000 --- a/drivers/clk/qcom/lcc-mdm9615.c +++ /dev/null @@ -1,572 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-regmap.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-branch.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" - -static struct clk_pll pll4 = { - .l_reg = 0x4, - .m_reg = 0x8, - .n_reg = 0xc, - .config_reg = 0x14, - .mode_reg = 0x0, - .status_reg = 0x18, - .status_bit = 16, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pll4", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -enum { - P_CXO, - P_PLL4, -}; - -static const struct parent_map lcc_cxo_pll4_map[] = { - { P_CXO, 0 }, - { P_PLL4, 2 } -}; - -static const char * const lcc_cxo_pll4[] = { - "cxo", - "pll4_vote", -}; - -static struct freq_tbl clk_tbl_aif_osr_492[] = { - { 512000, P_PLL4, 4, 1, 240 }, - { 768000, P_PLL4, 4, 1, 160 }, - { 1024000, P_PLL4, 4, 1, 120 }, - { 1536000, P_PLL4, 4, 1, 80 }, - { 2048000, P_PLL4, 4, 1, 60 }, - { 3072000, P_PLL4, 4, 1, 40 }, - { 4096000, P_PLL4, 4, 1, 30 }, - { 6144000, P_PLL4, 4, 1, 20 }, - { 8192000, P_PLL4, 4, 1, 15 }, - { 12288000, P_PLL4, 4, 1, 10 }, - { 24576000, P_PLL4, 4, 1, 5 }, - { 27000000, P_CXO, 1, 0, 0 }, - { } -}; - -static struct freq_tbl clk_tbl_aif_osr_393[] = { - { 512000, P_PLL4, 4, 1, 192 }, - { 768000, P_PLL4, 4, 1, 128 }, - { 1024000, P_PLL4, 4, 1, 96 }, - { 1536000, P_PLL4, 4, 1, 64 }, - { 2048000, P_PLL4, 4, 1, 48 }, - { 3072000, P_PLL4, 4, 1, 32 }, - { 4096000, P_PLL4, 4, 1, 24 }, - { 6144000, P_PLL4, 4, 1, 16 }, - { 8192000, P_PLL4, 4, 1, 12 }, - { 12288000, P_PLL4, 4, 1, 8 }, - { 24576000, P_PLL4, 4, 1, 4 }, - { 27000000, P_CXO, 1, 0, 0 }, - { } -}; - -static struct clk_rcg mi2s_osr_src = { - .ns_reg = 0x48, - .md_reg = 0x4c, - .mn = { - .mnctr_en_bit = 8, - .mnctr_reset_bit = 7, - .mnctr_mode_shift = 5, - .n_val_shift = 24, - .m_val_shift = 8, - .width = 8, - }, - .p = { - .pre_div_shift = 3, - .pre_div_width = 2, - }, - .s = { - .src_sel_shift = 0, - .parent_map = lcc_cxo_pll4_map, - }, - .freq_tbl = clk_tbl_aif_osr_393, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_src", - .parent_names = lcc_cxo_pll4, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, -}; - -static const char * const lcc_mi2s_parents[] = { - "mi2s_osr_src", -}; - -static struct clk_branch mi2s_osr_clk = { - .halt_reg = 0x50, - .halt_bit = 1, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_osr_clk", - .parent_names = lcc_mi2s_parents, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_regmap_div mi2s_div_clk = { - .reg = 0x48, - .shift = 10, - .width = 4, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_div_clk", - .parent_names = lcc_mi2s_parents, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - }, - }, -}; - -static struct clk_branch mi2s_bit_div_clk = { - .halt_reg = 0x50, - .halt_bit = 0, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0x48, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_div_clk", - .parent_names = (const char *[]){ "mi2s_div_clk" }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_regmap_mux mi2s_bit_clk = { - .reg = 0x48, - .shift = 14, - .width = 1, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mi2s_bit_clk", - .parent_names = (const char *[]){ - "mi2s_bit_div_clk", - "mi2s_codec_clk", - }, - .num_parents = 2, - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \ -static struct clk_rcg prefix##_osr_src = { \ - .ns_reg = _ns, \ - .md_reg = _md, \ - .mn = { \ - .mnctr_en_bit = 8, \ - .mnctr_reset_bit = 7, \ - .mnctr_mode_shift = 5, \ - .n_val_shift = 24, \ - .m_val_shift = 8, \ - .width = 8, \ - }, \ - .p = { \ - .pre_div_shift = 3, \ - .pre_div_width = 2, \ - }, \ - .s = { \ - .src_sel_shift = 0, \ - .parent_map = lcc_cxo_pll4_map, \ - }, \ - .freq_tbl = clk_tbl_aif_osr_393, \ - .clkr = { \ - .enable_reg = _ns, \ - .enable_mask = BIT(9), \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_osr_src", \ - .parent_names = lcc_cxo_pll4, \ - .num_parents = 2, \ - .ops = &clk_rcg_ops, \ - .flags = CLK_SET_RATE_GATE, \ - }, \ - }, \ -}; \ - \ -static const char * const lcc_##prefix##_parents[] = { \ - #prefix "_osr_src", \ -}; \ - \ -static struct clk_branch prefix##_osr_clk = { \ - .halt_reg = hr, \ - .halt_bit = 1, \ - .halt_check = BRANCH_HALT_ENABLE, \ - .clkr = { \ - .enable_reg = _ns, \ - .enable_mask = BIT(21), \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_osr_clk", \ - .parent_names = lcc_##prefix##_parents, \ - .num_parents = 1, \ - .ops = &clk_branch_ops, \ - .flags = CLK_SET_RATE_PARENT, \ - }, \ - }, \ -}; \ - \ -static struct clk_regmap_div prefix##_div_clk = { \ - .reg = _ns, \ - .shift = 10, \ - .width = 8, \ - .clkr = { \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_div_clk", \ - .parent_names = lcc_##prefix##_parents, \ - .num_parents = 1, \ - .ops = &clk_regmap_div_ops, \ - }, \ - }, \ -}; \ - \ -static struct clk_branch prefix##_bit_div_clk = { \ - .halt_reg = hr, \ - .halt_bit = 0, \ - .halt_check = BRANCH_HALT_ENABLE, \ - .clkr = { \ - .enable_reg = _ns, \ - .enable_mask = BIT(19), \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_bit_div_clk", \ - .parent_names = (const char *[]){ \ - #prefix "_div_clk" \ - }, \ - .num_parents = 1, \ - .ops = &clk_branch_ops, \ - .flags = CLK_SET_RATE_PARENT, \ - }, \ - }, \ -}; \ - \ -static struct clk_regmap_mux prefix##_bit_clk = { \ - .reg = _ns, \ - .shift = 18, \ - .width = 1, \ - .clkr = { \ - .hw.init = &(struct clk_init_data){ \ - .name = #prefix "_bit_clk", \ - .parent_names = (const char *[]){ \ - #prefix "_bit_div_clk", \ - #prefix "_codec_clk", \ - }, \ - .num_parents = 2, \ - .ops = &clk_regmap_mux_closest_ops, \ - .flags = CLK_SET_RATE_PARENT, \ - }, \ - }, \ -} - -CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68); -CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80); -CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74); -CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c); - -static struct freq_tbl clk_tbl_pcm_492[] = { - { 256000, P_PLL4, 4, 1, 480 }, - { 512000, P_PLL4, 4, 1, 240 }, - { 768000, P_PLL4, 4, 1, 160 }, - { 1024000, P_PLL4, 4, 1, 120 }, - { 1536000, P_PLL4, 4, 1, 80 }, - { 2048000, P_PLL4, 4, 1, 60 }, - { 3072000, P_PLL4, 4, 1, 40 }, - { 4096000, P_PLL4, 4, 1, 30 }, - { 6144000, P_PLL4, 4, 1, 20 }, - { 8192000, P_PLL4, 4, 1, 15 }, - { 12288000, P_PLL4, 4, 1, 10 }, - { 24576000, P_PLL4, 4, 1, 5 }, - { 27000000, P_CXO, 1, 0, 0 }, - { } -}; - -static struct freq_tbl clk_tbl_pcm_393[] = { - { 256000, P_PLL4, 4, 1, 384 }, - { 512000, P_PLL4, 4, 1, 192 }, - { 768000, P_PLL4, 4, 1, 128 }, - { 1024000, P_PLL4, 4, 1, 96 }, - { 1536000, P_PLL4, 4, 1, 64 }, - { 2048000, P_PLL4, 4, 1, 48 }, - { 3072000, P_PLL4, 4, 1, 32 }, - { 4096000, P_PLL4, 4, 1, 24 }, - { 6144000, P_PLL4, 4, 1, 16 }, - { 8192000, P_PLL4, 4, 1, 12 }, - { 12288000, P_PLL4, 4, 1, 8 }, - { 24576000, P_PLL4, 4, 1, 4 }, - { 27000000, P_CXO, 1, 0, 0 }, - { } -}; - -static struct clk_rcg pcm_src = { - .ns_reg = 0x54, - .md_reg = 0x58, - .mn = { - .mnctr_en_bit = 8, - .mnctr_reset_bit = 7, - .mnctr_mode_shift = 5, - .n_val_shift = 16, - .m_val_shift = 16, - .width = 16, - }, - .p = { - .pre_div_shift = 3, - .pre_div_width = 2, - }, - .s = { - .src_sel_shift = 0, - .parent_map = lcc_cxo_pll4_map, - }, - .freq_tbl = clk_tbl_pcm_393, - .clkr = { - .enable_reg = 0x54, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "pcm_src", - .parent_names = lcc_cxo_pll4, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, -}; - -static struct clk_branch pcm_clk_out = { - .halt_reg = 0x5c, - .halt_bit = 0, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0x54, - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk_out", - .parent_names = (const char *[]){ "pcm_src" }, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_regmap_mux pcm_clk = { - .reg = 0x54, - .shift = 10, - .width = 1, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "pcm_clk", - .parent_names = (const char *[]){ - "pcm_clk_out", - "pcm_codec_clk", - }, - .num_parents = 2, - .ops = &clk_regmap_mux_closest_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_rcg slimbus_src = { - .ns_reg = 0xcc, - .md_reg = 0xd0, - .mn = { - .mnctr_en_bit = 8, - .mnctr_reset_bit = 7, - .mnctr_mode_shift = 5, - .n_val_shift = 24, - .m_val_shift = 8, - .width = 8, - }, - .p = { - .pre_div_shift = 3, - .pre_div_width = 2, - }, - .s = { - .src_sel_shift = 0, - .parent_map = lcc_cxo_pll4_map, - }, - .freq_tbl = clk_tbl_aif_osr_393, - .clkr = { - .enable_reg = 0xcc, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "slimbus_src", - .parent_names = lcc_cxo_pll4, - .num_parents = 2, - .ops = &clk_rcg_ops, - .flags = CLK_SET_RATE_GATE, - }, - }, -}; - -static const char * const lcc_slimbus_parents[] = { - "slimbus_src", -}; - -static struct clk_branch audio_slimbus_clk = { - .halt_reg = 0xd4, - .halt_bit = 0, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0xcc, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "audio_slimbus_clk", - .parent_names = lcc_slimbus_parents, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_branch sps_slimbus_clk = { - .halt_reg = 0xd4, - .halt_bit = 1, - .halt_check = BRANCH_HALT_ENABLE, - .clkr = { - .enable_reg = 0xcc, - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "sps_slimbus_clk", - .parent_names = lcc_slimbus_parents, - .num_parents = 1, - .ops = &clk_branch_ops, - .flags = CLK_SET_RATE_PARENT, - }, - }, -}; - -static struct clk_regmap *lcc_mdm9615_clks[] = { - [PLL4] = &pll4.clkr, - [MI2S_OSR_SRC] = &mi2s_osr_src.clkr, - [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr, - [MI2S_DIV_CLK] = &mi2s_div_clk.clkr, - [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr, - [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr, - [PCM_SRC] = &pcm_src.clkr, - [PCM_CLK_OUT] = &pcm_clk_out.clkr, - [PCM_CLK] = &pcm_clk.clkr, - [SLIMBUS_SRC] = &slimbus_src.clkr, - [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr, - [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr, - [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr, - [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr, - [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr, - [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr, - [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr, - [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr, - [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr, - [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr, - [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr, - [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr, - [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr, - [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr, - [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr, - [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr, - [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr, - [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr, - [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr, - [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr, - [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr, - [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr, -}; - -static const struct regmap_config lcc_mdm9615_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0xfc, - .fast_io = true, -}; - -static const struct qcom_cc_desc lcc_mdm9615_desc = { - .config = &lcc_mdm9615_regmap_config, - .clks = lcc_mdm9615_clks, - .num_clks = ARRAY_SIZE(lcc_mdm9615_clks), -}; - -static const struct of_device_id lcc_mdm9615_match_table[] = { - { .compatible = "qcom,lcc-mdm9615" }, - { } -}; -MODULE_DEVICE_TABLE(of, lcc_mdm9615_match_table); - -static int lcc_mdm9615_probe(struct platform_device *pdev) -{ - u32 val; - struct regmap *regmap; - - regmap = qcom_cc_map(pdev, &lcc_mdm9615_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* Use the correct frequency plan depending on speed of PLL4 */ - regmap_read(regmap, 0x4, &val); - if (val == 0x12) { - slimbus_src.freq_tbl = clk_tbl_aif_osr_492; - mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492; - codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492; - spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492; - codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492; - spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492; - pcm_src.freq_tbl = clk_tbl_pcm_492; - } - /* Enable PLL4 source on the LPASS Primary PLL Mux */ - regmap_write(regmap, 0xc4, 0x1); - - return qcom_cc_really_probe(pdev, &lcc_mdm9615_desc, regmap); -} - -static struct platform_driver lcc_mdm9615_driver = { - .probe = lcc_mdm9615_probe, - .driver = { - .name = "lcc-mdm9615", - .of_match_table = lcc_mdm9615_match_table, - }, -}; -module_platform_driver(lcc_mdm9615_driver); - -MODULE_DESCRIPTION("QCOM LCC MDM9615 Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:lcc-mdm9615"); diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c index 3926184cc91b..5e2465f73722 100644 --- a/drivers/clk/qcom/lcc-msm8960.c +++ b/drivers/clk/qcom/lcc-msm8960.c @@ -23,6 +23,10 @@ #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" +struct clk_parent_data pxo_parent_data = { + .fw_name = "pxo", .name = "pxo_board", +}; + static struct clk_pll pll4 = { .l_reg = 0x4, .m_reg = 0x8, @@ -33,9 +37,7 @@ static struct clk_pll pll4 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll4", - .parent_data = (const struct clk_parent_data[]){ - { .fw_name = "pxo", .name = "pxo_board" }, - }, + .parent_data = &pxo_parent_data, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -51,7 +53,7 @@ static const struct parent_map lcc_pxo_pll4_map[] = { { P_PLL4, 2 } }; -static const struct clk_parent_data lcc_pxo_pll4[] = { +static struct clk_parent_data lcc_pxo_pll4[] = { { .fw_name = "pxo", .name = "pxo_board" }, { .fw_name = "pll4_vote", .name = "pll4_vote" }, }; @@ -444,6 +446,7 @@ static const struct qcom_cc_desc lcc_msm8960_desc = { static const struct of_device_id lcc_msm8960_match_table[] = { { .compatible = "qcom,lcc-msm8960" }, { .compatible = "qcom,lcc-apq8064" }, + { .compatible = "qcom,lcc-mdm9615" }, { } }; MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table); @@ -453,6 +456,14 @@ static int lcc_msm8960_probe(struct platform_device *pdev) u32 val; struct regmap *regmap; + /* patch for the cxo <-> pxo difference */ + if (of_device_is_compatible(pdev->dev.of_node, "qcom,lcc-mdm9615")) { + pxo_parent_data.fw_name = "cxo"; + pxo_parent_data.name = "cxo_board"; + lcc_pxo_pll4[0].fw_name = "cxo"; + lcc_pxo_pll4[0].name = "cxo_board"; + } + regmap = qcom_cc_map(pdev, &lcc_msm8960_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); From patchwork Fri May 12 21:17:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13239838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B725EC7EE24 for ; Fri, 12 May 2023 21:18:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240413AbjELVSJ (ORCPT ); Fri, 12 May 2023 17:18:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240415AbjELVSH (ORCPT ); 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Fri, 12 May 2023 14:17:33 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, stable@kernel.org, Neil Armstrong Subject: [PATCH v3 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock Date: Sat, 13 May 2023 00:17:23 +0300 Message-Id: <20230512211727.3445575-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> References: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: stable@kernel.org Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-mdm9615.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index fb5c1244fb97..2f921891008d 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_names = (const char *[]){ "pll0" }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, From patchwork Fri May 12 21:17:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13239844 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82941C7EE31 for ; Fri, 12 May 2023 21:18:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240418AbjELVSM (ORCPT ); Fri, 12 May 2023 17:18:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240423AbjELVSL (ORCPT ); Fri, 12 May 2023 17:18:11 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A8468A5E for ; Fri, 12 May 2023 14:17:43 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4ec8eca56cfso11696885e87.0 for ; Fri, 12 May 2023 14:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683926255; x=1686518255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6wokvLB4E/PYGVb196XdxZfYyHsIhHMceF+n+PMLHuw=; b=jMTWZTkJt/nuLsFE07djpr/e0ogBtcSyQZGJkn9DuZJLntO/Z5eXiCq/3Gkt/Wxbp9 apXsNcOsao9tYHuotuSsk8am5f14u1V9g4bf9bA2sD2oOu3Fuy2JdEN+uT1IYhu9CGiB DFHu0nJf73HL8vrr291bkqDx4edwBmDJKtFfsB+R+z7GpMqZ6f9tc1+m/rxckFo7adsv WdoxbinlWBt/su7n8LACfkuZO7Mdu1GhDPE8Qlz/qplM4UCGGttAfddbTW2sPwiFs19L u8BnKbFMNCBLzcxLshVDr8pD3wqQZaGqioCGAzNA4dvCDcjsouTcWO0TVJdZY8Pbkx0u p90Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683926255; x=1686518255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6wokvLB4E/PYGVb196XdxZfYyHsIhHMceF+n+PMLHuw=; b=Qf1oE7+WLbUX4cFKcNn+GtZjq8e57PkMDt9Jzkhk4fvkhU6TpAckKSfA5mN8d8ufQa FJwP8VynOMsVzKo9BEr7eCYM2/LfDHNu8g45ERx/ju4hAWpdSURWE6wApux5Ht+rbM6M WJHo5PF1IahTL4v+hvpX2i5cRlLM2fZ7vVcoltEXR7GFQ14ZSSW9W4yz+/H9mPTFpc8h AwiIapxn7A94gdTXMQpc/yULeTAsye913zbQcoF5VYN5Oax+X93iAZhy3a+G9RHIa3g+ B1VUtViHkU1K/FCOJriee3UBXQLLlRSiGGyDvIfHtlKIOzuWdTnTdrSifMFP9YhOfZ1n kfbg== X-Gm-Message-State: AC+VfDyg9c3jRbaWc1rm3nbCLVi38GU6csBPkknk3CJNKcxJtgpi875B 0IUH8OLRi5eSjQQIyGeTnPqi8A== X-Google-Smtp-Source: ACHHUZ5PAjsGTpj0oDS+/FVXSitqLPEeDMjULN0n+fEjRdjSLBPvd6mxH8LKcQZO5zHx5pWPCqTH1g== X-Received: by 2002:a05:6512:78:b0:4eb:3bb5:81c5 with SMTP id i24-20020a056512007800b004eb3bb581c5mr3749966lfo.15.1683926254886; Fri, 12 May 2023 14:17:34 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id w4-20020ac254a4000000b004edafe3f8dbsm1590363lfk.11.2023.05.12.14.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 14:17:34 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Date: Sat, 13 May 2023 00:17:24 +0300 Message-Id: <20230512211727.3445575-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> References: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "cxo" to "cxo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "cxo_board" clock instead of manually registered "cxo" clock and allows us to drop the cxo clock. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-mdm9615.c | 206 ++++++++++++++++++++------------- 1 file changed, 124 insertions(+), 82 deletions(-) diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 2f921891008d..458c18b639db 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -37,6 +37,25 @@ static struct clk_fixed_factor cxo = { }, }; +enum { + DT_CXO, + DT_PLL4, +}; + +enum { + P_CXO, + P_PLL8, + P_PLL14, +}; + +static const struct parent_map gcc_cxo_map[] = { + { P_CXO, 0 }, +}; + +static const struct clk_parent_data gcc_cxo[] = { + { .index = DT_CXO, .name = "cxo_board" }, +}; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -47,8 +66,8 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll0", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -58,7 +77,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll0" }, + .parent_hws = (const struct clk_hw*[]) { + &pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -69,7 +90,9 @@ static struct clk_regmap pll4_vote = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "pll4_vote", - .parent_names = (const char *[]){ "pll4" }, + .parent_data = &(const struct clk_parent_data) { + .index = DT_PLL4, .name = "pll4", + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -85,8 +108,8 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -96,7 +119,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_hws = (const struct clk_hw*[]) { + &pll8.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -112,8 +137,8 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll14", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -123,26 +148,22 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_names = (const char *[]){ "pll14" }, + .parent_hws = (const struct clk_hw*[]) { + &pll14.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, }; -enum { - P_CXO, - P_PLL8, - P_PLL14, -}; - static const struct parent_map gcc_cxo_pll8_map[] = { { P_CXO, 0 }, { P_PLL8, 3 } }; -static const char * const gcc_cxo_pll8[] = { - "cxo", - "pll8_vote", +static const struct clk_parent_data gcc_cxo_pll8[] = { + { .index = DT_CXO, .name = "cxo_board" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_cxo_pll14_map[] = { @@ -150,17 +171,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = { { P_PLL14, 4 } }; -static const char * const gcc_cxo_pll14[] = { - "cxo", - "pll14_vote", -}; - -static const struct parent_map gcc_cxo_map[] = { - { P_CXO, 0 }, -}; - -static const char * const gcc_cxo[] = { - "cxo", +static const struct clk_parent_data gcc_cxo_pll14[] = { + { .index = DT_CXO, .name = "cxo_board" }, + { .hw = &pll14_vote.hw }, }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -206,7 +219,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -222,8 +235,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -257,7 +270,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -273,8 +286,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -308,7 +321,7 @@ static struct clk_rcg gsbi3_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -324,8 +337,8 @@ static struct clk_branch gsbi3_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_clk", - .parent_names = (const char *[]){ - "gsbi3_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi3_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -359,7 +372,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -375,8 +388,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -410,7 +423,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -426,8 +439,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -473,7 +486,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -489,7 +502,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi1_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -522,7 +537,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -538,7 +553,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi2_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -571,7 +588,7 @@ static struct clk_rcg gsbi3_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -587,7 +604,9 @@ static struct clk_branch gsbi3_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_clk", - .parent_names = (const char *[]){ "gsbi3_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi3_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -620,7 +639,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -636,7 +655,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi4_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -669,7 +690,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -685,7 +706,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi5_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -724,7 +747,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -740,7 +763,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp0_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -773,7 +798,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -789,7 +814,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -822,7 +849,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -838,7 +865,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -874,7 +903,7 @@ static struct clk_rcg prng_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -890,7 +919,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_hws = (const struct clk_hw*[]) { + &prng_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -936,7 +967,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -951,7 +982,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_hws = (const struct clk_hw*[]) { + &sdc1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -984,7 +1017,7 @@ static struct clk_rcg sdc2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc2_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -999,7 +1032,9 @@ static struct clk_branch sdc2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc2_clk", - .parent_names = (const char *[]){ "sdc2_src" }, + .parent_hws = (const struct clk_hw*[]) { + &sdc2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1037,7 +1072,7 @@ static struct clk_rcg usb_hs1_xcvr_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1053,7 +1088,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hs1_xcvr_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1086,7 +1123,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1102,8 +1139,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_clk", - .parent_names = - (const char *[]){ "usb_hsic_xcvr_fs_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_xcvr_fs_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1141,7 +1179,7 @@ static struct clk_rcg usb_hs1_system_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_system_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1156,8 +1194,9 @@ static struct clk_branch usb_hs1_system_clk = { .enable_reg = 0x36a4, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = - (const char *[]){ "usb_hs1_system_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hs1_system_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hs1_system_clk", .ops = &clk_branch_ops, @@ -1196,7 +1235,7 @@ static struct clk_rcg usb_hsic_system_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_system_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1211,8 +1250,9 @@ static struct clk_branch usb_hsic_system_clk = { .enable_reg = 0x2b58, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = - (const char *[]){ "usb_hsic_system_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_system_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hsic_system_clk", .ops = &clk_branch_ops, @@ -1251,7 +1291,7 @@ static struct clk_rcg usb_hsic_hsic_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_hsic_src", - .parent_names = gcc_cxo_pll14, + .parent_data = gcc_cxo_pll14, .num_parents = ARRAY_SIZE(gcc_cxo_pll14), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1265,7 +1305,9 @@ static struct clk_branch usb_hsic_hsic_clk = { .enable_reg = 0x2b50, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "usb_hsic_hsic_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_hsic_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hsic_hsic_clk", .ops = &clk_branch_ops, @@ -1281,8 +1323,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = { .enable_reg = 0x2b48, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .name = "usb_hsic_hsio_cal_clk", .ops = &clk_branch_ops, }, From patchwork Fri May 12 21:17:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13239840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEC38C83005 for ; Fri, 12 May 2023 21:18:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240417AbjELVSK (ORCPT ); Fri, 12 May 2023 17:18:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240423AbjELVSI (ORCPT ); Fri, 12 May 2023 17:18:08 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C64B93ED for ; Fri, 12 May 2023 14:17:43 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4f1fe1208a4so8838727e87.2 for ; Fri, 12 May 2023 14:17:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683926255; x=1686518255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CWMNT07qFC9FaIB+soq8G5lluprlR23tOWvaEOZLetQ=; b=cIPaom3wezsX11bH/sBVZ2pG7UEB3pQFipRO3osb/jJxblZ3uFbEP/3fQTloCb5qQS qIKNk9YS1UefS1feMFgWSnWGdnfXHRc5M/3qAQuZ+ereZfzR2S3+4yrujd/eebC7Dkgq FLTmkHNtW7NZG8ipKfG7hbWbyYGu6Y60S8HQz/NbQXy4VnPd0dLhOChC2Bzjt1tse28S LG5HoNWX8n/1if1UOdOU6E7kIUpaMVK217/ysJquhxJMawQH5ARSOoLgdk94410H15x2 RuQToiVhFn3hwlHd8Wqo/fI2dUiC4fT1+KxmKZtZ7RavlwB4rFI0Mb9fvMa866wo9WVo QfAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683926255; x=1686518255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CWMNT07qFC9FaIB+soq8G5lluprlR23tOWvaEOZLetQ=; b=YSDJXfgO6L1cMOPUbq9jZbQawBOQqg9tAIgwqAgxcVJkLlZUMMtSgZuSOBUfMh5NKl /plXHX6u5o3pQ0tFKWazuTwhzwk+lM56F4owfx/JR0dmpeMQk3LSVLct6vLjaE6SrxI5 wTEQicpYBk4PuvJ9ll+5e5IqHRDvfXkHym4vUKosEZ/bR9ywxfBYth6zXRmdStuZmooG Kgu8hUch/psegEgumebuaB3rSxK+c1X/Hlgyi83BAY46Ypmxs5V2Sv2ei6GEPwNOK3UL LnQsPETqINSuzpnLxbF0t+IZYZ0OIf14TpqLn0YJ99OqyvU+clszAvkSp3A5zzixBEAx A09w== X-Gm-Message-State: AC+VfDxuw6R7bVU8ZKc8ZxrZvMqxju1FJVHmCKu8QVq8MX68YQ36R6Kj 7TXKt2yhLtWyMB4qqNNYu9dWHQ== X-Google-Smtp-Source: ACHHUZ5zrLF+O/LpG2j37bluYQcdJUzTojWzv2VX0mN4f2ln7RSXN8FFUz5mLA7bn9yLm4apZ65wqA== X-Received: by 2002:ac2:546b:0:b0:4ed:b329:5d85 with SMTP id e11-20020ac2546b000000b004edb3295d85mr4006830lfn.15.1683926255710; Fri, 12 May 2023 14:17:35 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id w4-20020ac254a4000000b004edafe3f8dbsm1590363lfk.11.2023.05.12.14.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 14:17:35 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 08/10] clk: qcom: gcc-mdm9615: drop the cxo clock Date: Sat, 13 May 2023 00:17:25 +0300 Message-Id: <20230512211727.3445575-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> References: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The gcc and lcc devices have been switched to the DT-defined cxo_board clock. Now we can drop the manually defined cxo clock. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-mdm9615.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 458c18b639db..64d4f508e43a 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -26,17 +26,6 @@ #include "clk-branch.h" #include "reset.h" -static struct clk_fixed_factor cxo = { - .mult = 1, - .div = 1, - .hw.init = &(struct clk_init_data){ - .name = "cxo", - .parent_names = (const char *[]){ "cxo_board" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - enum { DT_CXO, DT_PLL4, @@ -1623,10 +1612,6 @@ static struct clk_branch ebi2_aon_clk = { }, }; -static struct clk_hw *gcc_mdm9615_hws[] = { - &cxo.hw, -}; - static struct clk_regmap *gcc_mdm9615_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, @@ -1736,8 +1721,6 @@ static const struct qcom_cc_desc gcc_mdm9615_desc = { .num_clks = ARRAY_SIZE(gcc_mdm9615_clks), .resets = gcc_mdm9615_resets, .num_resets = ARRAY_SIZE(gcc_mdm9615_resets), - .clk_hws = gcc_mdm9615_hws, - .num_clk_hws = ARRAY_SIZE(gcc_mdm9615_hws), }; static const struct of_device_id gcc_mdm9615_match_table[] = { From patchwork Fri May 12 21:17:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13239842 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DEA3C87FDC for ; Fri, 12 May 2023 21:18:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240546AbjELVSN (ORCPT ); Fri, 12 May 2023 17:18:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240477AbjELVSM (ORCPT ); Fri, 12 May 2023 17:18:12 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9610C7ED2 for ; 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Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index b40c52ddf9b4..556abe90cf5b 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -39,7 +39,7 @@ cpu-pmu { }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; @@ -113,6 +113,20 @@ lcc: clock-controller@28000000 { reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&cxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "cxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; l2cc: clock-controller@2011000 { From patchwork Fri May 12 21:17:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13239843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 651DAC87FE2 for ; Fri, 12 May 2023 21:18:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240550AbjELVSO (ORCPT ); Fri, 12 May 2023 17:18:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240423AbjELVSM (ORCPT ); Fri, 12 May 2023 17:18:12 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 897388A7D for ; Fri, 12 May 2023 14:17:50 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2ac7de2b72fso115789321fa.1 for ; Fri, 12 May 2023 14:17:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683926257; x=1686518257; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UhWJCvsiOM+PbnYgsNzdrZ31BrHJ3YrqzSWfh68CWBg=; b=LTCeDjNIPw9zFiuXJu99yoJ6EnntXtG3+RtvRtFiyUPyHdAcDwFqQEyveGm941vond 0RKkviUk1NZ8eX3A5HRLZfCet6/FFjlj2rmWeRk022gSQjdMCjtuHp7Pyl5Z3KeO+uJ+ zqOkuNvAx6LJAftmVG6DZiE8ksQAc+xaC92KUMoYPoJrc48iM5Hnw7MwtiGL+YNLsVib l+1V5SJmNc1uY2pKe0cnr1roau8Cwv2LiLJC/zh6/a1VS4aM/WAfpZCIcq88Z6iz1j+9 fdT6r2J8wQGxZwJe7N7DfwVKlMO0y270kBk71hJW4HM3/5gRSPnmBAwCOj8i7RhhgQoD jxJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683926257; x=1686518257; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UhWJCvsiOM+PbnYgsNzdrZ31BrHJ3YrqzSWfh68CWBg=; b=APDKvQhz1cIkH56OyafUKfpDetyBWux8rIwTZn6NPpE2UDQWkxhulxugFFCyC8GFbu O7IPsDeLN4D7aTsUxh260C9IASvkjRTHmrLXM7My3fEo5GqDCkFbDOpFGvrHMgNiYunJ wJ478VwDLDVr165Jtx/6Il5RVoiIrYNqDdTvkdQqtjQniUY2Mf0ahvqyINGiu/E18gWW wLWNuDgrkKlSo9sz1hT1G+Vp97Mwld61AJj7eKwbBrLc6Yx3YXsy0Cdk6iNzKfzra/6W TpQlwMx2bWmT0uCZCdanaTnb9vtU5MH5OFy0Eyh1mzuYvZHef0VHQAa2q26J7Mre7ayW qD/Q== X-Gm-Message-State: AC+VfDwEQO0tEyhKY8snJ0GLSfMh7AEcM9UWnK+kq16wxBp8T5V/B+Jj UWzaSBI/uX1e9QZQg8LgqE2zHw== X-Google-Smtp-Source: ACHHUZ64lNbAweb8iOnKkk1XHLEikx3Xor5qRBwHiMlnolDco6DeWqdIFsODjadj1J5mvoqdPuF/LA== X-Received: by 2002:ac2:44cc:0:b0:4e8:3fca:4927 with SMTP id d12-20020ac244cc000000b004e83fca4927mr3971478lfm.58.1683926257521; Fri, 12 May 2023 14:17:37 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id w4-20020ac254a4000000b004edafe3f8dbsm1590363lfk.11.2023.05.12.14.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 May 2023 14:17:37 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks Date: Sat, 13 May 2023 00:17:27 +0300 Message-Id: <20230512211727.3445575-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> References: <20230512211727.3445575-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fully specify the clocks used by the GCC on the mdm9615 platform. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 556abe90cf5b..fc4f52f9e9f7 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -106,6 +107,8 @@ gcc: clock-controller@900000 { #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&cxo_board>, + <&lcc PLL4>; }; lcc: clock-controller@28000000 {