From patchwork Sat May 13 08:05:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13240092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5674DC77B7F for ; Sat, 13 May 2023 08:07:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pxkGH-0000h9-1J; Sat, 13 May 2023 04:05:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxkGB-0000bb-92 for qemu-devel@nongnu.org; Sat, 13 May 2023 04:05:47 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pxkG9-00056w-6a for qemu-devel@nongnu.org; Sat, 13 May 2023 04:05:47 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f41dceb9d4so78533765e9.1 for ; Sat, 13 May 2023 01:05:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683965142; x=1686557142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dHRV3Xek8jw+Z4jb1DFEO6p5BvBIXzddq9qz2fsYJuo=; b=kMTHevfW7d5pZEGTOgffhUAvdiVZ5jugE1WLaAeiVpg6Il9C2+NmauVbzSsNDvQEqa 7Mu38BpQBsaywqK2AGOAa8m/SowI9Rvz4/IvTrvf+jaEhFa1uzEmO6w7W0lZU+4xETaV A58MZjO5nh+3Su7VvXw9vuZ85Zwo4mPZwk9pCq9YubBvdUtaVUprwfTSQ7MEFaKJBzez DfHKDvze/5BJrtVtFm9+lE7dObaVP0D7bJohXJalmgLQFmgCp5FFzfifxm7lo3/qYqiK UWxylyq8AIWyZqHAOu7bLoKLeNHC3rJJUtWoZjcYobwGMVVE5Bd5Rc29YPXG77/Eyryg Wd7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683965142; x=1686557142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dHRV3Xek8jw+Z4jb1DFEO6p5BvBIXzddq9qz2fsYJuo=; b=I4DmPPNkIj+lsg+KbWnsCK92VX8d3DpDXogVGKOD8o7lUhiHratPPcEbZWbBV2JR9y e5UzbcaXC+OxDGORV1pZbGieDmJSyJQZC76cOxX6lqzZZuf5fnrAVFRH7CvyLyeNJgJp JvULXQSprhAIdrnMvJBaVBvthDOJpwK/E+/zbWvEGFnmmj9K/gxO3bTq/oZbQEPTjOPQ pelZ09BRvX4n17nxDyg0kkHZivGxfsnopByox0W6YMtONzEkhdYNVEis0AU6EThYDJCh bnT27O5GqFRHhyjflcpxlxWxskNhM118f19HV7FZ8hOOo3KKTVXvh3/+kU5KfBSHMohi EhkA== X-Gm-Message-State: AC+VfDxQ0mHCW/R5s2iQSIK+pOKxqCzZOOdoUVSE4ISkCoibK+F/vLWY df9GEN21nki9WRh++vJcWEh7/NjmlT8= X-Google-Smtp-Source: ACHHUZ6IMjefbst6OiILLEOPvV3wKAAAps3cuS3JLvpmhyIw5v+pacIwH6D9jO++JH5KIdPb43Sf+w== X-Received: by 2002:a05:600c:228e:b0:3f4:2174:b28a with SMTP id 14-20020a05600c228e00b003f42174b28amr18741696wmf.15.1683965141687; Sat, 13 May 2023 01:05:41 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id s7-20020a1cf207000000b003f1733feb3dsm30811688wmc.0.2023.05.13.01.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 May 2023 01:05:40 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Stafford Horne , Richard Henderson Subject: [PULL 1/3] target/openrisc: Allow fpcsr access in user mode Date: Sat, 13 May 2023 09:05:32 +0100 Message-Id: <20230513080534.580800-2-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230513080534.580800-1-shorne@gmail.com> References: <20230513080534.580800-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=shorne@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As per OpenRISC spec 1.4 FPCSR can be read and written in user mode. Update mtspr and mfspr helpers to support this by moving the is_user check into the helper. Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- target/openrisc/sys_helper.c | 45 ++++++++++++++++------ target/openrisc/translate.c | 72 ++++++++++++++++-------------------- 2 files changed, 66 insertions(+), 51 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ec145960e3..ccdee3b8be 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -29,17 +29,37 @@ #define TO_SPR(group, number) (((group) << 11) + (number)) +static inline bool is_user(CPUOpenRISCState *env) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return (env->sr & SR_SM) == 0; +#endif +} + void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) { -#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = env_archcpu(env); +#ifndef CONFIG_USER_ONLY CPUState *cs = env_cpu(env); target_ulong mr; int idx; #endif + /* Handle user accessible SPRs first. */ switch (spr) { + case TO_SPR(0, 20): /* FPCSR */ + cpu_set_fpcsr(env, rb); + return; + } + + if (is_user(env)) { + raise_exception(cpu, EXCP_ILLEGAL); + } + #ifndef CONFIG_USER_ONLY + switch (spr) { case TO_SPR(0, 11): /* EVBAR */ env->evbar = rb; break; @@ -187,27 +207,33 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) cpu_openrisc_timer_update(cpu); qemu_mutex_unlock_iothread(); break; -#endif - - case TO_SPR(0, 20): /* FPCSR */ - cpu_set_fpcsr(env, rb); - break; } +#endif } target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, target_ulong spr) { + OpenRISCCPU *cpu = env_archcpu(env); #ifndef CONFIG_USER_ONLY uint64_t data[TARGET_INSN_START_WORDS]; MachineState *ms = MACHINE(qdev_get_machine()); - OpenRISCCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); int idx; #endif + /* Handle user accessible SPRs first. */ switch (spr) { + case TO_SPR(0, 20): /* FPCSR */ + return env->fpcsr; + } + + if (is_user(env)) { + raise_exception(cpu, EXCP_ILLEGAL); + } + #ifndef CONFIG_USER_ONLY + switch (spr) { case TO_SPR(0, 0): /* VR */ return env->vr; @@ -324,11 +350,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, cpu_openrisc_count_update(cpu); qemu_mutex_unlock_iothread(); return cpu_openrisc_count_get(cpu); -#endif - - case TO_SPR(0, 20): /* FPCSR */ - return env->fpcsr; } +#endif /* for rd is passed in, if rd unchanged, just keep it back. */ return rd; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 76e53c78d4..43ba0cc1ad 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -819,45 +819,12 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a) static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) { - check_r0_write(dc, a->d); - - if (is_user(dc)) { - gen_illegal_exception(dc); - } else { - TCGv spr = tcg_temp_new(); - - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - if (dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - } else { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); - } - dc->base.is_jmp = DISAS_EXIT; - } + TCGv spr = tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); - } - return true; -} - -static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) -{ - if (is_user(dc)) { - gen_illegal_exception(dc); - } else { - TCGv spr; + check_r0_write(dc, a->d); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - /* For SR, we will need to exit the TB to recognize the new - * exception state. For NPC, in theory this counts as a branch - * (although the SPR only exists for use by an ICE). Save all - * of the cpu state first, allowing it to be overwritten. - */ + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); if (dc->delayed_branch) { tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_discard_tl(jmp_pc); @@ -865,11 +832,36 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); } dc->base.is_jmp = DISAS_EXIT; + } + + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); + return true; +} + +static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) +{ + TCGv spr = tcg_temp_new(); - spr = tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); } + /* + * For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp = DISAS_EXIT; + + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); return true; } From patchwork Sat May 13 08:05:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13240093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45C36C77B7F for ; Sat, 13 May 2023 08:07:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pxkGD-0000go-Il; Sat, 13 May 2023 04:05:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxkGB-0000ba-4u for qemu-devel@nongnu.org; Sat, 13 May 2023 04:05:47 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pxkG9-000576-Ih for qemu-devel@nongnu.org; Sat, 13 May 2023 04:05:46 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3062db220a3so7019877f8f.0 for ; Sat, 13 May 2023 01:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683965143; x=1686557143; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kk1SZdthGI97ZtAraCpLe6062EPa77UtYxoYCQVHTcE=; b=eImgkpUpqSWydxD4C3I0DbQwcWoro2oqZcqKqhGWaHOZJffYgPQeXIkxNDfgbsU8HA 1I2eKHrzivOU2tqfeJ1swlqBXc4odIVlWg9E3Q9kGhN/a8wSxTlUmjwlXflagqdsqvm4 8Dpcn2lpq5NcMRTlk4oYex6X5d66e4RIGL1Bdu5GIdtEfXudGa0VRe3sO+CHq51/WliY hfef34hCKuuxZDGw9ibjpjSBoqj3tbNDRT9tIPuKvKSosCCRX32NSTiJdQzMulFnma83 44YlSqk45cuKvliLbPgXCHWXZbHFqx1cJz/5MOsueD47Ti8xIHaZMzxptOG1akV8YvDz cSLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683965143; x=1686557143; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kk1SZdthGI97ZtAraCpLe6062EPa77UtYxoYCQVHTcE=; b=IrdYtTvLmNdsF36DBbudifSs7xew1pTPHZhgXZZ4QK6wkm1iJ+FYlumwyj+Zq+Mkxk jx3xZlljvBZNJpAFffyt5eySRf0TR2/XmkGng0n8o+R78YERIHZ1seQCFxuG8wUH2/FE CAX7pzC4+sc9Kx1WC+2uURXAs/taFgVgCUCg1pNplhx9olBhgh+/JS+9Wsob2Bmzbv+p xrpNnxpXnfIS0etIM+X3Hzs46mcpgOG1xD1hbRurq0KTbl8ND9ZdLWQpAaxQWdt0P8wE oLxlN+7yx1kpGyRYcTLZE2HFgU/CWI0kFdpZtHLiYES4ffCLpY+BnQBIvtghZV8oUfEH hdzA== X-Gm-Message-State: AC+VfDyNuLFkHfjOqCX1hUaGpxXOh+sFLvg5zL5E+yHhkmB2cQN7Mvjb NYC41Wnj9Ac5nunJChYziFDb/70iM/o= X-Google-Smtp-Source: ACHHUZ5GIVTsrQ3IHSnYgIzRrva92+28hg251EyYh1v4sR+UvbfmXbpD/SgHxWMgY8Yq9Vt4HmFUeQ== X-Received: by 2002:a05:6000:104b:b0:2e4:eebe:aee3 with SMTP id c11-20020a056000104b00b002e4eebeaee3mr17115701wrx.60.1683965142741; Sat, 13 May 2023 01:05:42 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id x18-20020a5d6b52000000b002ff2c39d072sm25752559wrw.104.2023.05.13.01.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 May 2023 01:05:42 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Stafford Horne , Richard Henderson Subject: [PULL 2/3] target/openrisc: Set PC to cpu state on FPU exception Date: Sat, 13 May 2023 09:05:33 +0100 Message-Id: <20230513080534.580800-3-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230513080534.580800-1-shorne@gmail.com> References: <20230513080534.580800-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=shorne@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Store the PC to ensure the correct value can be read in the exception handler. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- target/openrisc/fpu_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index f9e34fa2cc..8b81d2f62f 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -20,8 +20,8 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exception.h" #include "fpu/softfloat.h" static int ieee_ex_to_openrisc(int fexcp) @@ -45,6 +45,15 @@ static int ieee_ex_to_openrisc(int fexcp) return ret; } +static G_NORETURN +void do_fpe(CPUOpenRISCState *env, uintptr_t pc) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = EXCP_FPE; + cpu_loop_exit_restore(cs, pc); +} + void HELPER(update_fpcsr)(CPUOpenRISCState *env) { int tmp = get_float_exception_flags(&env->fp_status); @@ -55,7 +64,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env) if (tmp) { env->fpcsr |= tmp; if (env->fpcsr & FPCSR_FPEE) { - helper_exception(env, EXCP_FPE); + do_fpe(env, GETPC()); } } } From patchwork Sat May 13 08:05:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13240091 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D82DC7EE24 for ; Sat, 13 May 2023 08:06:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pxkGE-0000gt-OO; Sat, 13 May 2023 04:05:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pxkGB-0000bq-Sm for qemu-devel@nongnu.org; Sat, 13 May 2023 04:05:47 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pxkGA-000578-3e for qemu-devel@nongnu.org; Sat, 13 May 2023 04:05:47 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-30626f4d74aso7022606f8f.0 for ; Sat, 13 May 2023 01:05:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683965144; x=1686557144; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3qQzmOCm9I15s8dR1uKLFgkkYWJssm91+59ldpNI9f0=; b=DW1nJ5NkvvzmvExIbWU6HJeBzGWZ+HxQWRVjxVwJqWZVKBFurr7n20nZ1wNh2kn0rF HXHJwLtwLFLo8Y1IdIQbaEKf6jV0JdssbkGfYLuHJZkW33n/AWZdnr6ivDu/etCo2n7Q z3soC3EclabGlwLim7AYiTRwyYqj+uanXqyWPk9iMq5tOb/8Yo/j8EjGx5ios8Ob2ovU KNjVDYuq7Twi2VSqu91/xuaQOpAsXctyGuH/SVzK0V7jyuH1kRjuquGzh/eMFXbZgK0E rcwp2wQsu7TS684CV+upVrsiHg7fxR50UD+xudbj/67HgvWAIjJBiGAjDmDCacm8JNmZ Sg7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683965144; x=1686557144; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3qQzmOCm9I15s8dR1uKLFgkkYWJssm91+59ldpNI9f0=; b=FZtzSppPGknvH5Em6fRuEXhbDBP2KWYfrmMIV9XBMXAyjuRmY9o/wLZUAtmmOilKaL e0p8Jnw1UnDIbxlWW/Utp2uXuCgMLtgNXrdBJUqaZptCg4pu9di/LpCiVooQDOnIGI2e Im+wsMb+NSs8wY2PtAXWFRa6CpVtOa8F/F3NPydLc/NA3CVYVbr0IEMEl65YBEq/V9/m vVx/I1eiUxTdDWnRQudYuEjdLEKD2mJtjGp7BKeHhY+OrRvdO0QpRZtkdQcdN7X62cdQ crjfvIyZM6hz6xuHU7FyHEpJNv82UuQN0thKBTdofxEukIG4KGeA2aF/rddUA0De+ozT +t9g== X-Gm-Message-State: AC+VfDyL9VeGcLY/gnVTSUYdTwePMl20OCoZOi5ubrCUGQ+cFPvIkX/j 5qHjZLm05Jx0LDlpyUnSH+a75xjjqY0= X-Google-Smtp-Source: ACHHUZ6wD9Iwe14wdDZIsLyYcUjLL34JF9m24I+5YALt4+Kg8NyOewMlbvrIWnxI9Fsdap9T5NPifA== X-Received: by 2002:adf:e784:0:b0:309:99c:f23f with SMTP id n4-20020adfe784000000b00309099cf23fmr949514wrm.63.1683965143785; Sat, 13 May 2023 01:05:43 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id x20-20020a1c7c14000000b003f17af4c4e0sm30625293wmc.9.2023.05.13.01.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 May 2023 01:05:43 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Stafford Horne , Richard Henderson Subject: [PULL 3/3] target/openrisc: Setup FPU for detecting tininess before rounding Date: Sat, 13 May 2023 09:05:34 +0100 Message-Id: <20230513080534.580800-4-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230513080534.580800-1-shorne@gmail.com> References: <20230513080534.580800-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=shorne@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org OpenRISC defines tininess to be detected before rounding. Setup qemu to obey this. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- target/openrisc/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 0ce4f796fa..61d748cfdc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -90,6 +91,9 @@ static void openrisc_cpu_reset_hold(Object *obj) s->exception_index = -1; cpu_set_fpcsr(&cpu->env, 0); + set_float_detect_tininess(float_tininess_before_rounding, + &cpu->env.fp_status); + #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; cpu->env.picsr = 0x00000000;