From patchwork Fri Feb 1 16:46:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10793335 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 07C8C13B5 for ; Fri, 1 Feb 2019 16:48:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ECCFC324D3 for ; Fri, 1 Feb 2019 16:48:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E0270324EA; Fri, 1 Feb 2019 16:48:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D9ED324D3 for ; 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Fri, 1 Feb 2019 16:47:17 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Date: Fri, 1 Feb 2019 17:46:45 +0100 Message-Id: <1549039612-28905-2-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTURzv7O7uXleL6+bjZGIw7U0uwQ8XsrLHh6FfwoysLLvlTa1t2q7z kUZW5mNYioJa5INIpnOhTlExpzmXI0Q3U3ylMRoRli58o2Dl3K2+/f6/x/n/zuHgiLAO9cET FMm0UkHJxDw+t7VvbfCIV1pk9NGJCgnZVN6AkmNL31CyyjSIkoX2HwhpsTRi5MCjWYyczPIl 9fZRlBzueMkjF5+aAFlu6eKQb0zTGFkzNsQhPz2s5ZFPDCaM7J3NRUMJqa5SB6R6bT5P2vz6 gbTH0cmRPmvRAumi3u8c7zI/JJaWJaTQSsmJ6/z4tkJ+kk2QZrP5ZwHTdjVwwyERDPuqu4Ea 8HEhUQugdbKDHZYA7NZrUNewCKC6d4T3N6LLHcVcggbAx0Xz3H8Re3bZpoLjPCIQtmvvOgMe RAacGutGnB6EmOJAw/MarlMQEefhatcE5sRcYi/sfv9uCwuIMLiqs2KubX5wYjAfcWI3Ihzm 2du2+kFCj8GV5UGuy3QWri00c1xYBL+bW9iwL+wvKWA9DBzI07JXyIS5H9pZzzHYax5CnaUR 4iBs6JC46FNw6JVxi4bETjg+5+6kkU1Y3FqGuGgBzMsRutwHYEuBlS3gBTW6UvZwKZx1lLKP WAngyNdOpAjsefF/WTUAWuBNqxh5HM0EKejUQIaSMypFXODNRLkebH6g/l/mhXaw/PGGERA4 EO8QNK5HRAtRKoVJlxsBxBGxh+D07chooSCWSr9HKxNjlCoZzRjBbpwr9hZkbLNdERJxVDJ9 h6aTaOVflYO7+WSBfTGqes79hplUgwVLOqPfuCbK+ay21nnIkoI8HSVZP2eM2UYwMm0OCKkF 9Ear529rkySs2PG2x1190RYl0/TP1mdeiEqp6kwYN1Mr+/HKiC9uiXbf9YrDt4yXdmn8C6KW rip086Lg412OkOHwOTl/I2XOMOx3UlcV0DIcWijmMvFU0CFEyVB/AO82ZRk8AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkkeLIzCtJLcpLzFFi42I5/e/4PV3RipAYg/Wr9Sw2zljPanH9y3NW i/lHzrFa9D9+zWxx/vwGdouzTW/YLW41yFhsenyN1eLyrjlsFp97jzBazDi/j8li7ZG77BZL r19ksrjduILNonXvEXaLw2/aWR0EPNbMW8PosWlVJ5vH5iX1Hgff7WHy6NuyitHj8ya5ALYo PZui/NKSVIWM/OISW6VoQwsjPUNLCz0jE0s9Q2PzWCsjUyV9O5uU1JzMstQifbsEvYzt/VwF D3grHjxQbmA8wt3FyMkhIWAisab9GnsXIxeHkMBSRom2Xa2sEAkxiUn7trND2MISf651sUEU fWKUaFzxlqmLkYODTUBPYseqQpAaEYF6if43l9hAbGaBV0wSDe81QEqEBQIlOhaqgoRZBFQl 9h89ADaSV8BL4vuaC1Dj5SRunutkBrE5BbwlOh5vZwSxhYBqVv07wDyBkW8BI8MqRpHU0uLc 9NxiI73ixNzi0rx0veT83E2MwGjYduznlh2MXe+CDzEKcDAq8fBu+BUUI8SaWFZcmXuIUYKD WUmE1ykrJEaINyWxsiq1KD++qDQntfgQoynQUROZpUST84GRmlcSb2hqaG5haWhubG5sZqEk znveoDJKSCA9sSQ1OzW1ILUIpo+Jg1OqgdG4VDtTSPr21KU3a3nYLsdrBIV31W+/IqL86uHR jraoHGEeh9Ns/HNOq+ZvfefVMM3y5Fw54zT5gEy+67/3Kn52bD6V3JqccsA54T+PPGt5z6rZ 9qxVOtVViw1POarVPylnZbxr1cWw2Hr9h8+cHk7FQaF+D1WXFK5d09DowlTxVUB/xzMvJZbi jERDLeai4kQAEk/QtJwCAAA= X-CMS-MailID: 20190201164718eucas1p1bca3a199d60e109e1da654d8afff2a47 X-Msg-Generator: CA X-RootMTR: 20190201164718eucas1p1bca3a199d60e109e1da654d8afff2a47 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164718eucas1p1bca3a199d60e109e1da654d8afff2a47 References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. Signed-off-by: Lukasz Luba Acked-by: Rob Herring --- include/dt-bindings/clock/exynos5420.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469..0d00fbb 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,16 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +228,8 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_SCLK_SPLL 660 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -248,8 +261,9 @@ #define CLK_DOUT_CCLK_DREX0 794 #define CLK_DOUT_CLK2X_PHY0 795 #define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_FF_DOUT_SPLL2 797 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 798 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ From patchwork Fri Feb 1 16:46:46 2019 Content-Type: text/plain; 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Fri, 1 Feb 2019 16:47:17 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC Date: Fri, 1 Feb 2019 17:46:46 +0100 Message-Id: <1549039612-28905-3-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPKsWRmVeSWpSXmKPExsWy7djP87riFSExBufnqFlsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLHY9Pgaq8XHnnusFpd3zWGz+Nx7hNFixvl9TBZr j9xlt7h4ytXiduMKNovDb9pZLf5d28jiIOjx/kYru8emVZ1sHpuX1HscfLeHyaNvyypGj8+b 5ALYorhsUlJzMstSi/TtErgy+q9cZC24plVxeedp5gbGSypdjJwcEgImElsX97N2MXJxCAms YJToOPOIEcL5wihxfPpuJgjnM6NE97lvrDAte478YYdILGeUmHpwCjtcy5Ztj4AcDg42AT2J HasKQRpEBKol7lzfzwxSwyzQwCyxo2kCC0hCWCBQYuajfjYQm0VAVeJE6wUwm1fAS2LJ5DZG iG1yEjfPdTKD2JwC3hIdj7eD3SchsI9d4vrnK0wQRS4S+xb+YYawhSVeHd/CDmHLSPzfOR+q pljibMcqNgi7RqL95A6oGmuJw8cvsoIczSygKbF+lz5E2FFi8dtdTCBhCQE+iRtvBUHCzEDm pG3TmSHCvBIdbUIQ1RoSW3ouQC0Sk1i+ZhrUcA+JAx82QoNnHqPE2y99bBMY5WchLFvAyLiK UTy1tDg3PbXYKC+1XK84Mbe4NC9dLzk/dxMjMBmd/nf8yw7GXX+SDjEKcDAq8fBu+BUUI8Sa WFZcmXuIUYKDWUmE1ykrJEaINyWxsiq1KD++qDQntfgQozQHi5I4bzXDg2ghgfTEktTs1NSC 1CKYLBMHp1QDo+cUrrnXmCbMLHINqv/qvuT3b6/Nmu9WM545lWZ/pPO7w9dJqvuO5jdfZMv9 lpLu3vbWZzn3SevKafGPdX4Vu1y6qXrUYcp3lmk/VeatfGaZUWTwPiqbKfnwbOF7d055uwiy 761kn35XcFtu/yeTL1kZ+b39G6b11z9ctvaEbQGj06bDTHJNlkosxRmJhlrMRcWJAEQYNONC AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsVy+t/xe7piFSExBnsWyltsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLHY9Pgaq8XHnnusFpd3zWGz+Nx7hNFixvl9TBZr j9xlt7h4ytXiduMKNovDb9pZLf5d28jiIOjx/kYru8emVZ1sHpuX1HscfLeHyaNvyypGj8+b 5ALYovRsivJLS1IVMvKLS2yVog0tjPQMLS30jEws9QyNzWOtjEyV9O1sUlJzMstSi/TtEvQy +q9cZC24plVxeedp5gbGSypdjJwcEgImEnuO/GHvYuTiEBJYyijxeMkdRoiEmMSkfdvZIWxh iT/Xutggij4xSqxauoq1i5GDg01AT2LHqkKQGhGBeon+N5fAapgF+pglGo8vZgVJCAv4S7R1 7AEbxCKgKnGi9QIbiM0r4CWxZHIb1DI5iZvnOplBbE4Bb4mOx9vB4kJANav+HWCewMi3gJFh FaNIamlxbnpusaFecWJucWleul5yfu4mRmB0bDv2c/MOxksbgw8xCnAwKvHwbvgVFCPEmlhW XJl7iFGCg1lJhNcpKyRGiDclsbIqtSg/vqg0J7X4EKMp0FETmaVEk/OBkZtXEm9oamhuYWlo bmxubGahJM573qAySkggPbEkNTs1tSC1CKaPiYNTqoHRQT3tzs9Tyw105LlnbeLd98NUtCil dtbSOZueJl1fstk2tMBvosfDyP4ja02jTH0W3Y+x2ZHTs+DMe+s3Z475tumsU6vZcXpfgLXH tFWm6p7RYa+nRp9Mvyv748wt68Jd6do1a53LDRPiD1/Ne3g0J/bsbY9wIUebilWvnssed+zL +PZpLsdEJZbijERDLeai4kQAazIxqqQCAAA= X-CMS-MailID: 20190201164719eucas1p2091c6d41a6cc21a3d36081daf4bc8267 X-Msg-Generator: CA X-RootMTR: 20190201164719eucas1p2091c6d41a6cc21a3d36081daf4bc8267 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164719eucas1p2091c6d41a6cc21a3d36081daf4bc8267 References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch provides support for clocks needed for Dynamic Memory Controller in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and GATE entries. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 46 ++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 34cce3c..f1a4f56 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -132,6 +132,8 @@ #define BPLL_LOCK 0x20010 #define BPLL_CON0 0x20110 #define SRC_CDREX 0x20200 +#define GATE_BUS_CDREX0 0x20700 +#define GATE_BUS_CDREX1 0x20704 #define DIV_CDREX0 0x20500 #define DIV_CDREX1 0x20504 #define KPLL_LOCK 0x28000 @@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { DIV_CDREX1, SRC_KFC, DIV_KFC0, + GATE_BUS_CDREX0, + GATE_BUS_CDREX1, }; static const unsigned long exynos5800_clk_regs[] __initconst = { @@ -425,6 +429,10 @@ PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; +PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", + "mout_sclk_mpll", "ff_dout_spll2", + "mout_sclk_spll", "mout_sclk_epll"}; + /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock @@ -450,7 +458,7 @@ static const struct samsung_fixed_factor_clock static const struct samsung_fixed_factor_clock exynos5800_fixed_factor_clks[] __initconst = { FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), - FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), + FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), }; static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { @@ -472,11 +480,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), + MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", + mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), + MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", - mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), + mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), - MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), + MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), @@ -648,7 +659,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), - MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), + MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, @@ -817,6 +828,8 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", DIV_CDREX0, 3, 5), + DIV(0, "dout_pclk_drex0", "dout_cclk_drex0", DIV_CDREX0, 28, 3), + DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", DIV_CDREX1, 8, 3), @@ -1170,6 +1183,31 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), + + GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 0, 0, 0), + GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 1, 0, 0), + GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", + SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), }; static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { From patchwork Fri Feb 1 16:46:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10793311 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 61F0B13B5 for ; Fri, 1 Feb 2019 16:48:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 520E0324D3 for ; Fri, 1 Feb 2019 16:48:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 462F0324EA; Fri, 1 Feb 2019 16:48:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 62F42324D3 for ; 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Fri, 1 Feb 2019 16:47:18 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Fri, 1 Feb 2019 17:46:47 +0100 Message-Id: <1549039612-28905-4-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSaUgUYRjum9nZHa2RcTV9yaPYEDRwtQz6yCizazAqC4tQIdecPFKzHS2z yCNLE9Ol09QyxFC2wmutRcrQzCPzDq202FpCsExqV8ooq3E2+vd8z/E+Ly8fTSrvUkvo+ORU XpusSVTJ7WX3O2b7fCE9LNLf9MsJ15fUUnjUOkHhivY+ChebP5K4v79OgXtzPinw6yx33GAe ofCXwrcUHm4ul2PLhXaES/pbCHyv/Y0CDz7bgseya+T4yac8Cs+N1MuCHLnpl2cVXIP+vJxr rMrkWj8/JLgigx5xlgbPUHm4/boYPjH+GK/1Wx9lHzdlMaKUVof08sq9WahpUQGyo4FdDVND TUQBsqeVbA2C7O5hSnpYEVQVGW2KBcHT11bZv0iloV4uCdUIZoZKFaIwHxnRaQsQTctZNRj1 R0XamT0J46OPSdFPslkkGHN084Oc2F0w1pVHiFjGekFusYUUswwbAq2TAVKXJ7zqO0+K2I7d DvnmB0icA2yLAkwDE0gybYbRB+JCInaCyU6DQsLu0HOp0La0AL35epvnFOR1G22eQHjSOUiJ vSTrA7XNfhK9ERrvDBEiDawDvJxyFGnyL7x4/xop0Qzkn1NKbm8wFA4QEnaB6rtXbcM5KDM0 2e55E8HX3m5Ch5aW/i+7hZAeufJpQlIsL6xM5o+rBU2SkJYcqz54JKkB/f1DPXOdX41oZii6 DbE0Ui1i6n7siVRSmmPCiaQ2BDSpcmaCE8IilUyM5kQGrz1yQJuWyAttyI2WqVyZkwtMEUo2 VpPKH+b5FF77TyVouyVZSH8drf+9rf6K7HZCQWVmR+iswb3McxCWW8PXqN8x/p2P4LTbN2v0 DaZ6a+XqoE2YC6paXJHDfIza3+gSGTGbml17JeRM8HSA17KF7wfX/uzKHfeRu4ztPNQ9Z973 PW4Hd2HMP/qF924PX517jseqD6d2mE3KyyOBhK6PS8vY8FytkglxmpUrSK2g+QPx2eqqPwMA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42I5/e/4PV3xipAYg21tfBYbZ6xntbj+5Tmr xfwj51gt+h+/ZrY4f34Du8XZpjfsFrcaZCw2Pb7GavGx5x6rxeVdc9gsPvceYbSYcX4fk8Xa I3fZLS6ecrW43biCzeLwm3ZWi3/XNrI4CHq8v9HK7rFpVSebx+Yl9R4H3+1h8ujbsorR4/Mm uQC2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1MlfTublNSczLLUIn27BL2M t593MBYc5KuYsyi0gXErTxcjJ4eEgInEoi0b2boYuTiEBJYySlz9dosdIiEmMWnfdihbWOLP tS6ook+MEstXfWHtYuTgYBPQk9ixqhCkRkSgXqL/zSWwGmaBPmaJxuOLWUESwgK+Eo+nfWIB sVkEVCVa+j8zg/TyCnhJHHxlDDFfTuLmuU5mEJtTwFui4/F2RhBbCKhk1b8DzBMY+RYwMqxi FEktLc5Nzy020itOzC0uzUvXS87P3cQIjIxtx35u2cHY9S74EKMAB6MSD++GX0ExQqyJZcWV uYcYJTiYlUR4nbJCYoR4UxIrq1KL8uOLSnNSiw8xmgLdNJFZSjQ5Hxi1eSXxhqaG5haWhubG 5sZmFkrivOcNKqOEBNITS1KzU1MLUotg+pg4OKUaGGP/3Lmjpe785bPERu8Nsi8U5B/P+aEW 2jAhgEPS9dTM4tuR3d9ufQt6+3HWsi985q6LEv5nXLPsCWXeEr0++nSna/bHhR8LrszvlOLa 9y/wnqH+YZ1PzAdiNl31/Zt0du/SCTwxpmfXTBS5GP6mZvfMMrbXmWZXohfsXHPQaOWfwMe3 zh5qifmgxFKckWioxVxUnAgAsp6ClaICAAA= X-CMS-MailID: 20190201164719eucas1p106c8761eb4bff12a906b601a37bf58b5 X-Msg-Generator: CA X-RootMTR: 20190201164719eucas1p106c8761eb4bff12a906b601a37bf58b5 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164719eucas1p106c8761eb4bff12a906b601a37bf58b5 References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index f1a4f56..1fc5152 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1323,6 +1323,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1465,7 +1476,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), From patchwork Fri Feb 1 16:46:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10793297 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC15617E9 for ; Fri, 1 Feb 2019 16:47:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D79D8324D3 for ; Fri, 1 Feb 2019 16:47:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CBB52324EA; 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Fri, 1 Feb 2019 16:47:20 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190201164719eusmtrp216c6b171dba080394d239d603a34db3e~-S1hs_VZi0866308663eusmtrp2h; Fri, 1 Feb 2019 16:47:19 +0000 (GMT) X-AuditID: cbfec7f4-84fff700000010c6-6a-5c547819f7d1 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 04.29.04284.718745C5; Fri, 1 Feb 2019 16:47:19 +0000 (GMT) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190201164719eusmtip29327c6560fb31f61912e57f3c597729d~-S1hBI86S0078200782eusmtip2g; Fri, 1 Feb 2019 16:47:19 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/8] drivers: devfreq: add DMC driver for Exynos5422 Date: Fri, 1 Feb 2019 17:46:48 +0100 Message-Id: <1549039612-28905-5-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJKsWRmVeSWpSXmKPExsWy7djP87qSFSExBgd6lS02zljPanH9y3NW i/lHzrFa9D9+zWxx/vwGdouzTW/YLW41yFhsenyN1eLyrjlsFp97jzBazDi/j8li7ZG77Ba3 G1ewWRx+087qwOexaVUnm8fmJfUeB9/tYfLo27KK0ePzJrkA1igum5TUnMyy1CJ9uwSujGk3 PQoeX2SqmHt0J1sD44tJTF2MnBwSAiYS87e9Z+xi5OIQEljBKDFxwgsWkISQwBdGiU/P4yAS nxklzl6fxQzTcej3RyaIxHJGiZ7dLewQDlBH8+mDQFUcHGwCehI7VhWCNIgIVEvcub6fGaSG WWAyk8Si091gu4UF3CUW3H/FBlLPIqAq8e1eCEiYV8BL4t/cw6wQy+Qkbp7rBFvMKeAt0fF4 O9ipEgLL2CX2H5zOCFHkInFzwReo64QlXh3fwg5hy0j83zkf6s9iibMdq9gg7BqJ9pM7oGqs JQ4fv8gKcgOzgKbE+l36EGFHiasvnoK9IiHAJ3HjrSBImBnInLRtOlSYV6KjTQiiWkNiS88F qEViEsvXTGOHKPGQOLU3BRKc8xgl3q3XmcAoPwth1QJGxlWM4qmlxbnpqcVGeanlesWJucWl eel6yfm5mxiBCeb0v+NfdjDu+pN0iFGAg1GJh3fDr6AYIdbEsuLK3EOMEhzMSiK8TlkhMUK8 KYmVValF+fFFpTmpxYcYpTlYlMR5qxkeRAsJpCeWpGanphakFsFkmTg4pRoYI5/4/uBly62p j/u1xyTMQqU8QZ3TeoEpm/yOdZsPz3BqnxzNlbtg55qpzFImdzlyXh57dfwur8zEuzynWzeU OOu03Ezi/7L4yNXCVq6nK54Kd31UmPxvuvgOYQO5tVJPJY+fv3P5XPqCf1F7W+fzcF9O8b52 Z+HfefN2vPPcc2kfd/Mdv7WPfJVYijMSDbWYi4oTAdd1toosAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLLMWRmVeSWpSXmKPExsVy+t/xe7riFSExBu03LSw2zljPanH9y3NW i/lHzrFa9D9+zWxx/vwGdouzTW/YLW41yFhsenyN1eLyrjlsFp97jzBazDi/j8li7ZG77Ba3 G1ewWRx+087qwOexaVUnm8fmJfUeB9/tYfLo27KK0ePzJrkA1ig9m6L80pJUhYz84hJbpWhD CyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jGk3PQoeX2SqmHt0J1sD44tJTF2M nBwSAiYSh35/BLK5OIQEljJKfNx6nw0iISYxad92dghbWOLPtS6wuJDAJ0aJ5auluhg5ONgE 9CR2rCoECYsI1Ev0v7nEBjKHWWA+k0T/lLmsIAlhAXeJBfdfsYHUswioSny7FwIS5hXwkvg3 9zArxHg5iZvnOplBbE4Bb4mOx9sZIVZ5Saz6d4B5AiPfAkaGVYwiqaXFuem5xYZ6xYm5xaV5 6XrJ+bmbGIFBv+3Yz807GC9tDD7EKMDBqMTDu+FXUIwQa2JZcWXuIUYJDmYlEV6nrJAYId6U xMqq1KL8+KLSnNTiQ4ymQDdNZJYSTc4HRmReSbyhqaG5haWhubG5sZmFkjjveYPKKCGB9MSS 1OzU1ILUIpg+Jg5OqQbGgIIjBiwmmcospqcuTLpopL1t/yH1Y1OcJb8f2FPdWn92g6ikAevW nt7Go07HvjqnXIs6uPLlnhMHytdbR+VoNuytVsx1yF/V7hk8+cZppoX5Z3K5ZJmq+9s+yKl1 nLmgs9V5odB19si8uS17Z4WsPTFpqfXn6UvcnRd1Ku4XMAso09C93+msxFKckWioxVxUnAgA /e39t5ACAAA= X-CMS-MailID: 20190201164720eucas1p13aac6550399d240b261a2cbe489d3dfc X-Msg-Generator: CA X-RootMTR: 20190201164720eucas1p13aac6550399d240b261a2cbe489d3dfc X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164720eucas1p13aac6550399d240b261a2cbe489d3dfc References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. The patch also contains needed MAINTAINERS file update. Signed-off-by: Lukasz Luba --- MAINTAINERS | 7 + drivers/devfreq/Kconfig | 13 + drivers/devfreq/Makefile | 1 + drivers/devfreq/exynos5422-dmc.c | 1274 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 1295 insertions(+) create mode 100644 drivers/devfreq/exynos5422-dmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 9f64f8d..e81dfbf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3310,6 +3310,13 @@ S: Maintained F: drivers/devfreq/exynos-bus.c F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422 +M: Lukasz Luba +L: linux-pm@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/devfreq/exynos5422-dmc.c + BUSLOGIC SCSI DRIVER M: Khalid Aziz L: linux-scsi@vger.kernel.org diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 6a172d3..2a876ad 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -113,6 +113,19 @@ config ARM_RK3399_DMC_DEVFREQ It sets the frequency for the memory controller and reads the usage counts from hardware. +config ARM_EXYNOS5422_DMC_DEVFREQ + tristate "ARM EXYNOS5422 DMC DEVFREQ Driver" + depends on ARCH_EXYNOS || COMPILE_TEST + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select DEVFREQ_GOV_PASSIVE + select PM_DEVFREQ_EVENT + select PM_OPP + help + This adds DEVFREQ driver for Exynos5422 DMC (Dynamic Memory Controller). + The driver provides support for Dynamic Voltage and Frequency Scaling in + DMC and DRAM. It also supports changing timings of DRAM running with + different frequency. + source "drivers/devfreq/event/Kconfig" endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 32b8d4d..d011835 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o +obj-$(CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ) += exynos5422-dmc.o # DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff --git a/drivers/devfreq/exynos5422-dmc.c b/drivers/devfreq/exynos5422-dmc.c new file mode 100644 index 0000000..8a19281 --- /dev/null +++ b/drivers/devfreq/exynos5422-dmc.c @@ -0,0 +1,1274 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_DESC "Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change" + +#define EXYNOS5422_REV_0 (0x1) +#define EXYNOS5422_PROD_REV_MAIN_MASK (0xf0) +#define EXYNOS5422_PROD_REV_SUB_MASK (0xf) + +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034) +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8) +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC) + +#define EXYNOS5_DREXI_MEMCTRL (0x0004) +#define EXYNOS5_DREXI_DIRECTCMD (0x0010) +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGSETSW (0x00E0) +#define EXYNOS5_DREXI_MRSTATUS (0x0054) +#define EXYNOS5_DREXI_QOSCONTROL8 (0x00A0) +#define EXYNOS5_DREXI_BRBRSVCONTROL (0x0100) +#define EXYNOS5_DREXI_BP_CONTROL0 (0x0210) +#define EXYNOS5_DREXI_BP_CONTROL1 (0x0220) +#define EXYNOS5_DREXI_BP_CONTROL2 (0x0230) +#define EXYNOS5_DREXI_BP_CONTROL3 (0x0240) + +#define EXYNOS5_LPDDR3PHY_CON3 (0x0A20) +#define EXYNOS5_TIMING_SET_SWI (1UL << 28) + +#define AREF_NORMAL (0x2e) + +#define EXYNOS5_TIMING_USE_SET (1UL << 4) +#define EXYNOS5_TIMING_SET_SW_CON (1UL) + +#define EXYNOS5_CLK_MUX_STAT_CDREX (0x400) +#define EXYNOS5_MCLK_CDREX_SEL_BPLL (1UL) +#define EXYNOS5_MCLK_CDREX_SEL_MX_MSPLL (2UL) +#define EXYNOS5_CLKSRC_CDREX_SEL_SHIFT (4) +#define EXYNOS5_MCLK_CDREX_MASK (0x7) + +#define EXYNOS5_CLK_SRC_CDREX (0x200) +#define DMC_PAUSE_CTRL (0x91C) +#define DMC_PAUSE_ENABLE (1UL) +#define SELF_REFRESH_MASK (0x20UL) +#define SR_CMD_EXIT_CHIP0 (0x08000000) +#define SR_CMD_EXIT_CHIP1 (0x08100000) +#define CMD_SR_ENTER (0x04000000) +#define CMD_SR_EXIT (0x08000000) +#define CMD_CHIP0 (0x00000000) +#define CMD_CHIP1 (0x00100000) +#define USE_MX_MSPLL_TIMINGS (1) +#define USE_BPLL_TIMINGS (0) + +#define DMC_REG_VOLT_STEP 0 + +#define IS_MEM_2GB(val) \ + ( \ + (((val) & 0xf0) & 0x20) ? 1 : \ + (((val) & 0xf0) & 0x30) ? 1 : 0 \ + ) + +#define EXYNOS5_POP_OPTIONS(val) \ + (((val >> 4) & 0x3UL) << 4) +#define EXYNOS5_DDR_TYPE(val) \ + (((val >> 14) & 0x1UL)) + +#define CHIP_PROD_ID (0) +#define CHIP_PKG_ID (4) + +#define PMCNT_CONST_RATIO_MUL 15 +#define PMCNT_CONST_RATIO_DIV 10 + +/** + * enum dmc_slot_id - An enum with slots in DMC + */ +enum dmc_slot_id { + DMC0_0, + DMC0_1, + DMC1_0, + DMC1_1, + DMC_SLOTS_END +}; + +/** + * struct dmc_slot_info - Describes DMC's slot + * + * The structure holds DMC's slot name which is part of the device name + * provided in DT. Each slot has particular share of the DMC bandwidth. + * To abstract the model performance and values in performance counters, + * fields 'ratio_mul' and 'ratio_div' are used in calculation algorithm + * for each slot. Please check the corresponding function with the algorithm, + * to see how these variables are used. + */ +struct dmc_slot_info { + char *name; + int id; + int ratio_mul; + int ratio_div; +}; + +/** + * struct dmc_opp_table - Operating level desciption + * + * Covers frequency and voltage settings of the DMC operating mode. + */ +struct dmc_opp_table { + unsigned long freq_khz; + unsigned long volt_uv; +}; + +/** + * struct dram_param - Parameters for the external memory chip + * + * Covers timings settings for a particular memory chip's operating frequency. + */ +struct dram_param { + unsigned int timing_row; + unsigned int timing_data; + unsigned int timing_power; +}; + +/** + * struct exynos5_dmc - main structure describing DMC device + * + * The main structure for the Dynamic Memory Controller which covers clocks, + * memory regions, HW information, parameters and current operating mode. + */ +struct exynos5_dmc { + struct device *dev; + struct devfreq *df; + struct devfreq_simple_ondemand_data gov_data; + void __iomem *base_drexi0; + void __iomem *base_drexi1; + void __iomem *base_clk; + void __iomem *chip_id; + struct mutex lock; + unsigned long curr_rate; + unsigned long curr_volt; + const struct dmc_opp_table *opp; + const struct dmc_opp_table *opp_bypass; + int opp_count; + const struct dram_param *dram_param; + const struct dram_param *dram_bypass_param; + int dram_param_count; + unsigned int prod_rev; + unsigned int pkg_rev; + unsigned int mem_info; + struct regulator *vdd_mif; + struct clk *fout_spll; + struct clk *fout_bpll; + struct clk *mout_spll; + struct clk *mout_bpll; + struct clk *mout_mclk_cdrex; + struct clk *dout_clk2x_phy0; + struct clk *mout_mx_mspll_ccore; + struct clk *mx_mspll_ccore_phy; + struct clk *mout_mx_mspll_ccore_phy; + struct devfreq_event_dev **counter; + int num_counters; + bool counters_enabled; +}; + +/** + * exynos5_counters_fname() - Macro generating function for event devices + * @f: function name suffix + * + * Macro which generates needed function for manipulation of event devices. + * It aims to avoid code duplication relaying on similar prefix and function + * parameters in the devfreq event device framework functions. + */ +#define exynos5_counters_fname(f) \ +static int exynos5_counters_##f(struct exynos5_dmc *dmc) \ +{ \ + int i, ret; \ + \ + for (i = 0; i < dmc->num_counters; i++) { \ + if (!dmc->counter[i]) \ + continue; \ + ret = devfreq_event_##f(dmc->counter[i]); \ + if (ret < 0) \ + return ret; \ + } \ + return 0; \ +} +exynos5_counters_fname(set_event); +exynos5_counters_fname(enable_edev); +exynos5_counters_fname(disable_edev); + +/** + * dmc_opp_exynos5422 - Array with frequency and voltage values + * + * Operating points for Exynos5422 SoC revisions. + * The order and sizeof the array has a meaning and is tightly connected with + * DRAM parameters in arrays bellow. + */ +static const struct dmc_opp_table dmc_opp_exynos5422[] = { + {825000, 1050000}, + {728000, 1037500}, + {633000, 1012500}, + {543000, 937500}, + {413000, 887500}, + {275000, 875000}, + {206000, 875000}, + {165000, 875000}, +}; + +/** + * dmc_opp_bypass_exynos5422 - frequency and voltage level for temporary mode + */ +static const struct dmc_opp_table dmc_opp_bypass_exynos5422 = {400000, 887500}; + +/** + * dram_param_exynos5422 - DRAM timings for particular HW setup + * + * Operating parameters for DRAM memory running with different clock frequency. + * The order is the same as in 'dmc_opp_table' above, the highest frequency + * is first. + * These settings are needed for proper operation of the DRAM memory with + * corresponding frequency. They are calculated for Exynos5422 revision 0 + * with 2GB LPDDR3 memory chip. + */ +static const struct dram_param dram_param_exynos5422[] = { + {0x365A9713, 0x4740085E, 0x543A0446}, + {0x30598651, 0x3730085E, 0x4C330336}, + {0x2A48758F, 0x3730085E, 0x402D0335}, + {0x244764CD, 0x3730085E, 0x38270335}, + {0x1B35538A, 0x2720085E, 0x2C1D0225}, + {0x12244287, 0x2720085E, 0x1C140225}, + {0x112331C6, 0x2720085E, 0x180F0225}, + {0x11223185, 0x2720085E, 0x140C0225}, +}; + + +/** + * Operating parameters for DRAM memory running on temporary clock 400MHz during + * switching frequency on the main clock. This variable provides timings for + * Exynos5422 SoC revision 0 and DRAM 2GB chip. + */ +static const struct dram_param dram_bypass_param_exynos5422 = { + 0x365a9713, 0x4740085e, 0x543a0446 +}; + +/** + * dmc_slot - An array which holds DMC's slots information + * + * The array is used in algorithm calculating slots performance and usage + * based on performance counters' values. The values i.e. 15/10=1.5 correspond + * to slot share in the DMC channel, which has 2.0 abstract width. + */ +static const struct dmc_slot_info dmc_slot[] = { + {"dmc0_0", DMC0_0, 15, 10}, + {"dmc0_1", DMC0_1, 5, 10}, + {"dmc1_0", DMC1_0, 10, 10}, + {"dmc1_1", DMC1_0, 10, 10}, +}; + +/** + * find_target_freq_id() - Finds requested frequency in local DMC configuration + * @dmc: device for which the information is checked + * @target_rate: requested frequency in KHz + * + * Seeks in the local DMC driver structure for the requested frequency value + * and returns index or error value. + */ +static int find_target_freq_idx(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int i; + + for (i = 0; i < dmc->opp_count; i++) + if (dmc->opp[i].freq_khz <= target_rate) + return i; + + return -EINVAL; +} + +/** + * exynos5_get_chip_info() - Gets chip ID information + * @dmc: device for which the information is checked + * + * Function wrapper for getting the chip ID information. + */ +static void exynos5_get_chip_info(struct exynos5_dmc *dmc) +{ + unsigned int val; + + val = readl(dmc->chip_id + CHIP_PROD_ID); + dmc->prod_rev = val; + + val = readl(dmc->chip_id + CHIP_PKG_ID); + dmc->pkg_rev = val; + + dmc->mem_info = EXYNOS5_POP_OPTIONS(val); + dmc->mem_info |= EXYNOS5_DDR_TYPE(val); +} + +/** + * exynos5_dmc_pause_on_switching() - Controls a pause feature in DMC + * @dmc: device which is used for changing this feature + * @set: a boolean state passing enable/disable request + * + * There is a need of pausing DREX DMC when divider or MUX in clock tree + * changes its configuration. In such situation access to the memory is blocked + * in DMC automatically. This feature is used when clock frequency change + * request appears and touches clock tree. + */ +static int exynos5_dmc_pause_on_switching(struct exynos5_dmc *dmc, bool set) +{ + unsigned int val; + + val = readl(dmc->base_clk + DMC_PAUSE_CTRL); + if (set) + val |= DMC_PAUSE_ENABLE; + else + val &= ~DMC_PAUSE_ENABLE; + writel(val, dmc->base_clk + DMC_PAUSE_CTRL); + + return 0; +} + +/** + * exynos5_dmc_chip_revision_settings() - Chooses proper DMC's configuration + * @dmc: device for which is going to be checked and configured + * + * Function checks the HW product information in order to choose proper + * configuration for DMC frequency, voltage and DRAM timings. + */ +static int exynos5_dmc_chip_revision_settings(struct exynos5_dmc *dmc) +{ + exynos5_get_chip_info(dmc); + + if (!IS_MEM_2GB(dmc->mem_info)) { + dev_warn(dmc->dev, "DRAM memory type not supported\n"); + return -EINVAL; + } + + dmc->dram_param = dram_param_exynos5422; + + dmc->dram_param_count = ARRAY_SIZE(dram_param_exynos5422); + + dmc->dram_bypass_param = &dram_bypass_param_exynos5422; + + dmc->opp = dmc_opp_exynos5422; + dmc->opp_count = ARRAY_SIZE(dmc_opp_exynos5422); + + dmc->opp_bypass = &dmc_opp_bypass_exynos5422; + + return 0; +} + +/** + * exynos5_init_freq_table() - Initialized PM OPP framework + * @dev: devfreq device for which the OPP table is going to be + * initialized + * @dmc: DMC device for which the frequencies are used for OPP init + * @profile: devfreq device's profile + * + * Populate the devfreq device's OPP table based on current frequency, voltage. + */ +static int exynos5_init_freq_table(struct device *dev, struct exynos5_dmc *dmc, + struct devfreq_dev_profile *profile) +{ + int i, ret; + + for (i = 0; i < dmc->opp_count; i++) { + ret = dev_pm_opp_add(dev, dmc->opp[i].freq_khz, + dmc->opp[i].volt_uv); + if (ret) { + dev_warn(dev, "failed to add opp %uHz %umV\n", 1, 1); + while (i-- > 0) + dev_pm_opp_remove(dev, dmc->opp[i].freq_khz); + return ret; + } + } + + return 0; +} + +/** + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings + * @dmc: device for which the new settings is going to be applied + * @param: DRAM parameters which passes timing data + * + * Low-level function for changing timings for DRAM memory clocking from + * 'bypass' clock source (fixed frequency @400MHz). + * It uses timing bank registers set 1. + */ +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc, + const struct dram_param *param) +{ + + writel(AREF_NORMAL, dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(param->timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); + writel(param->timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); + writel(param->timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); + writel(param->timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); + writel(param->timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); + writel(param->timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); +} + + +/** + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings + * @dmc: device for which the new settings is going to be applied + * @target_rate: target frequency of the DMC + * + * Low-level function for changing timings for DRAM memory operating from main + * clock source (BPLL), which can have different frequencies. Thus, each + * frequency must have corresponding timings register values in order to keep + * the needed delays. + * It uses timing bank registers set 0. + */ +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx; + + + for (idx = 0; idx < dmc->dram_param_count; idx++) + if (dmc->opp[idx].freq_khz <= target_rate) + break; + + if (idx >= dmc->dram_param_count) + return -EINVAL; + + writel(AREF_NORMAL, dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->dram_param[idx].timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->dram_param[idx].timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->dram_param[idx].timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->dram_param[idx].timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->dram_param[idx].timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); + writel(dmc->dram_param[idx].timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); + + return 0; +} + +/** + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings + * @dmc: device for which the new settings is going to be applied + * @set: boolean variable passing set value + * + * Changes the register set, which holds timing parameters. + * There is two register sets: 0 and 1. The register set 0 + * is used in normal operation when the clock is provided from main PLL. + * The bank register set 1 is used when the main PLL frequency is going to be + * changed and the clock is taken from alternative, stable source. + * This function switches between these banks according to the + * currently used clock source. + */ +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) +{ + unsigned int reg; + + reg = readl(dmc->base_clk + EXYNOS5_LPDDR3PHY_CON3); + + if (set) + reg |= EXYNOS5_TIMING_SET_SWI; + else + reg &= ~EXYNOS5_TIMING_SET_SWI; + + writel(reg, dmc->base_clk + EXYNOS5_LPDDR3PHY_CON3); +} + +/* + * Change clock parent for MUX_CORE_SEL and the main clock for DMC. + * The mux takes two clock sources: main BPLL and mx_mspll ('bypass'). + */ +static int exynos5_dmc_change_clock_parent(struct exynos5_dmc *dmc, + struct clk *parent, + unsigned int parent_selection_id) +{ + unsigned int reg = 0; + + reg = readl(dmc->base_clk + EXYNOS5_CLK_SRC_CDREX); + if (clk_set_parent(dmc->mout_mclk_cdrex, parent)) { + dev_err(dmc->dev, "Couldn't change parent of mclk_cdrex\n"); + return -EINVAL; + } + + for ( ; reg != parent_selection_id; ) { + cpu_relax(); + reg = readl(dmc->base_clk + EXYNOS5_CLK_MUX_STAT_CDREX); + reg >>= EXYNOS5_CLKSRC_CDREX_SEL_SHIFT; + reg &= EXYNOS5_MCLK_CDREX_MASK; + } + + return 0; +} + + +/** + * exynos5_dmc_change_voltage() - Changes the voltage regulator value + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Main function for changing voltage on the VDD_MIF regulator. + */ +static int exynos5_dmc_change_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt + DMC_REG_VOLT_STEP); + + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + return 0; +} + +/** + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for 'normal' mode. + * It checks the need of higher voltage and changes the value. The target + * voltage might be lower that currently set and still the system will be + * stable. + */ +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + + if (dmc->curr_volt > target_volt) + ret = exynos5_dmc_change_voltage(dmc, target_volt); + + return ret; +} + +/** + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for the 'bypass' mode. + * It checks the need of higher voltage and changes the value. + * The target voltage must not be less than currently needed, because + * for current frequency the device might become unstable. + */ +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + unsigned long bypass_volt = dmc->opp_bypass->volt_uv; + + target_volt = max(bypass_volt, target_volt); + + if (dmc->curr_volt >= target_volt) + return 0; + + ret = exynos5_dmc_change_voltage(dmc, target_volt); + + return ret; +} + +/** + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings + * @dmc: device for which it is going to be set + * @target_rate: new frequency which is chosen to be final + * + * Function changes the DRAM timings for the temporary 'bypass' mode. + */ +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx = find_target_freq_idx(dmc, target_rate); + + if (idx < 0) + return -EINVAL; + + exynos5_set_bypass_dram_timings(dmc, dmc->dram_bypass_param); + + return 0; +} + +/** + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock + * @dmc: DMC device for which the switching is going to happen + * @target_rate: new frequency which is going to be set as a final + * @target_volt: new voltage which is going to be set as a final + * + * Function configures DMC and clocks for operating in temporary 'bypass' mode. + * This mode is used only temporary but if required, changes voltage and timings + * for DRAM chips. It switches the main clock to stable clock source for the + * period of the main PLL reconfiguration. + */ +static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + /* + * Having higher voltage for a particular frequency does not harm + * the chip. Use it for the temporary frequency change when one + * voltage manipulation might be avoided. + */ + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt); + if (ret) + return ret; + + /* + * Longer delays for DRAM does not cause crash, the opposite does. + */ + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); + if (ret) + return ret; + + /* + * Delays are long enough, so use them for the new coming clock. + */ + exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS); + + /* + * Voltage is set at least to a level needed for this frequency, + * so switching clock source is safe now. + */ + clk_prepare_enable(dmc->fout_spll); + clk_prepare_enable(dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + ret = exynos5_dmc_change_clock_parent(dmc, dmc->mout_mx_mspll_ccore, + EXYNOS5_MCLK_CDREX_SEL_MX_MSPLL); + return ret; +} + +/** + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC + * using safe procedure + * @dmc: device for which the frequency is going to be changed + * @target_rate: requested new frequency + * @target_volt: requested voltage which corresponds to the new frequency + * + * The DMC frequency change procedure requires a few steps. + * The main requirement is to change the clock source in the clk mux + * for the time of main clock PLL locking. The assumption is that the + * alternative clock source set as parent is stable. + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass' + * clock. This requires alignment in DRAM timing parameters for the new + * T-period. There is two bank sets for keeping DRAM + * timings: set 0 and set 1. The set 0 is used when main clock source is + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between + * the two bank sets is part of the process. + * The voltage must also be aligned to the minimum required level. There is + * this intermediate step with switching to 'bypass' parent clock source. + * if the old voltage is lower, it requires an increase of the voltage level. + * The complexity of the voltage manipulation is hidden in low level function. + * In this function there is last alignment of the voltage level at the end. + */ +static int +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, + target_volt); + if (ret) + return ret; + + /* We are safe to increase the timings for current bypass frequency. + * Thanks to this the settings we be ready for the upcoming clock source + * change. + */ + exynos5_dram_change_timings(dmc, target_rate); + + clk_set_rate(dmc->fout_bpll, target_rate * 1000); + + exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS); + + ret = exynos5_dmc_change_clock_parent(dmc, dmc->mout_bpll, + EXYNOS5_MCLK_CDREX_SEL_BPLL); + if (ret) + return ret; + + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + clk_disable_unprepare(dmc->fout_spll); + /* Make sure if the voltage is not from 'bypass' settings and align to + * the right level for power efficiency. + */ + ret = exynos5_dmc_align_target_voltage(dmc, target_volt); + + return ret; +} + +/** + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP + * table. + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @target_rate: returned frequency which is the same or lower than + * requested + * @target_volt: returned voltage which corresponds to the returned + * frequency + * + * Function gets requested frequency and checks OPP framework for needed + * frequency and voltage. It populates the values 'target_rate' and + * 'target_volt' or returns error value when OPP framework fails. + */ +static int exynos5_dmc_get_volt_freq(struct device *dev, unsigned long *freq, + unsigned long *target_rate, + unsigned long *target_volt, u32 flags) +{ + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + *target_rate = dev_pm_opp_get_freq(opp); + *target_volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + return 0; +} + +/** + * exynos5_dmc_target() - Function responsible for changing frequency of DMC + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @flags: flags provided for this frequency change request + * + * An entry function provided to the devfreq framework which provides frequency + * change of the DMC. The function gets the possible rate from OPP table based + * on requested frequency. It calls the next function responsible for the + * frequency and voltage change. In case of failure, does not set 'curr_rate' + * and returns error value to the framework. + */ +static int exynos5_dmc_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long target_rate = 0; + unsigned long target_volt = 0; + int ret; + + ret = exynos5_dmc_get_volt_freq(dev, freq, &target_rate, &target_volt, + flags); + if (ret) + return ret; + + if (target_rate == dmc->curr_rate) + return 0; + + mutex_lock(&dmc->lock); + + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); + + if (ret) { + mutex_unlock(&dmc->lock); + return ret; + } + + dmc->curr_rate = target_rate; + + mutex_unlock(&dmc->lock); + return 0; +} + +/** + * exynos5_cnt_name_match() - Tries to match 'edev' with the right device index + * @edev: event device for which the name is going to be matched + * + * Function matches the name of the 'edev' counter device with known devices + * with configured ratios and shares of the DMC channels. + * When the name is matched, it returns the index for the proper device. + */ +static int exynos5_cnt_name_match(struct devfreq_event_dev *edev) +{ + int i; + int id = -ENODEV; + + for (i = 0; i < ARRAY_SIZE(dmc_slot); i++) { + if (strstr(edev->desc->name, dmc_slot[i].name)) + return i; + } + + return id; +} + +/** + * exynos5_cnt_calculate() - Calculates the values of performance counters. + * @edev: event device for which the counter is used for calculation + * @cnt: raw counter value + * @cnt_norm: counter value normalized to DMC performance ratio for a proper + * channel or virtual channel + * + * Function calculates normalized value for the raw counter. The raw counter + * value does not show real channel usage. The DMC splits not equally the + * bandwidth for the channels. The function checks the type of the 'edev' + * counter and calculates the normalized value based on the 'shares' of the + * bandwidth set in the controller. + */ +static int exynos5_cnt_calculate(struct devfreq_event_dev *edev, + unsigned long cnt, u64 *cnt_norm) +{ + int idx; + + idx = exynos5_cnt_name_match(edev); + if (idx < 0) + return idx; + + *cnt_norm = cnt; + + if (!(dmc_slot[idx].ratio_mul == dmc_slot[idx].ratio_div)) { + *cnt_norm = *cnt_norm * dmc_slot[idx].ratio_mul; + *cnt_norm = div_u64(*cnt_norm, dmc_slot[idx].ratio_div); + } + + *cnt_norm = *cnt_norm * PMCNT_CONST_RATIO_MUL; + *cnt_norm = div_u64(*cnt_norm, PMCNT_CONST_RATIO_DIV); + + return idx; +} + +/** + * exynos5_counters_get() - Gets the performance counters values. + * @dmc: device for which the counters are going to be checked + * @load_count: variable which is populated with counter value + * @total_count: variable which is used as 'wall clock' reference + * + * Function which provides performance counters values. It sums up counters for + * two DMC channels. The 'total_count' is used as a reference and max value. + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%]. + */ +static int exynos5_counters_get(struct exynos5_dmc *dmc, + unsigned long *load_count, + unsigned long *total_count) +{ + unsigned long load_dmc[2] = {0, 0}; + unsigned long total = 0; + u64 load = 0; + struct devfreq_event_data event; + int ret, i, idx; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + + ret = devfreq_event_get_event(dmc->counter[i], &event); + if (ret < 0) + return ret; + + idx = exynos5_cnt_calculate(dmc->counter[i], event.load_count, + &load); + if (idx < 0) + continue; + + if (idx == DMC0_0 || idx == DMC0_1) + load_dmc[0] += load; + else + load_dmc[1] += load; + + if (total < event.total_count) + total = event.total_count; + } + + *load_count = load_dmc[0] + load_dmc[1]; + *total_count = total; + + return 0; +} + +/** + * exynos5_dmc_get_status() - Read current DMC performance statistics. + * @dev: device for which the statistics are requested + * @stat: structure which has statistic fields + * + * Function reads the DMC performance counters and calculates 'busy_time' + * and 'total_time'. To protect from overflow, the values are shifted right + * by 10. After read out the counters are setup to count again. + */ +static int exynos5_dmc_get_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long load, total; + int ret; + bool cnt_en; + + mutex_lock(&dmc->lock); + cnt_en = dmc->counters_enabled; + mutex_unlock(&dmc->lock); + if (!cnt_en) { + dev_warn(dev, "performance counters needed, but not present\n"); + return -EAGAIN; + } + + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; + + /* To protect from overflow in calculation ratios, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency + * @dev: device for which the framework checks operating frequency + * @freq: returned frequency value + * + * It returns the currently used frequency of the DMC. The real operating + * frequency might be lower when the clock source value could not be divided + * to the requested value. + */ +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + + mutex_lock(&dmc->lock); + *freq = dmc->curr_rate; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_df_profile - Devfreq governor's profile structure + * + * It provides to the devfreq framework needed functions and polling period. + */ +static struct devfreq_dev_profile exynos5_dmc_df_profile = { + .polling_ms = 500, + .target = exynos5_dmc_target, + .get_dev_status = exynos5_dmc_get_status, + .get_cur_freq = exynos5_dmc_get_cur_freq, +}; + +/** + * exynos5_dmc_align_initial_frequency() - Align initial frequency value + * @dmc: device for which the frequency is going to be set + * @bootloader_init_freq: initial frequency set by the bootloader in KHz + * + * The initial bootloader frequency, which is present during boot, might be + * different that supported frequency values in the driver. It is possible + * due to different PLL settings or used PLL as a source. + * This function provides the 'initial_freq' for the devfreq framework + * statistics engine which supports only registered values. Thus, some alignment + * must be made. + */ +unsigned long +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, + unsigned long bootloader_init_freq) +{ + unsigned long aligned_freq; + int idx; + + idx = find_target_freq_idx(dmc, bootloader_init_freq); + if (idx >= 0) + aligned_freq = dmc->opp[idx].freq_khz; + else + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_khz; + + return aligned_freq; +} + +/** + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation. + * @dev: device for which the clocks are setup + * @dmc: DMC structure containing needed fields + * + * Get the needed clocks defined in DT device, enable and set the right parents. + * Read current frequency and initialize the initial rate for governor. + */ +static int exynos5_dmc_init_clks(struct device *dev, struct exynos5_dmc *dmc) +{ + int ret; + unsigned long target_volt = 0; + unsigned long target_rate = 0; + + dmc->fout_spll = devm_clk_get(dev, "fout_spll"); + if (IS_ERR(dmc->fout_spll)) + return PTR_ERR(dmc->fout_spll); + + dmc->fout_bpll = devm_clk_get(dev, "fout_bpll"); + if (IS_ERR(dmc->fout_bpll)) + return PTR_ERR(dmc->fout_bpll); + + dmc->mout_mclk_cdrex = devm_clk_get(dev, "mout_mclk_cdrex"); + if (IS_ERR(dmc->mout_mclk_cdrex)) + return PTR_ERR(dmc->mout_mclk_cdrex); + + dmc->mout_bpll = devm_clk_get(dev, "mout_bpll"); + if (IS_ERR(dmc->mout_bpll)) + return PTR_ERR(dmc->mout_bpll); + + dmc->mout_mx_mspll_ccore = devm_clk_get(dev, "mout_mx_mspll_ccore"); + if (IS_ERR(dmc->mout_mx_mspll_ccore)) + return PTR_ERR(dmc->mout_mx_mspll_ccore); + + dmc->dout_clk2x_phy0 = devm_clk_get(dev, "dout_clk2x_phy0"); + if (IS_ERR(dmc->dout_clk2x_phy0)) + return PTR_ERR(dmc->dout_clk2x_phy0); + + dmc->mout_spll = devm_clk_get(dev, "ff_dout_spll2"); + if (IS_ERR(dmc->mout_spll)) + return PTR_ERR(dmc->mout_spll); + + /* + * Convert frequency to KHz values and set it for the governor. + */ + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex) / 1000; + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; + + ret = exynos5_dmc_get_volt_freq(dev, &dmc->curr_rate, &target_rate, + &target_volt, 0); + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + clk_prepare_enable(dmc->mout_spll); + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + clk_prepare_enable(dmc->fout_bpll); + clk_prepare_enable(dmc->mout_bpll); + + return 0; +} + +/** + * exynos5_performance_counters_init() - Initializes performance DMC's counters + * @dmc: DMC for which it does the setup + * + * Initialization of performance counters in DMC for estimating usage. + * The counter's values are used for calculation of a memory bandwidth and based + * on that the governor changes the frequency. + * The counters are not used when the governor is GOVERNOR_USERSPACE. + */ +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) +{ + int counters_size; + int ret, i; + + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev); + if (dmc->num_counters < 0) { + dev_err(dmc->dev, "could not get devfreq-event counters\n"); + return dmc->num_counters; + } + + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + if (!dmc->counter) + return -ENOMEM; + + for (i = 0; i < dmc->num_counters; i++) { + dmc->counter[i] = + devfreq_event_get_edev_by_phandle(dmc->dev, i); + if (IS_ERR_OR_NULL(dmc->counter[i])) + return -EPROBE_DEFER; + } + + ret = exynos5_counters_enable_edev(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not enable event counter\n"); + return ret; + } + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "counld not set event counter\n"); + return ret; + } + + mutex_lock(&dmc->lock); + dmc->counters_enabled = true; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_probe() - Probe function for the DMC driver + * @pdev: platform device for which the driver is going to be initialized + * + * Initialize basic components: clocks, regulators, performance counters, etc. + * Read out product version and based on the information setup + * internal structures for the controller (frequency and voltage) and for DRAM + * memory parameters: timings for each operating frequency. + * Register new devfreq device for controlling DVFS of the DMC. + */ +static int exynos5_dmc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct exynos5_dmc *dmc; + struct device *dev = &pdev->dev; + struct resource *res; + + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); + if (!dmc) + return -ENOMEM; + + mutex_init(&dmc->lock); + + dmc->dev = dev; + platform_set_drvdata(pdev, dmc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc->base_drexi0 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi0)) + return PTR_ERR(dmc->base_drexi0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dmc->base_drexi1 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi1)) + return PTR_ERR(dmc->base_drexi1); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + dmc->base_clk = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_clk)) + return PTR_ERR(dmc->base_clk); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 3); + dmc->chip_id = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->chip_id)) + return PTR_ERR(dmc->chip_id); + + ret = exynos5_dmc_chip_revision_settings(dmc); + if (ret) + return ret; + + ret = exynos5_init_freq_table(dev, dmc, &exynos5_dmc_df_profile); + if (ret) + return ret; + + dmc->vdd_mif = devm_regulator_get(dev, "vdd_mif"); + if (IS_ERR(dmc->vdd_mif)) { + ret = PTR_ERR(dmc->vdd_mif); + dev_warn(dev, "couldn't get regulator\n"); + goto remove_opp_table; + } + + ret = exynos5_dmc_init_clks(dev, dmc); + if (ret) { + dev_warn(dev, "couldn't initialize clocks\n"); + goto remove_opp_table; + } + + ret = exynos5_dmc_pause_on_switching(dmc, 1); + if (ret) { + dev_warn(dev, "couldn't setup pause on switching\n"); + goto remove_clocks; + } + + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, + DEVFREQ_GOV_USERSPACE, + &dmc->gov_data); + + if (IS_ERR(dmc->df)) { + ret = PTR_ERR(dmc->df); + goto err_devfreq_add; + } + + dev_info(&pdev->dev, "DMC init for prod_id=0x%08x pkg_id=0x%08x\n", + dmc->prod_rev, dmc->pkg_rev); + + return 0; + +err_devfreq_add: + exynos5_counters_disable_edev(dmc); +remove_clocks: + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); +remove_opp_table: + while (dmc->opp_count-- > 0) + dev_pm_opp_remove(dev, dmc->opp[dmc->opp_count].freq_khz); + + return ret; +} + +/** + * exynos5_dmc_remove() - Remove function for the platform device + * @pdev: platform device which is going to be removed + * + * The function relies on 'devm' framework function which automatically + * clean the device's resources. It just calls explicitly disable function for + * the performance counters. + */ +static int exynos5_dmc_remove(struct platform_device *pdev) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); + + exynos5_counters_disable_edev(dmc); + + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + + dev_pm_opp_remove_table(&pdev->dev); + + dev_info(&pdev->dev, "DMC removed\n"); + + return 0; +} + +static const struct of_device_id exynos5_dmc_of_match[] = { + { .compatible = "samsung,exynos5422-dmc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match); + +static struct platform_driver exynos5_dmc_platdrv = { + .probe = exynos5_dmc_probe, + .remove = exynos5_dmc_remove, + .driver = { + .name = "exynos5-dmc", + .of_match_table = exynos5_dmc_of_match, + }, +}; +module_platform_driver(exynos5_dmc_platdrv); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Samsung"); From patchwork Fri Feb 1 16:46:49 2019 Content-Type: text/plain; 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Fri, 1 Feb 2019 16:47:19 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description Date: Fri, 1 Feb 2019 17:46:49 +0100 Message-Id: <1549039612-28905-6-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrFKsWRmVeSWpSXmKPExsWy7djPc7qSFSExBrMny1psnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLHY9Pgaq8XlXXPYLD73HmG0mHF+H5PF2iN32S2W Xr/IZHG7cQWbReveI+wWh9+0szoIeKyZt4bRY9OqTjaPzUvqPQ6+28Pk0bdlFaPH501yAWxR XDYpqTmZZalF+nYJXBnP7xxhLdimVHGj6zhjA+MD6S5GTg4JAROJnh0X2LsYuTiEBFYwSmz+ MgPK+cIo8efudTYI5zOjxITDZ5hhWk5P2MYMkVjOKHGz+xELXMvNE8cYuxg5ONgE9CR2rCoE aRARqJa4c30/WAOzwB0mib0zl7KAJIQFQiUebO8Gs1kEVCXa30xkB+nlFfCSeHdeFmKZnMTN c51gizkFvCU6Hm9nBJkjIbCNXeLjrT9MEEUuEi+mfIC6Tlji1fEt7BC2jMTpyT0sEHaxxNmO VWwQdo1E+8kdUDXWEoePX2QF2cssoCmxfpc+RNhRYtezTrBXJAT4JG68FQQJMwOZk7ZNZ4YI 80p0tAlBVGtIbOm5AHWMmMTyNdOghntIdF/sZYWEzjxGiYlPnzJPYJSfhbBsASPjKkbx1NLi 3PTUYuO81HK94sTc4tK8dL3k/NxNjMAUdPrf8a87GPf9STrEKMDBqMTDu+FXUIwQa2JZcWXu IUYJDmYlEV6nrJAYId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rzVDA+ihQTSE0tSs1NTC1KLYLJM HJxSDYwF27/NPrvt1JMbVzWNrhZnNB2Lmnp3qZttmvayb4m2rdL1OfNXq7QtCd100sbR219a yLyrVThTVeNBa/8RvXUs9m+iO3YWSTivjj7KmfMvroOZ78uWxb9LLgolNku9W8S9vuq2e8ay n+1r2fPvb5DZpJvq+bjwyGKhu/mXWu6ZJZvMX7bLa7MSS3FGoqEWc1FxIgCATCaiPQMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42I5/e/4PV2JipAYg4PftCw2zljPanH9y3NW i/lHzrFa9D9+zWxx/vwGdouzTW/YLW41yFhsenyN1eLyrjlsFp97jzBazDi/j8li7ZG77BZL r19ksrjduILNonXvEXaLw2/aWR0EPNbMW8PosWlVJ5vH5iX1Hgff7WHy6NuyitHj8ya5ALYo PZui/NKSVIWM/OISW6VoQwsjPUNLCz0jE0s9Q2PzWCsjUyV9O5uU1JzMstQifbsEvYznd46w FmxTqrjRdZyxgfGBdBcjJ4eEgInE6QnbmLsYuTiEBJYySixe/5odIiEmMWnfdihbWOLPtS42 iKJPjBKP+6cDdXBwsAnoSexYVQhSIyJQL9H/5hIbiM0s8IpJouG9BogtLBAs8fPzBlYQm0VA VaL9zUR2kFZeAS+Jd+dlIcbLSdw818kMYnMKeEt0PN7OCGILAZWs+neAeQIj3wJGhlWMIqml xbnpucVGesWJucWleel6yfm5mxiBEbHt2M8tOxi73gUfYhTgYFTi4d3wKyhGiDWxrLgy9xCj BAezkgivU1ZIjBBvSmJlVWpRfnxRaU5q8SFGU6CbJjJLiSbnA6M1ryTe0NTQ3MLS0NzY3NjM Qkmc97xBZZSQQHpiSWp2ampBahFMHxMHp1QDo9HaxrvH7SWZXoVt1dfelpSTHmw4wfmVfIni 3fSCXuuuoilBru9vX2qe/oO9kfPe17+yBQ5xJj1Xc5Iz/1hwp7AfnLhT9cu0/n0sny4cn5jj Ynfj+QnvkkeiqfOK76Z9ZNg0T1m5fDO3nEix6ZuvDZ1Ti6WnyliJhxcECQhrXb60Zrlp0cYJ SizFGYmGWsxFxYkAdUUcK54CAAA= X-CMS-MailID: 20190201164720eucas1p1ae770f7981fa09016b69ca7265e820c7 X-Msg-Generator: CA X-RootMTR: 20190201164720eucas1p1ae770f7981fa09016b69ca7265e820c7 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164720eucas1p1ae770f7981fa09016b69ca7265e820c7 References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. It also contains needed MAINTAINERS file update. Signed-off-by: Lukasz Luba --- .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 106 +++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt new file mode 100644 index 0000000..229efba --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt @@ -0,0 +1,106 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-bus". +- clock-names : the name of clock used by the bus, "bus". +- clocks : phandles for clock specified in "clock-names" property. +- devfreq-events : phandles for PPMU devices connected to this DMC. + +The example definition of a DMC and PPMU devices declared in DT is shown below: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>, + <0x10030000 0x1000>, <0x10000000 0x1000>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_DOUT_CLK2X_PHY0>, + <&clock CLK_CLKM_PHY0>, + <&clock CLK_CLKM_PHY1>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + "dout_clk2x_phy0", + "clkm_phy0", + "clkm_phy1"; + + status = "okay"; + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>, + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>; + }; + + diff --git a/MAINTAINERS b/MAINTAINERS index e81dfbf..ab0d8a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3316,6 +3316,7 @@ L: linux-pm@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Maintained F: drivers/devfreq/exynos5422-dmc.c +F: Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt BUSLOGIC SCSI DRIVER M: Khalid Aziz From patchwork Fri Feb 1 16:46:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10793313 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0715E6C2 for ; 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Fri, 1 Feb 2019 16:47:20 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 6/8] DT: arm: exynos: add DMC device for exynos5422 Date: Fri, 1 Feb 2019 17:46:50 +0100 Message-Id: <1549039612-28905-7-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WSe0hTcRTH++3uPnxMrtP0ZGawHmSQVkbdSKIsahipiFGYUVMv03I+dn1m kAXmA18olJpohDK9OFxr+FhpNSURcyaGmg8SJDOb/ZEzSrNy3ln/fc73nO/5nj8OhUmbcC8q PjGVVScqEmSEo7j19c/BfV6ZEVH7eSvJPKlswZlR6yecqesx40zpzBeMGRzUkczAXQvJjOd4 M/qZEZwZNtYQzGJxD2IqB7tEjLZnimQaRodEzMSdRoLJ7ewhmW5LHn6CljfXNiO5ni8g5E/r b8tffX0ukpcYeCRf1PuEEZGOgbFsQnw6q/Y/fs0xbrpJiyf/2JY5sVRG5KAVj0LkQAF9CPKM WrIQOVJSuhGBRlcgEgorgpbeAlwoFhHMzprRhmW5eJUQGhoEHavvsH8W6zPrWkFRBO0H7XyK zeBOZ8Pk6Iv1GYyeFEFnVYPY1nCjz8B4rQW3sZjeBS3Dn9cTJHQwrJR9EAtpPvDeXIDZ2IE+ B/kzbfYrjCSslIYKfBqWzTwpsBvM9xrs7A39FUX2PRwM5POEwLcgr6/dPnMMunuHcNvNGO0L LUZ/QT4Jc1Uz6zLQLjC24GqTsTUsb32ACbIE8u9Jhek9YCh6KxLYAzTN9+3L5fCt2ryuS+la BG26wDK0vfp/1iOEeOTJpnEqJcsFJLIZfpxCxaUlKv1iklR6tPZA/b97l9pR169oE6IpJHOW 6JbDo6S4Ip3LUpkQUJjMXRJ0PSJKKolVZN1k1UlX1WkJLGdCWymxzFOSvWn6spRWKlLZGyyb zKo3uiLKwSsHdedOhLiFLNU3jO28uBhOZhp0mYXpFqiIPKg96qzMCODSCssjiZQE3vXs49Wa S1rt4VN6gyLdpFwo6dTsVl8YHzli+bgFy5A+fFla/yfU1xgNGJp3cqnIrsrP0pjeeHpq52O6 5r7Hbg7i63aEOlmCXc9H9l3p8K3pnpBNhTnJxFyc4sBeTM0p/gJLc3pbPAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42I5/e/4PV3JipAYg3+nxCw2zljPanH9y3NW i/lHzrFa9D9+zWxx/vwGdouzTW/YLW41yFhsenyN1eLyrjlsFp97jzBazDi/j8li7ZG77BZL r19ksrjduILNonXvEXaLw2/aWR0EPNbMW8PosWlVJ5vH5iX1Hgff7WHy6NuyitHj8ya5ALYo PZui/NKSVIWM/OISW6VoQwsjPUNLCz0jE0s9Q2PzWCsjUyV9O5uU1JzMstQifbsEvYwHK9ey FvyQrbj9dQJbA+NvsS5GTg4JAROJX71/2boYuTiEBJYySvx5fJ4ZIiEmMWnfdnYIW1jiz7Uu NhBbSOATo8Tkv35djBwcbAJ6EjtWFYKERQTqJfrfXAIrYRZ4xSTR8F4DxBYWcJO4Ne8NK4jN IqAqsf7yS0YQm1fAS+L3hPssEOPlJG6e6wRbyyngLdHxeDsjxCoviVX/DjBPYORbwMiwilEk tbQ4Nz232EivODG3uDQvXS85P3cTIzAith37uWUHY9e74EOMAhyMSjy8G34FxQixJpYVV+Ye YpTgYFYS4XXKCokR4k1JrKxKLcqPLyrNSS0+xGgKdNREZinR5HxgtOaVxBuaGppbWBqaG5sb m1koifOeN6iMEhJITyxJzU5NLUgtgulj4uCUamCsOnxXQuKrZxLjgvtCjzO/nE+99TaawbL9 zeFzm4t++JyvlHFPuiBgGi0vr/dsY9aU2BP+KcEVE2a/m7djn++Uvdy3fq/+XFXqvVO78OW3 u8FfbmWdXGa8+FFH2Sn7HSLut8+ncj89ePEVe/fjZ7Hehvqnru2T8VDRCzopvnydMtfEuyfi 1nY9U2Ipzkg01GIuKk4EAApodMSeAgAA X-CMS-MailID: 20190201164721eucas1p286976bab0cc9e06c2cf74a0eaa20144e X-Msg-Generator: CA X-RootMTR: 20190201164721eucas1p286976bab0cc9e06c2cf74a0eaa20144e X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164721eucas1p286976bab0cc9e06c2cf74a0eaa20144e References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 78 +++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 22 ++++++++ 2 files changed, 100 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff158..574d398 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -235,6 +235,36 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>, + <0x10030000 0x1000>, <0x10000000 0x1000>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_DOUT_CLK2X_PHY0>, + <&clock CLK_CLKM_PHY0>, + <&clock CLK_CLKM_PHY1>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + "dout_clk2x_phy0", + "clkm_phy0", + "clkm_phy1"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -271,6 +301,54 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index bf09eab..e2b59e9 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -127,6 +127,12 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>, + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -535,6 +541,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; }; From patchwork Fri Feb 1 16:46:51 2019 Content-Type: text/plain; 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Fri, 1 Feb 2019 16:47:21 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 7/8] drivers: devfreq: events: add Exynos PPMU new events Date: Fri, 1 Feb 2019 17:46:51 +0100 Message-Id: <1549039612-28905-8-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJKsWRmVeSWpSXmKPExsWy7djP87pSFSExBtPP6ltsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLHY9Pgaq8XlXXPYLD73HmG0mHF+H5PF2iN32S1u N65gszj8pp3Vgc9j06pONo/NS+o9Dr7bw+TRt2UVo8fnTXIBrFFcNimpOZllqUX6dglcGbcW TWEveMdWsfb4GsYGxvesXYwcHBICJhIfG226GDk5hARWMErsXcbbxcgFZH9hlJjS28AG4Xxm lPh5upUJpAqk4fLq98wQieWMEp8PLWWGa5l+8TULyFg2AT2JHasKQRpEBKol7lzfD1bDLDCZ SWLR6W6wScICPhKzTj5iBrFZBFQlWo7NYASxeQW8JNY2PmKE2CYncfNcJ1gNp4C3RMfj7Ywg gyQEFrFL/GxoYoMocpG4PuMUVIOwxKvjW9ghbBmJ/zvnQ51dLHG2YxVUfY1E+8kdUDXWEoeP XwSHBbOApsT6XfoQYUeJx0s/QYOIT+LGW0GQMDOQOWnbdGaIMK9ER5sQRLWGxJaeC1CLxCSW r5nGDlHiIfHnUBUkdOYxSix6fJ1pAqP8LIRdCxgZVzGKp5YW56anFhvmpZbrFSfmFpfmpesl 5+duYgQmmNP/jn/awfj1UtIhRgEORiUe3g2/gmKEWBPLiitzDzFKcDArifA6ZYXECPGmJFZW pRblxxeV5qQWH2KU5mBREuetZngQLSSQnliSmp2aWpBaBJNl4uCUamBk/mP1wy0rp2al54pV VzZcfq1WXR3d0CV5gXvn7FM3vt7Znh247PGSKpmQyGtTL2/sark7oSVqJ5vqptlPeO4YPuT4 9bCtOrgrfariFrOKLsao/f5+Ov+nfKvn5asKuexxZvvHdr3fqYzSC34d+FAXy7zybm3U3+Lz T5aVcIq7PTj0anOvYFuqEktxRqKhFnNRcSIAR/ESHywDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t/xe7pSFSExBn+WMltsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLHY9Pgaq8XlXXPYLD73HmG0mHF+H5PF2iN32S1u N65gszj8pp3Vgc9j06pONo/NS+o9Dr7bw+TRt2UVo8fnTXIBrFF6NkX5pSWpChn5xSW2StGG FkZ6hpYWekYmlnqGxuaxVkamSvp2NimpOZllqUX6dgl6GbcWTWEveMdWsfb4GsYGxvesXYyc HBICJhKXV79n7mLk4hASWMoo0dvdxgiREJOYtG87O4QtLPHnWhcbRNEnRolTG44wdTFycLAJ 6EnsWFUIUiMiUC/R/+YSWA2zwHwmif4pc8E2CAv4SMw6+YgZxGYRUJVoOTYDbAGvgJfE2sZH UMvkJG6e6wSr4RTwluh4vB0sLgRUs+rfAeYJjHwLGBlWMYqklhbnpucWG+oVJ+YWl+al6yXn 525iBIb9tmM/N+9gvLQx+BCjAAejEg/vhl9BMUKsiWXFlbmHGCU4mJVEeJ2yQmKEeFMSK6tS i/Lji0pzUosPMZoCHTWRWUo0OR8Yk3kl8YamhuYWlobmxubGZhZK4rznDSqjhATSE0tSs1NT C1KLYPqYODilGhg5O7QOM9ZltrafZix4sXlTQcNXUe8r/lmGbOXH6+aa3/gsNSWdL82txYrb JePxSqWHntbXL5/42fvlReqpQ0myjQcDrrJ5aT6/Kh2+OurP30d3GITMnl50suYUX3lbXKcy /90NbY0p3Q+dDZyXnbS62LU5ce69d23vX29wVv+VYm2apxtw5q8SS3FGoqEWc1FxIgDKuY5J kQIAAA== X-CMS-MailID: 20190201164722eucas1p1b619d939e0f93ddb9ee1af7306e7cf67 X-Msg-Generator: CA X-RootMTR: 20190201164722eucas1p1b619d939e0f93ddb9ee1af7306e7cf67 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164722eucas1p1b619d939e0f93ddb9ee1af7306e7cf67 References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new performance events supported by Exynos5422 SoC counters. The counters are built-in in Dynamic Memory Controller and provide information regarding memory utilization. Signed-off-by: Lukasz Luba --- drivers/devfreq/event/exynos-ppmu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c index c61de0b..67d6674 100644 --- a/drivers/devfreq/event/exynos-ppmu.c +++ b/drivers/devfreq/event/exynos-ppmu.c @@ -89,6 +89,12 @@ static struct __exynos_ppmu_events { PPMU_EVENT(d1-cpu), PPMU_EVENT(d1-general), PPMU_EVENT(d1-rt), + + /* For Exynos5422 SoC */ + PPMU_EVENT(dmc0_0), + PPMU_EVENT(dmc0_1), + PPMU_EVENT(dmc1_0), + PPMU_EVENT(dmc1_1), }; static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev) From patchwork Fri Feb 1 16:46:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10793293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C4A5A13B5 for ; Fri, 1 Feb 2019 16:47:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B5F19324D3 for ; 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Fri, 1 Feb 2019 16:47:23 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190201164722eusmtrp24c530abdf5435a2b8ccc7288d7ce73f8~-S1kZ7XcN0866308663eusmtrp2k; Fri, 1 Feb 2019 16:47:22 +0000 (GMT) X-AuditID: cbfec7f4-835ff700000010c6-6f-5c54781be095 Received: from eusmtip2.samsung.com ( [203.254.199.222]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 46.29.04284.A18745C5; Fri, 1 Feb 2019 16:47:22 +0000 (GMT) Received: from AMDC3778.DIGITAL.local (unknown [106.120.51.20]) by eusmtip2.samsung.com (KnoxPortal) with ESMTPA id 20190201164722eusmtip260af2de1ad4fc7d769441ffbe05e8b24~-S1jpbhfE0078200782eusmtip2i; Fri, 1 Feb 2019 16:47:22 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Russell King , Guenter Roeck , Benson Leung , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 8/8] ARM: exynos_defconfig: enable DMC driver Date: Fri, 1 Feb 2019 17:46:52 +0100 Message-Id: <1549039612-28905-9-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSe0hTYRzt2713u0qr66z8YWG1sLLwkRR9UNR6EKMHREmBCTnz4nvqrjNf 1Xr6IEuMcmhoSaQtTZ2mth7ONRUtnWKlmZq4KFBnxaTogdV2J/13fuec33fODz6akDRQ3nSM MoVVKRXxUqE72dj+w+K/NC0kLGio1R/XaWsoXPShn8QDM58oXGbuoXDXxF0CX7VOEthiqRXh 7nNTIjykWYb11jcU7jfcFGJ7vhlhreWZAJuuP0W42jwiwu/OVgrx86lsSuYh73/TR8hLNH2k XK/LFcrr75yRt04/EcivNOiQ3K73OSgKdd8aycbHpLKqwG3h7tGlZY+IpAEqbfJXpUiD/pB5 yI0GZiO0tBQI85A7LWEqEVRfswn4YQbBPXM74gc7gs5WG5pbMf42krxQgaCsyfx/5byunspD NC1kAqBZl+xYWMRkwvBAC+HwEMwlAqq/dQocgicjg74KI+HAJOML9dZcZ4KY2Qu3H48SfJoP vO3JdWI3Zh/kWJuclYBpF0GdXiviTbuhwNjrusgTJjoaXPwy+POoTMBjDrpzdEIeZ0F2Z7PL swWed/Q5SxOMH9QYAnl6B4wP3icdNDALYNDm4aCJf7CwsYjgaTHkXJLw7rXQcLnXFbQEKqpu uB6Xw+yXTmcxCVOKoObVoQK0vPh/1i2EdMiLVXMJUSwXrGRPBnCKBE6tjAo4kZigR//+0ovZ jplmZPgdYUIMjaTzxbU/D4VJKEUql55gQkAT0kXinbEhYRJxpCI9g1UlHlep41nOhJbSpNRL nDlv7JiEiVKksHEsm8Sq5lQB7eatQZvWrwiGYer1xSOb13QF0aNeD42FoctlaSOSXl0VETp6 euzs7qniwNJzcaHnI4qUp8ZPZh1AMou67fDX05rkDNmuB++vxbcldq1cyP3QLt7v6WtVx10c vvnxc7Vds2rPQlmv+EI4Puq2nV79fdqmpcrzI1/GlucbbOu7/Eoicmi7lOSiFRvWESpO8RcD CzjHRwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsVy+t/xe7pSFSExBrfbjSw2zljPajH9yWUW i+tfnrNazD9yjtXi1KtlzBb9j18zW5w/v4Hd4mzTG3aLWw0yFpseX2O1uLxrDpvF594jjBYz zu9jsjg0dS+jxdojd9ktbjeuYLM4/Kad1UHQ4/K1i8wesxsusnhsWtXJ5rF5Sb3HwXd7mDz6 tqxi9Pi8SS6APUrPpii/tCRVISO/uMRWKdrQwkjP0NJCz8jEUs/Q2DzWyshUSd/OJiU1J7Ms tUjfLkEvY978ncwF11krXv9ewd7A+J+li5GTQ0LAROLAnwNANheHkMBSRol1Ez6zQiTEJCbt 284OYQtL/LnWxQZR9IlR4vKZu0AOBwebgJ7EjlWFIDUiAvUS/W8ugdUwC0xhllg8/w7YIGEB B4mLyw8wg9gsAqoSmx93MoLYvAJeEgt332OGWCAncfNcJ5jNKeAt0fF4O1iNEFDNqn8HmCcw 8i1gZFjFKJJaWpybnltsqFecmFtcmpeul5yfu4kRGCnbjv3cvIPx0sbgQ4wCHIxKPLwbfgXF CLEmlhVX5h5ilOBgVhLhdcoKiRHiTUmsrEotyo8vKs1JLT7EaAp01ERmKdHkfGAU55XEG5oa mltYGpobmxubWSiJ8543qIwSEkhPLEnNTk0tSC2C6WPi4JRqYIxTajOb86LT8vzf9S0n96zL XsuwTnmb8vufB97ELFnjcXOTLpNr8e6DSg3bNuw0dI7d8aIwd2t7OPd2a9kNwVMOPm09Md+c 1Y5h3dUrq5WdTacoFriumaQmLFZuEnBz5nWp2q3HJj/QEumavNho9e/i7PKkWeXevIunB4d/ r2P5H8jpqfwnSVuJpTgj0VCLuag4EQCqakeXqgIAAA== X-CMS-MailID: 20190201164723eucas1p1ec009489584e1c85fd0d62270796e003 X-Msg-Generator: CA X-RootMTR: 20190201164723eucas1p1ec009489584e1c85fd0d62270796e003 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164723eucas1p1ec009489584e1c85fd0d62270796e003 References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable driver for Dynamic Memory Controller dynamic frequency and voltage scaling in Exynos5422 SoCs. Signed-off-by: Lukasz Luba --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index d635edf..b5dddcc 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -291,6 +291,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_EXYNOS_IOMMU=y CONFIG_EXTCON=y