From patchwork Wed May 17 10:55:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuchen X-Patchwork-Id: 13244633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4084CC77B75 for ; Wed, 17 May 2023 10:56:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzEov-0002xz-G9; Wed, 17 May 2023 06:55:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzEoo-0002vZ-3L for qemu-devel@nongnu.org; Wed, 17 May 2023 06:55:43 -0400 Received: from smtp.h3c.com ([60.191.123.56] helo=h3cspam01-ex.h3c.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzEok-0002t3-L4 for qemu-devel@nongnu.org; Wed, 17 May 2023 06:55:41 -0400 Received: from mail.maildlp.com ([172.25.15.155]) by h3cspam01-ex.h3c.com with ESMTP id 34HAtCwP049402; Wed, 17 May 2023 18:55:12 +0800 (GMT-8) (envelope-from yu.chen@h3c.com) Received: from DAG2EX08-IDC.srv.huawei-3com.com (unknown [172.20.54.131]) by mail.maildlp.com (Postfix) with ESMTP id 6C0DF222E3C7; Wed, 17 May 2023 18:59:09 +0800 (CST) Received: from DAG2EX10-IDC.srv.huawei-3com.com (172.20.54.133) by DAG2EX08-IDC.srv.huawei-3com.com (172.20.54.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Wed, 17 May 2023 18:55:14 +0800 Received: from DAG2EX10-IDC.srv.huawei-3com.com ([fe80::e886:502d:5063:7e2b]) by DAG2EX10-IDC.srv.huawei-3com.com ([fe80::e886:502d:5063:7e2b%10]) with mapi id 15.01.2507.021; Wed, 17 May 2023 18:55:14 +0800 From: Yuchen To: "qemu-devel@nongnu.org" CC: "pbonzini@redhat.com" , "rth@twiddle.net" , "ehabkost@redhat.com" , Chengchiwen Subject: [PATCH] target/i386: Clear xsave pkru bit when KVM XCR0 not support Thread-Topic: [PATCH] target/i386: Clear xsave pkru bit when KVM XCR0 not support Thread-Index: AdmH10nRMdIv88FeTxmtO8yhX/g2Mg== Date: Wed, 17 May 2023 10:55:13 +0000 Message-ID: <914d4bfc6901485c9f029ce26ceb7d10@h3c.com> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.99.196.41] x-sender-location: DAG2 MIME-Version: 1.0 X-DNSRBL: X-MAIL: h3cspam01-ex.h3c.com 34HAtCwP049402 Received-SPF: pass client-ip=60.191.123.56; envelope-from=yu.chen@h3c.com; helo=h3cspam01-ex.h3c.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, HTML_MESSAGE=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Migrating guest from Intel new CPU (as Gold 6230) to old CPU (as E5-2650 v4) will pause on the destination host. Because old CPU not support xsave pkru feature, and KVM KVM_SET_XSAVE ioctl return EINVAL. This kernel commit introduces the problem: ea4d6938d4c0 x86/fpu: Replace KVMs home brewed FPU copy from user Signed-off-by: YuChen --- target/i386/xsave_helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) } + if (!has_xsave_pkru) { + env->xstate_bv &= ~XSTATE_PKRU_MASK; + } header->xstate_bv = env->xstate_bv; e = &x86_ext_save_areas[XSTATE_YMM_BIT]; @@ -181,6 +186,9 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen) env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm + 8); } + if (xsave->header.xstate_bv & XSTATE_PKRU_MASK) { + has_xsave_pkru = true; + } env->xstate_bv = header->xstate_bv; e = &x86_ext_save_areas[XSTATE_YMM_BIT]; -- 2.34.1 ------------------------------------------------------------------------------------------------------------------------------------- ????????????????????????????????? ???????????????????????????????????????? ???????????????????????????????????????? ??? This e-mail and its attachments contain confidential information from New H3C, which is intended only for the person or entity whose address is listed above. Any use of the information contained herein in any way (including, but not limited to, total or partial disclosure, reproduction, or dissemination) by persons other than the intended recipient(s) is prohibited. If you receive this e-mail in error, please notify the sender by phone or email immediately and delete it! diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 996e9f3bfe..64e2b969fe 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -6,6 +6,8 @@ #include "cpu.h" +static bool has_xsave_pkru; + void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) { CPUX86State *env = &cpu->env; @@ -47,6 +49,9 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) stq_p(xmm + 8, env->xmm_regs[i].ZMM_Q(1));