From patchwork Wed May 17 11:56:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zelong dong X-Patchwork-Id: 13244795 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B97C6C77B75 for ; Wed, 17 May 2023 11:57:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231400AbjEQL5i (ORCPT ); Wed, 17 May 2023 07:57:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231322AbjEQL5g (ORCPT ); Wed, 17 May 2023 07:57:36 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9EEC359E for ; Wed, 17 May 2023 04:56:50 -0700 (PDT) Received: from droid10-sz.amlogic.com (10.28.11.69) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Wed, 17 May 2023 19:56:39 +0800 From: zelong dong To: Neil Armstrong , Sean Young , Mauro Carvalho Chehab , Rob Herring , Jerome Brunet , Kevin Hilman , Martin Blumenstingl CC: , , , , , Zelong Dong Subject: [PATCH v2 1/3] media: rc: meson-ir: sort Meson IR Controller register macros Date: Wed, 17 May 2023 19:56:33 +0800 Message-ID: <20230517115635.31565-2-zelong.dong@amlogic.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230517115635.31565-1-zelong.dong@amlogic.com> References: <20230517115635.31565-1-zelong.dong@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.11.69] Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Zelong Dong There are more registers to come in the next Meson IR Controller. For defining clearly, sort register macros and let address and bit macros as a set. Signed-off-by: Zelong Dong Reviewed-by: Neil Armstrong --- drivers/media/rc/meson-ir.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c index 4b769111f78e..a32d034b33aa 100644 --- a/drivers/media/rc/meson-ir.c +++ b/drivers/media/rc/meson-ir.c @@ -19,44 +19,43 @@ #define DRIVER_NAME "meson-ir" -/* valid on all Meson platforms */ #define IR_DEC_LDR_ACTIVE 0x00 + #define IR_DEC_LDR_IDLE 0x04 + #define IR_DEC_LDR_REPEAT 0x08 + #define IR_DEC_BIT_0 0x0c -#define IR_DEC_REG0 0x10 -#define IR_DEC_FRAME 0x14 -#define IR_DEC_STATUS 0x18 -#define IR_DEC_REG1 0x1c -/* only available on Meson 8b and newer */ -#define IR_DEC_REG2 0x20 +#define IR_DEC_REG0 0x10 #define REG0_RATE_MASK GENMASK(11, 0) -#define DECODE_MODE_NEC 0x0 -#define DECODE_MODE_RAW 0x2 +#define IR_DEC_FRAME 0x14 + +#define IR_DEC_STATUS 0x18 +#define STATUS_IR_DEC_IN BIT(8) -/* Meson 6b uses REG1 to configure the mode */ +#define IR_DEC_REG1 0x1c +#define REG1_TIME_IV_MASK GENMASK(28, 16) +#define REG1_ENABLE BIT(15) #define REG1_MODE_MASK GENMASK(8, 7) #define REG1_MODE_SHIFT 7 +#define REG1_IRQSEL_MASK GENMASK(3, 2) +#define REG1_RESET BIT(0) -/* Meson 8b / GXBB use REG2 to configure the mode */ +/* The following regs are only available on Meson 8b and newer */ +#define IR_DEC_REG2 0x20 #define REG2_MODE_MASK GENMASK(3, 0) #define REG2_MODE_SHIFT 0 -#define REG1_TIME_IV_MASK GENMASK(28, 16) +#define DECODE_MODE_NEC 0x0 +#define DECODE_MODE_RAW 0x2 -#define REG1_IRQSEL_MASK GENMASK(3, 2) #define REG1_IRQSEL_NEC_MODE 0 #define REG1_IRQSEL_RISE_FALL 1 #define REG1_IRQSEL_FALL 2 #define REG1_IRQSEL_RISE 3 -#define REG1_RESET BIT(0) -#define REG1_ENABLE BIT(15) - -#define STATUS_IR_DEC_IN BIT(8) - #define MESON_TRATE 10 /* us */ struct meson_ir { From patchwork Wed May 17 11:56:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zelong dong X-Patchwork-Id: 13244794 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A1E6C77B7F for ; Wed, 17 May 2023 11:57:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231395AbjEQL5h (ORCPT ); Wed, 17 May 2023 07:57:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231236AbjEQL5g (ORCPT ); Wed, 17 May 2023 07:57:36 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 301EF3A90 for ; Wed, 17 May 2023 04:56:52 -0700 (PDT) Received: from droid10-sz.amlogic.com (10.28.11.69) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Wed, 17 May 2023 19:56:41 +0800 From: zelong dong To: Neil Armstrong , Sean Young , Mauro Carvalho Chehab , Rob Herring , Jerome Brunet , Kevin Hilman , Martin Blumenstingl CC: , , , , , Zelong Dong Subject: [PATCH v2 2/3] media: rc: meson-ir: rename Meson IR Controller register macros Date: Wed, 17 May 2023 19:56:34 +0800 Message-ID: <20230517115635.31565-3-zelong.dong@amlogic.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230517115635.31565-1-zelong.dong@amlogic.com> References: <20230517115635.31565-1-zelong.dong@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.11.69] Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Zelong Dong There are more registers to come in the next Meson IR Controller. For defining clearly, rename register macros. Signed-off-by: Zelong Dong Reviewed-by: Neil Armstrong --- drivers/media/rc/meson-ir.c | 80 ++++++++++++++++++------------------- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c index a32d034b33aa..7ab6304f7184 100644 --- a/drivers/media/rc/meson-ir.c +++ b/drivers/media/rc/meson-ir.c @@ -20,43 +20,39 @@ #define DRIVER_NAME "meson-ir" #define IR_DEC_LDR_ACTIVE 0x00 - #define IR_DEC_LDR_IDLE 0x04 - #define IR_DEC_LDR_REPEAT 0x08 - #define IR_DEC_BIT_0 0x0c #define IR_DEC_REG0 0x10 -#define REG0_RATE_MASK GENMASK(11, 0) +#define IR_DEC_REG0_BASE_TIME GENMASK(11, 0) #define IR_DEC_FRAME 0x14 #define IR_DEC_STATUS 0x18 -#define STATUS_IR_DEC_IN BIT(8) +#define IR_DEC_STATUS_PULSE BIT(8) #define IR_DEC_REG1 0x1c -#define REG1_TIME_IV_MASK GENMASK(28, 16) -#define REG1_ENABLE BIT(15) -#define REG1_MODE_MASK GENMASK(8, 7) -#define REG1_MODE_SHIFT 7 -#define REG1_IRQSEL_MASK GENMASK(3, 2) -#define REG1_RESET BIT(0) +#define IR_DEC_REG1_TIME_IV GENMASK(28, 16) +#define IR_DEC_REG1_ENABLE BIT(15) +#define IR_DEC_REG1_MODE GENMASK(8, 7) +#define IR_DEC_REG1_IRQSEL GENMASK(3, 2) +#define IR_DEC_REG1_RESET BIT(0) /* The following regs are only available on Meson 8b and newer */ #define IR_DEC_REG2 0x20 -#define REG2_MODE_MASK GENMASK(3, 0) -#define REG2_MODE_SHIFT 0 +#define IR_DEC_REG2_MODE GENMASK(3, 0) -#define DECODE_MODE_NEC 0x0 -#define DECODE_MODE_RAW 0x2 +#define DEC_MODE_NEC 0x0 +#define DEC_MODE_RAW 0x2 -#define REG1_IRQSEL_NEC_MODE 0 -#define REG1_IRQSEL_RISE_FALL 1 -#define REG1_IRQSEL_FALL 2 -#define REG1_IRQSEL_RISE 3 +#define IRQSEL_NEC_MODE 0 +#define IRQSEL_RISE_FALL 1 +#define IRQSEL_FALL 2 +#define IRQSEL_RISE 3 -#define MESON_TRATE 10 /* us */ +#define MESON_RAW_TRATE 10 /* us */ +#define MESON_HW_TRATE 20 /* us */ struct meson_ir { void __iomem *reg; @@ -84,11 +80,11 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id) spin_lock(&ir->lock); duration = readl_relaxed(ir->reg + IR_DEC_REG1); - duration = FIELD_GET(REG1_TIME_IV_MASK, duration); - rawir.duration = duration * MESON_TRATE; + duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration); + rawir.duration = duration * MESON_RAW_TRATE; status = readl_relaxed(ir->reg + IR_DEC_STATUS); - rawir.pulse = !!(status & STATUS_IR_DEC_IN); + rawir.pulse = !!(status & IR_DEC_STATUS_PULSE); ir_raw_event_store_with_timeout(ir->rc, &rawir); @@ -130,7 +126,7 @@ static int meson_ir_probe(struct platform_device *pdev) map_name = of_get_property(node, "linux,rc-map-name", NULL); ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY; ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; - ir->rc->rx_resolution = MESON_TRATE; + ir->rc->rx_resolution = MESON_RAW_TRATE; ir->rc->min_timeout = 1; ir->rc->timeout = IR_DEFAULT_TIMEOUT; ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT; @@ -152,24 +148,27 @@ static int meson_ir_probe(struct platform_device *pdev) } /* Reset the decoder */ - meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET); - meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0); + meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET, + IR_DEC_REG1_RESET); + meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET, 0); /* Set general operation mode (= raw/software decoding) */ if (of_device_is_compatible(node, "amlogic,meson6-ir")) - meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK, - FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW)); + meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE, + FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW)); else - meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK, - FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW)); + meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE, + FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW)); /* Set rate */ - meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1); + meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, + MESON_RAW_TRATE - 1); /* IRQ on rising and falling edges */ - meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK, - FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL)); + meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_IRQSEL, + FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL)); /* Enable the decoder */ - meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE); + meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE, + IR_DEC_REG1_ENABLE); dev_info(dev, "receiver initialized\n"); @@ -183,7 +182,7 @@ static int meson_ir_remove(struct platform_device *pdev) /* Disable the decoder */ spin_lock_irqsave(&ir->lock, flags); - meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0); + meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0); spin_unlock_irqrestore(&ir->lock, flags); return 0; @@ -203,14 +202,15 @@ static void meson_ir_shutdown(struct platform_device *pdev) * bootloader a chance to power the system back on */ if (of_device_is_compatible(node, "amlogic,meson6-ir")) - meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK, - DECODE_MODE_NEC << REG1_MODE_SHIFT); + meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE, + FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC)); else - meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK, - DECODE_MODE_NEC << REG2_MODE_SHIFT); + meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE, + FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC)); /* Set rate to default value */ - meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13); + meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, + MESON_HW_TRATE - 1); spin_unlock_irqrestore(&ir->lock, flags); } From patchwork Wed May 17 11:56:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zelong dong X-Patchwork-Id: 13244793 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7B01C77B75 for ; Wed, 17 May 2023 11:56:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231388AbjEQL45 (ORCPT ); Wed, 17 May 2023 07:56:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231329AbjEQL4z (ORCPT ); Wed, 17 May 2023 07:56:55 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBB7D40E5 for ; Wed, 17 May 2023 04:56:53 -0700 (PDT) Received: from droid10-sz.amlogic.com (10.28.11.69) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Wed, 17 May 2023 19:56:43 +0800 From: zelong dong To: Neil Armstrong , Sean Young , Mauro Carvalho Chehab , Rob Herring , Jerome Brunet , Kevin Hilman , Martin Blumenstingl CC: , , , , , Zelong Dong Subject: [PATCH v2 3/3] media: rc: meson-ir: support MMIO regmaps to access registers Date: Wed, 17 May 2023 19:56:35 +0800 Message-ID: <20230517115635.31565-4-zelong.dong@amlogic.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230517115635.31565-1-zelong.dong@amlogic.com> References: <20230517115635.31565-1-zelong.dong@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.11.69] Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Zelong Dong Supports MMIO regmaps to access controller registers in Meson IR driver. Signed-off-by: Zelong Dong --- drivers/media/rc/meson-ir.c | 72 +++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 34 deletions(-) diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c index 7ab6304f7184..ac4ebaa3904c 100644 --- a/drivers/media/rc/meson-ir.c +++ b/drivers/media/rc/meson-ir.c @@ -14,6 +14,7 @@ #include #include #include +#include #include @@ -55,21 +56,16 @@ #define MESON_HW_TRATE 20 /* us */ struct meson_ir { - void __iomem *reg; + struct regmap *reg; struct rc_dev *rc; spinlock_t lock; }; -static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg, - u32 mask, u32 value) -{ - u32 data; - - data = readl(ir->reg + reg); - data &= ~mask; - data |= (value & mask); - writel(data, ir->reg + reg); -} +static struct regmap_config meson_ir_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; static irqreturn_t meson_ir_irq(int irqno, void *dev_id) { @@ -79,11 +75,11 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id) spin_lock(&ir->lock); - duration = readl_relaxed(ir->reg + IR_DEC_REG1); + regmap_read(ir->reg, IR_DEC_REG1, &duration); duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration); rawir.duration = duration * MESON_RAW_TRATE; - status = readl_relaxed(ir->reg + IR_DEC_STATUS); + regmap_read(ir->reg, IR_DEC_STATUS, &status); rawir.pulse = !!(status & IR_DEC_STATUS_PULSE); ir_raw_event_store_with_timeout(ir->rc, &rawir); @@ -97,6 +93,7 @@ static int meson_ir_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; + void __iomem *res_start; const char *map_name; struct meson_ir *ir; int irq, ret; @@ -105,7 +102,12 @@ static int meson_ir_probe(struct platform_device *pdev) if (!ir) return -ENOMEM; - ir->reg = devm_platform_ioremap_resource(pdev, 0); + res_start = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(res_start)) + return PTR_ERR(res_start); + + ir->reg = devm_regmap_init_mmio(&pdev->dev, res_start, + &meson_ir_regmap_config); if (IS_ERR(ir->reg)) return PTR_ERR(ir->reg); @@ -148,27 +150,28 @@ static int meson_ir_probe(struct platform_device *pdev) } /* Reset the decoder */ - meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET, - IR_DEC_REG1_RESET); - meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET, 0); + regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, + IR_DEC_REG1_RESET); + regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0); /* Set general operation mode (= raw/software decoding) */ if (of_device_is_compatible(node, "amlogic,meson6-ir")) - meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE, - FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW)); + regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE, + FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW)); else - meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE, - FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW)); + regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, + FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW)); /* Set rate */ - meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, - MESON_RAW_TRATE - 1); + regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, + FIELD_PREP(IR_DEC_REG0_BASE_TIME, + MESON_RAW_TRATE - 1)); /* IRQ on rising and falling edges */ - meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_IRQSEL, - FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL)); + regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL, + FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL)); /* Enable the decoder */ - meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE, - IR_DEC_REG1_ENABLE); + regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, + IR_DEC_REG1_ENABLE); dev_info(dev, "receiver initialized\n"); @@ -182,7 +185,7 @@ static int meson_ir_remove(struct platform_device *pdev) /* Disable the decoder */ spin_lock_irqsave(&ir->lock, flags); - meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0); + regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0); spin_unlock_irqrestore(&ir->lock, flags); return 0; @@ -202,15 +205,16 @@ static void meson_ir_shutdown(struct platform_device *pdev) * bootloader a chance to power the system back on */ if (of_device_is_compatible(node, "amlogic,meson6-ir")) - meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE, - FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC)); + regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE, + FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC)); else - meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE, - FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC)); + regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, + FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC)); /* Set rate to default value */ - meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, - MESON_HW_TRATE - 1); + regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, + FIELD_PREP(IR_DEC_REG0_BASE_TIME, + MESON_HW_TRATE - 1)); spin_unlock_irqrestore(&ir->lock, flags); }