From patchwork Thu May 18 13:09:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DF61C77B7D for ; Thu, 18 May 2023 13:11:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZAD1luoang9sMR9bm8dG1ha2eJ5uyu1jmyNbkghH048=; b=pjokLhkW1vtYQX TQZcCMwGNnjnG8c8b4CNqKHzOnqDGvtn2KWfd3Xnz22TCDsWwOZND7hppQs6rbzjlCB8BmOD2kKJm GPSVKWTRgii9cXc4WnstyfLUb6hEQ/uLDMYTh4pYxPA+PxDSVE+ZCjPn7h50reDK60p06RqQD3Xa2 8UcpaiKNXu7YxRtKYta8VVX5wBWfdAmI09tbaqqi+hB2ZQhTbGH3B8LWMAaVW2DKcDcC5xLtiEuWp UV9bT/x8VEtm3w4s01O/jM36ynbBvb/zQIE74t/UxPIxu+v/lWpwhcydi8qvZo26SaKMO+g6uA+NC VdPThq4KhFC3U2MkKeNA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzdPJ-00D1ya-03; Thu, 18 May 2023 13:11:01 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdPF-00D1xr-0z for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:10:59 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C5E9264F36; Thu, 18 May 2023 13:10:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED15CC433A8; Thu, 18 May 2023 13:10:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415456; bh=dIHdwvZEudsqHMu5s9YuHTx8NxWZy6Q3fEAityYqUho=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V7oF99ZvljCZIOzFW51A3fZFEU+AZ0Ylc0WcebtlQ7dxxV8Oh6nbpdl/bkgV0Dgos oCFhvdVLPPTyO1uMdMJi9mkBVxmvcOLpvb9VQYOXhVFkXyp1awIdxcoz/ppzabcr/p 0T4e5Y3rT3AERrBFx6E1aygYAtYx+Sz1h0RX0ZKx/d+7HcJ/rNC5vX9ZJuNtmoS2B+ Xta9XLJ+NGZYwNuNtn8zCVY44jgWiE4qb8Yf1YXaKWTiZuk1feUWXlUSMBiLT0TACP ukDW7uSIp3pDraIeCJfqCy0S1fHKBd9bIB0vSJGd1jt0pvJR4fbQAndzBP3DgMk4T1 /2zWXM6XUG9RA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 01/22] riscv: vdso: Unify vdso32 & compat_vdso into vdso/Makefile Date: Thu, 18 May 2023 09:09:52 -0400 Message-Id: <20230518131013.3366406-2-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061057_428493_BFADAF96 X-CRM114-Status: GOOD ( 21.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Linux kernel abi and vdso abi could be different, and current vdso/Makefile force vdso use the same abi as the kernel. It isn't suitable for the next s64ilp32 patch series because s64ilp32 uses 64ilp32 abi in the kernel but still uses 32ilp32 in the userspace. This patch unifies vdso32 & compat_vdso into vdso/Makefile to solve this problem, similar to Powerpc's vdso framework. Before this: - vdso/ - vdso/vdso.S - vdso/gen_vdso_offsets.sh - compat_vdso/compat_vdso.S - compat_vdso/gen_compat_vdso_offsets.sh - vdso.c After this: - vdso/ - vdso64.S - vdso/gen_vdso64_offsets.sh - vdso32.S - vdso/gen_vdso32_offsets.sh - vdso.c Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 11 ++ arch/riscv/Makefile | 15 +- arch/riscv/include/asm/vdso.h | 34 +++- arch/riscv/include/asm/vdso/gettimeofday.h | 7 +- arch/riscv/kernel/Makefile | 3 +- arch/riscv/kernel/compat_signal.c | 2 +- arch/riscv/kernel/vdso.c | 4 +- arch/riscv/kernel/vdso/Makefile | 179 ++++++++++++------ ..._vdso_offsets.sh => gen_vdso32_offsets.sh} | 2 +- arch/riscv/kernel/vdso/gen_vdso64_offsets.sh | 5 + arch/riscv/kernel/vdso32.S | 8 + arch/riscv/kernel/{vdso/vdso.S => vdso64.S} | 8 +- 12 files changed, 197 insertions(+), 81 deletions(-) rename arch/riscv/kernel/vdso/{gen_vdso_offsets.sh => gen_vdso32_offsets.sh} (78%) create mode 100755 arch/riscv/kernel/vdso/gen_vdso64_offsets.sh create mode 100644 arch/riscv/kernel/vdso32.S rename arch/riscv/kernel/{vdso/vdso.S => vdso64.S} (73%) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c58d74235363..643884620cd6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -5,9 +5,11 @@ # config 64BIT + select VDSO64 bool config 32BIT + select VDSO32 bool config RISCV @@ -248,6 +250,14 @@ config RISCV_DMA_NONCOHERENT config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) +config VDSO32 + bool + depends on MMU + +config VDSO64 + bool + depends on MMU + source "arch/riscv/Kconfig.socs" source "arch/riscv/Kconfig.errata" @@ -594,6 +604,7 @@ config CRASH_DUMP config COMPAT bool "Kernel support for 32-bit U-mode" default 64BIT + select VDSO32 depends on 64BIT && MMU help This option enables support for a 32-bit U-mode running under a 64-bit diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index e859e1721a8f..dafe958c4217 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -122,18 +122,19 @@ libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a PHONY += vdso_install vdso_install: - $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@ - $(if $(CONFIG_COMPAT),$(Q)$(MAKE) \ - $(build)=arch/riscv/kernel/compat_vdso compat_$@) + $(if $(CONFIG_VDSO32),$(Q)$(MAKE) \ + $(build)=arch/riscv/kernel/vdso vdso32_install + $(if $(CONFIG_VDSO64),$(Q)$(MAKE) \ + $(build)=arch/riscv/kernel/vdso vdso64_install ifeq ($(KBUILD_EXTMOD),) ifeq ($(CONFIG_MMU),y) prepare: vdso_prepare vdso_prepare: prepare0 - $(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso include/generated/vdso-offsets.h - $(if $(CONFIG_COMPAT),$(Q)$(MAKE) \ - $(build)=arch/riscv/kernel/compat_vdso include/generated/compat_vdso-offsets.h) - + $(if $(CONFIG_VDSO32),$(Q)$(MAKE) \ + $(build)=arch/riscv/kernel/vdso include/generated/vdso32-offsets.h) + $(if $(CONFIG_VDSO64),$(Q)$(MAKE) \ + $(build)=arch/riscv/kernel/vdso include/generated/vdso64-offsets.h) endif endif diff --git a/arch/riscv/include/asm/vdso.h b/arch/riscv/include/asm/vdso.h index f891478829a5..305ddc6de21c 100644 --- a/arch/riscv/include/asm/vdso.h +++ b/arch/riscv/include/asm/vdso.h @@ -17,22 +17,36 @@ #define __VVAR_PAGES 2 #ifndef __ASSEMBLY__ -#include -#define VDSO_SYMBOL(base, name) \ - (void __user *)((unsigned long)(base) + __vdso_##name##_offset) +#ifdef CONFIG_VDSO64 +#include -#ifdef CONFIG_COMPAT -#include +#define VDSO64_SYMBOL(base, name) \ + (void __user *)((unsigned long)(base) + rv64__vdso_##name##_offset) -#define COMPAT_VDSO_SYMBOL(base, name) \ - (void __user *)((unsigned long)(base) + compat__vdso_##name##_offset) +extern char vdso64_start[], vdso64_end[]; -extern char compat_vdso_start[], compat_vdso_end[]; +#endif /* CONFIG_VDSO64 */ -#endif /* CONFIG_COMPAT */ +#ifdef CONFIG_VDSO32 +#include -extern char vdso_start[], vdso_end[]; +#define VDSO32_SYMBOL(base, name) \ + (void __user *)((unsigned long)(base) + rv32__vdso_##name##_offset) + +extern char vdso32_start[], vdso32_end[]; + +#endif /* CONFIG_VDSO32 */ + +#ifdef CONFIG_64BIT +#define vdso_start vdso64_start +#define vdso_end vdso64_end +#define VDSO_SYMBOL VDSO64_SYMBOL +#else /* CONFIG_64BIT */ +#define vdso_start vdso32_start +#define vdso_end vdso32_end +#define VDSO_SYMBOL VDSO32_SYMBOL +#endif /* CONFIG_64BIT */ #endif /* !__ASSEMBLY__ */ diff --git a/arch/riscv/include/asm/vdso/gettimeofday.h b/arch/riscv/include/asm/vdso/gettimeofday.h index ba3283cf7acc..a7ae8576797b 100644 --- a/arch/riscv/include/asm/vdso/gettimeofday.h +++ b/arch/riscv/include/asm/vdso/gettimeofday.h @@ -17,6 +17,7 @@ #define VDSO_HAS_CLOCK_GETRES 1 +#ifdef __NR_gettimeofday static __always_inline int gettimeofday_fallback(struct __kernel_old_timeval *_tv, struct timezone *_tz) @@ -33,7 +34,9 @@ int gettimeofday_fallback(struct __kernel_old_timeval *_tv, return ret; } +#endif +#ifdef __NR_clock_gettime static __always_inline long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) { @@ -49,7 +52,9 @@ long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) return ret; } +#endif +#ifdef __NR_clock_getres static __always_inline int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) { @@ -65,7 +70,7 @@ int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) return ret; } - +#endif #endif /* CONFIG_GENERIC_TIME_VSYSCALL */ static __always_inline u64 __arch_get_hw_counter(s32 clock_mode, diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 392fa6e35d4a..93de624f7fcd 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -52,6 +52,8 @@ obj-y += cacheinfo.o obj-y += patch.o obj-y += probes/ obj-$(CONFIG_MMU) += vdso.o vdso/ +obj-$(CONFIG_VDSO64) += vdso64.o +obj-$(CONFIG_VDSO32) += vdso32.o obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o @@ -86,4 +88,3 @@ obj-$(CONFIG_JUMP_LABEL) += jump_label.o obj-$(CONFIG_EFI) += efi.o obj-$(CONFIG_COMPAT) += compat_syscall_table.o obj-$(CONFIG_COMPAT) += compat_signal.o -obj-$(CONFIG_COMPAT) += compat_vdso/ diff --git a/arch/riscv/kernel/compat_signal.c b/arch/riscv/kernel/compat_signal.c index 6ec4e34255a9..8dea2012836e 100644 --- a/arch/riscv/kernel/compat_signal.c +++ b/arch/riscv/kernel/compat_signal.c @@ -217,7 +217,7 @@ int compat_setup_rt_frame(struct ksignal *ksig, sigset_t *set, if (err) return -EFAULT; - regs->ra = (unsigned long)COMPAT_VDSO_SYMBOL( + regs->ra = (unsigned long)VDSO32_SYMBOL( current->mm->context.vdso, rt_sigreturn); /* diff --git a/arch/riscv/kernel/vdso.c b/arch/riscv/kernel/vdso.c index 9a68e7eaae4d..497cde87dc69 100644 --- a/arch/riscv/kernel/vdso.c +++ b/arch/riscv/kernel/vdso.c @@ -193,8 +193,8 @@ static struct vm_special_mapping rv_compat_vdso_maps[] __ro_after_init = { static struct __vdso_info compat_vdso_info __ro_after_init = { .name = "compat_vdso", - .vdso_code_start = compat_vdso_start, - .vdso_code_end = compat_vdso_end, + .vdso_code_start = vdso32_start, + .vdso_code_end = vdso32_end, .dm = &rv_compat_vdso_maps[RV_VDSO_MAP_VVAR], .cm = &rv_compat_vdso_maps[RV_VDSO_MAP_VDSO], }; diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile index 022258426050..e3c3bf669c7b 100644 --- a/arch/riscv/kernel/vdso/Makefile +++ b/arch/riscv/kernel/vdso/Makefile @@ -1,87 +1,158 @@ # SPDX-License-Identifier: GPL-2.0-only -# Copied from arch/tile/kernel/vdso/Makefile # Absolute relocation type $(ARCH_REL_TYPE_ABS) needs to be defined before # the inclusion of generic Makefile. ARCH_REL_TYPE_ABS := R_RISCV_32|R_RISCV_64|R_RISCV_JUMP_SLOT include $(srctree)/lib/vdso/Makefile -# Symbols present in the vdso -vdso-syms = rt_sigreturn -ifdef CONFIG_64BIT -vdso-syms += vgettimeofday -endif -vdso-syms += getcpu -vdso-syms += flush_icache -vdso-syms += hwprobe -vdso-syms += sys_hwprobe -# Files to link into the vdso -obj-vdso = $(patsubst %, %.o, $(vdso-syms)) note.o +VDSO_CC := $(CC) +VDSO_LD := $(LD) + +# Disable profiling and instrumentation for VDSO code +GCOV_PROFILE := n +KCOV_INSTRUMENT := n +KASAN_SANITIZE := n +UBSAN_SANITIZE := n ccflags-y := -fno-stack-protector ccflags-y += -DDISABLE_BRANCH_PROFILING -ifneq ($(c-gettimeofday-y),) - CFLAGS_vgettimeofday.o += -fPIC -include $(c-gettimeofday-y) +CPPFLAGS_vdso.lds += -P -C -U$(ARCH) +ifneq ($(filter vgettimeofday, $(vdso-cc-syms)),) + CPPFLAGS_vdso.lds += -DHAS_VGETTIMEOFDAY endif -CFLAGS_hwprobe.o += -fPIC +# strip rule for the .so file +$(obj)/%.so: OBJCOPYFLAGS := -S +$(obj)/%.so: $(obj)/%.so.dbg FORCE + $(call if_changed,objcopy) -# Build rules -targets := $(obj-vdso) vdso.so vdso.so.dbg vdso.lds -obj-vdso := $(addprefix $(obj)/, $(obj-vdso)) +# install commands for the unstripped file +quiet_cmd_vdso_install = INSTALL $@ + cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@ -obj-y += vdso.o -CPPFLAGS_vdso.lds += -P -C -U$(ARCH) -ifneq ($(filter vgettimeofday, $(vdso-syms)),) -CPPFLAGS_vdso.lds += -DHAS_VGETTIMEOFDAY -endif +# Symbols present in the vdso +ifdef CONFIG_VDSO64 +vdso64-as-syms = rt_sigreturn +vdso64-as-syms += getcpu +vdso64-as-syms += flush_icache +vdso64-as-syms += sys_hwprobe -# Disable -pg to prevent insert call site -CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) +vdso64-cc-syms = vgettimeofday +vdso64-cc-syms += hwprobe -# Disable profiling and instrumentation for VDSO code -GCOV_PROFILE := n -KCOV_INSTRUMENT := n -KASAN_SANITIZE := n -UBSAN_SANITIZE := n +obj-as-vdso64 = $(patsubst %, %-64.o, $(vdso64-as-syms)) note-64.o +obj-as-vdso64 := $(addprefix $(obj)/, $(obj-as-vdso64)) -# Force dependency -$(obj)/vdso.o: $(obj)/vdso.so +obj-cc-vdso64 = $(patsubst %, %-64.o, $(vdso64-cc-syms)) +obj-cc-vdso64 := $(addprefix $(obj)/, $(obj-cc-vdso64)) -# link rule for the .so file, .lds has to be first -$(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE - $(call if_changed,vdsold) -LDFLAGS_vdso.so.dbg = -shared -S -soname=linux-vdso.so.1 \ +targets += $(obj-as-vdso64) $(obj-cc-vdso64) vdso64.so vdso64.so.dbg vdso64.lds + +$(obj)/vdso64.so.dbg: $(obj)/vdso.lds $(obj-as-vdso64) $(obj-cc-vdso64) FORCE + $(call if_changed,vdso64ld) +LDFLAGS_vdso64.so.dbg = -shared -S -soname=linux-vdso64.so.1 \ --build-id=sha1 --hash-style=both --eh-frame-hdr +# The DSO images are built using a special linker script +# Make sure only to export the intended __vdso_xxx symbol offsets. +quiet_cmd_vdso64ld = VDSO64LD $@ + cmd_vdso64ld = $(VDSO_LD) $(ld_flags) $(VDSO64_LD_FLAGS) -T $(filter-out FORCE,$^) -o $@.tmp && \ + $(OBJCOPY) $(patsubst %, -G __vdso_%, $(vdso64-as-syms) $(vdso64-cc-syms)) $@.tmp $@ && \ + rm $@.tmp -# strip rule for the .so file -$(obj)/%.so: OBJCOPYFLAGS := -S -$(obj)/%.so: $(obj)/%.so.dbg FORCE - $(call if_changed,objcopy) +# actual build commands +quiet_cmd_vdso64as = VDSO64AS $@ + cmd_vdso64as = $(VDSO_CC) $(a_flags) $(VDSO64_CC_FLAGS) -c -o $@ $< +quiet_cmd_vdso64cc = VDSO64CC $@ + cmd_vdso64cc = $(VDSO_CC) $(c_flags) $(VDSO64_CC_FLAGS) -c -o $@ $< + +# Force dependency +$(obj)/vdso64.o: $(obj)/vdso64.so + +$(obj-as-vdso64): %-64.o: %.S FORCE + $(call if_changed_dep,vdso64as) +$(obj-cc-vdso64): %-64.o: %.c FORCE + $(call if_changed_dep,vdso64cc) + +CFLAGS_vgettimeofday-64.o += -fPIC -include $(c-gettimeofday-y) +# Disable -pg to prevent insert call site +CFLAGS_REMOVE_vgettimeofday-64.o = $(CC_FLAGS_FTRACE) + +CFLAGS_hwprobe-64.o += -fPIC # Generate VDSO offsets using helper script -gen-vdsosym := $(srctree)/$(src)/gen_vdso_offsets.sh -quiet_cmd_vdsosym = VDSOSYM $@ - cmd_vdsosym = $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@ +gen-vdso64sym := $(srctree)/$(src)/gen_vdso64_offsets.sh +quiet_cmd_vdso64sym = VDSO64SYM $@ + cmd_vdso64sym = $(NM) $< | $(gen-vdso64sym) | LC_ALL=C sort > $@ -include/generated/vdso-offsets.h: $(obj)/vdso.so.dbg FORCE - $(call if_changed,vdsosym) +include/generated/vdso64-offsets.h: $(obj)/vdso64.so.dbg $(obj)/vdso64.so FORCE + $(call if_changed,vdso64sym) + +vdso64.so: $(obj)/vdso64.so.dbg + @mkdir -p $(MODLIB)/vdso + $(call cmd,vdso_install) + +vdso64_install: vdso64.so +endif + +ifdef CONFIG_VDSO32 +vdso32-as-syms = rt_sigreturn +vdso32-as-syms += getcpu +vdso32-as-syms += flush_icache +vdso32-as-syms += sys_hwprobe + +vdso32-cc-syms += hwprobe + +VDSO32_CC_FLAGS := -march=rv32g -mabi=ilp32 +VDSO32_LD_FLAGS := -melf32lriscv + +obj-as-vdso32 = $(patsubst %, %-32.o, $(vdso32-as-syms)) note-32.o +obj-as-vdso32 := $(addprefix $(obj)/, $(obj-as-vdso32)) + +obj-cc-vdso32 = $(patsubst %, %-32.o, $(vdso32-cc-syms)) +obj-cc-vdso32 := $(addprefix $(obj)/, $(obj-cc-vdso32)) + +targets += $(obj-as-vdso32) $(obj-cc-vdso32) vdso32.so vdso32.so.dbg vdso32.lds + +$(obj)/vdso32.so.dbg: $(obj)/vdso.lds $(obj-as-vdso32) $(obj-cc-vdso32) FORCE + $(call if_changed,vdso32ld) +LDFLAGS_vdso32.so.dbg = -shared -S -soname=linux-vdso32.so.1 \ + --build-id=sha1 --hash-style=both --eh-frame-hdr -# actual build commands # The DSO images are built using a special linker script # Make sure only to export the intended __vdso_xxx symbol offsets. -quiet_cmd_vdsold = VDSOLD $@ - cmd_vdsold = $(LD) $(ld_flags) -T $(filter-out FORCE,$^) -o $@.tmp && \ - $(OBJCOPY) $(patsubst %, -G __vdso_%, $(vdso-syms)) $@.tmp $@ && \ +quiet_cmd_vdso32ld = VDSO32LD $@ + cmd_vdso32ld = $(VDSO_LD) $(ld_flags) $(VDSO32_LD_FLAGS) -T $(filter-out FORCE,$^) -o $@.tmp && \ + $(OBJCOPY) $(patsubst %, -G __vdso_%, $(vdso32-as-syms) $(vdso32-cc-syms)) $@.tmp $@ && \ rm $@.tmp -# install commands for the unstripped file -quiet_cmd_vdso_install = INSTALL $@ - cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@ +# actual build commands +quiet_cmd_vdso32as = VDSO32AS $@ + cmd_vdso32as = $(VDSO_CC) $(a_flags) $(VDSO32_CC_FLAGS) -c -o $@ $< +quiet_cmd_vdso32cc = VDSO32CC $@ + cmd_vdso32cc = $(VDSO_CC) $(c_flags) $(VDSO32_CC_FLAGS) -c -o $@ $< -vdso.so: $(obj)/vdso.so.dbg +# Force dependency +$(obj)/vdso32.o: $(obj)/vdso32.so + +$(obj-as-vdso32): %-32.o: %.S FORCE + $(call if_changed_dep,vdso32as) +$(obj-cc-vdso32): %-32.o: %.c FORCE + $(call if_changed_dep,vdso32cc) + +CFLAGS_hwprobe-32.o += -fPIC + +# Generate VDSO offsets using helper script +gen-vdso32sym := $(srctree)/$(src)/gen_vdso32_offsets.sh +quiet_cmd_vdso32sym = VDSO32SYM $@ + cmd_vdso32sym = $(NM) $< | $(gen-vdso32sym) | LC_ALL=C sort > $@ + +include/generated/vdso32-offsets.h: $(obj)/vdso32.so.dbg $(obj)/vdso32.so FORCE + $(call if_changed,vdso32sym) + +vdso32.so: $(obj)/vdso32.so.dbg @mkdir -p $(MODLIB)/vdso $(call cmd,vdso_install) -vdso_install: vdso.so +vdso32_install: vdso32.so +endif diff --git a/arch/riscv/kernel/vdso/gen_vdso_offsets.sh b/arch/riscv/kernel/vdso/gen_vdso32_offsets.sh similarity index 78% rename from arch/riscv/kernel/vdso/gen_vdso_offsets.sh rename to arch/riscv/kernel/vdso/gen_vdso32_offsets.sh index c2e5613f3495..c0dee7361530 100755 --- a/arch/riscv/kernel/vdso/gen_vdso_offsets.sh +++ b/arch/riscv/kernel/vdso/gen_vdso32_offsets.sh @@ -2,4 +2,4 @@ # SPDX-License-Identifier: GPL-2.0 LC_ALL=C -sed -n -e 's/^[0]\+\(0[0-9a-fA-F]*\) . \(__vdso_[a-zA-Z0-9_]*\)$/\#define \2_offset\t0x\1/p' +sed -n -e 's/^[0]\+\(0[0-9a-fA-F]*\) . \(__vdso_[a-zA-Z0-9_]*\)$/\#define rv32\2_offset\t0x\1/p' diff --git a/arch/riscv/kernel/vdso/gen_vdso64_offsets.sh b/arch/riscv/kernel/vdso/gen_vdso64_offsets.sh new file mode 100755 index 000000000000..ac265ed49eaf --- /dev/null +++ b/arch/riscv/kernel/vdso/gen_vdso64_offsets.sh @@ -0,0 +1,5 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +LC_ALL=C +sed -n -e 's/^[0]\+\(0[0-9a-fA-F]*\) . \(__vdso_[a-zA-Z0-9_]*\)$/\#define rv64\2_offset\t0x\1/p' diff --git a/arch/riscv/kernel/vdso32.S b/arch/riscv/kernel/vdso32.S new file mode 100644 index 000000000000..9bdf3cb20ccb --- /dev/null +++ b/arch/riscv/kernel/vdso32.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define vdso64_start vdso32_start +#define vdso64_end vdso32_end + +#define __VDSO_PATH "arch/riscv/kernel/vdso/vdso32.so" + +#include "vdso64.S" diff --git a/arch/riscv/kernel/vdso/vdso.S b/arch/riscv/kernel/vdso64.S similarity index 73% rename from arch/riscv/kernel/vdso/vdso.S rename to arch/riscv/kernel/vdso64.S index 83f1c899e8d8..498b73da0dbf 100644 --- a/arch/riscv/kernel/vdso/vdso.S +++ b/arch/riscv/kernel/vdso64.S @@ -8,16 +8,16 @@ #include #ifndef __VDSO_PATH -#define __VDSO_PATH "arch/riscv/kernel/vdso/vdso.so" +#define __VDSO_PATH "arch/riscv/kernel/vdso/vdso64.so" #endif __PAGE_ALIGNED_DATA - .globl vdso_start, vdso_end + .globl vdso64_start, vdso64_end .balign PAGE_SIZE -vdso_start: +vdso64_start: .incbin __VDSO_PATH .balign PAGE_SIZE -vdso_end: +vdso64_end: .previous From patchwork Thu May 18 13:09:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC031C77B7D for ; Thu, 18 May 2023 13:11:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=u6WzUvb5q1W4/GETg2pGgbaVDZSmgNG/YOj847/0jGE=; b=v+KWGZXu8rBCi7 SVEcL4PimOehoLtzGI7JVeFdYZPiLkF+vFx7tsgNhZ8bASPrFCiTekm6r5ButKScEr4KsmE+SE5t6 UzX3zj1iS+0UW4tEcLCTw3E41gDWmJVIYaVRh1GxZKhXLmumNZZ1MsZMMiJuHNihu0gi9RxdUhV47 blU42hpRBXqGL0hLBecy1J9Wuuj9q8c9sDuKmhrA1DvoX7uCBqjIl+blnQGyMyAc7ga2D5DjdMnbh tiglYPjnUGFb0aqTaP9a56f2je5SkAA81o/xkder5oCxd11vycgiBOTTXCFRF/jSEZErvA4+DUfO5 rP8cByqfnINtvhzsahGw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzdPT-00D20t-2Y; Thu, 18 May 2023 13:11:11 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdPR-00D206-0x for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:11:10 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BD6DB64F48; Thu, 18 May 2023 13:11:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03E0CC433D2; Thu, 18 May 2023 13:10:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415468; bh=zy+LIqvorCsCX2M/f8auQf0yEixqHw8DL0243s77+7Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V33X5RSXttGRYRE6P1dvR0Tbx8vki/Mq7DswtIqCmy3ZEFQZpbBSsZILfBQdb/axC fW8gACvqQA8h24X6k4404VOWLXlYEJBBMImO5nemBEJZ/61Y+K01DoawjshCys6tPR CjMLoqcpJVur2iKg/LiMGQYwu0NzjCbEge5jadGCtxIk0hD9J9umPuYkHbaPKCDT9Y W3Ns51Fyrr8bLqReQVKpyg3/uZPPtBkd2mljV1s+MvXTJ7mR264CEc7tQT188cPrvB LeFL3fBkOwciz11llqrzSxDj2rBWzKYCoDVmv8w9JSJJWG4RoVTNoR/eGXfGTGU6TR 8QoIvXwrddaTw== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 02/22] riscv: vdso: Remove compat_vdso/ Date: Thu, 18 May 2023 09:09:53 -0400 Message-Id: <20230518131013.3366406-3-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061109_405726_A966DB6E X-CRM114-Status: GOOD ( 11.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren After unifying vdso32 & vdso64 into vdso/, we ever needn't compat_vdso directory. This commit removes the whole compat_vdso/. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/kernel/compat_vdso/.gitignore | 2 -- arch/riscv/kernel/compat_vdso/compat_vdso.S | 8 -------- arch/riscv/kernel/compat_vdso/compat_vdso.lds.S | 3 --- arch/riscv/kernel/compat_vdso/flush_icache.S | 3 --- arch/riscv/kernel/compat_vdso/gen_compat_vdso_offsets.sh | 5 ----- arch/riscv/kernel/compat_vdso/getcpu.S | 3 --- arch/riscv/kernel/compat_vdso/note.S | 3 --- arch/riscv/kernel/compat_vdso/rt_sigreturn.S | 3 --- 8 files changed, 30 deletions(-) delete mode 100644 arch/riscv/kernel/compat_vdso/.gitignore delete mode 100644 arch/riscv/kernel/compat_vdso/compat_vdso.S delete mode 100644 arch/riscv/kernel/compat_vdso/compat_vdso.lds.S delete mode 100644 arch/riscv/kernel/compat_vdso/flush_icache.S delete mode 100755 arch/riscv/kernel/compat_vdso/gen_compat_vdso_offsets.sh delete mode 100644 arch/riscv/kernel/compat_vdso/getcpu.S delete mode 100644 arch/riscv/kernel/compat_vdso/note.S delete mode 100644 arch/riscv/kernel/compat_vdso/rt_sigreturn.S diff --git a/arch/riscv/kernel/compat_vdso/.gitignore b/arch/riscv/kernel/compat_vdso/.gitignore deleted file mode 100644 index 19d83d846c1e..000000000000 --- a/arch/riscv/kernel/compat_vdso/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -compat_vdso.lds diff --git a/arch/riscv/kernel/compat_vdso/compat_vdso.S b/arch/riscv/kernel/compat_vdso/compat_vdso.S deleted file mode 100644 index ffd66237e091..000000000000 --- a/arch/riscv/kernel/compat_vdso/compat_vdso.S +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define vdso_start compat_vdso_start -#define vdso_end compat_vdso_end - -#define __VDSO_PATH "arch/riscv/kernel/compat_vdso/compat_vdso.so" - -#include "../vdso/vdso.S" diff --git a/arch/riscv/kernel/compat_vdso/compat_vdso.lds.S b/arch/riscv/kernel/compat_vdso/compat_vdso.lds.S deleted file mode 100644 index c7c9355d311e..000000000000 --- a/arch/riscv/kernel/compat_vdso/compat_vdso.lds.S +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "../vdso/vdso.lds.S" diff --git a/arch/riscv/kernel/compat_vdso/flush_icache.S b/arch/riscv/kernel/compat_vdso/flush_icache.S deleted file mode 100644 index 523dd8b96045..000000000000 --- a/arch/riscv/kernel/compat_vdso/flush_icache.S +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "../vdso/flush_icache.S" diff --git a/arch/riscv/kernel/compat_vdso/gen_compat_vdso_offsets.sh b/arch/riscv/kernel/compat_vdso/gen_compat_vdso_offsets.sh deleted file mode 100755 index 8ac070c783b3..000000000000 --- a/arch/riscv/kernel/compat_vdso/gen_compat_vdso_offsets.sh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh -# SPDX-License-Identifier: GPL-2.0 - -LC_ALL=C -sed -n -e 's/^[0]\+\(0[0-9a-fA-F]*\) . \(__vdso_[a-zA-Z0-9_]*\)$/\#define compat\2_offset\t0x\1/p' diff --git a/arch/riscv/kernel/compat_vdso/getcpu.S b/arch/riscv/kernel/compat_vdso/getcpu.S deleted file mode 100644 index 10f463efe271..000000000000 --- a/arch/riscv/kernel/compat_vdso/getcpu.S +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "../vdso/getcpu.S" diff --git a/arch/riscv/kernel/compat_vdso/note.S b/arch/riscv/kernel/compat_vdso/note.S deleted file mode 100644 index b10312907542..000000000000 --- a/arch/riscv/kernel/compat_vdso/note.S +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "../vdso/note.S" diff --git a/arch/riscv/kernel/compat_vdso/rt_sigreturn.S b/arch/riscv/kernel/compat_vdso/rt_sigreturn.S deleted file mode 100644 index 884aada4facc..000000000000 --- a/arch/riscv/kernel/compat_vdso/rt_sigreturn.S +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "../vdso/rt_sigreturn.S" From patchwork Thu May 18 13:09:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28ECCC77B7A for ; Thu, 18 May 2023 13:11:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ALzntz11FssGgvN1nXg6eny5E0AnWmcz3s8tBPHzYb4=; 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Thu, 18 May 2023 13:11:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415481; bh=MPy7nYgZxGVT5ozD/0/9eH3LbzI1BGzOCOHyLrnUh3A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MuOlaXfZwhnukyDoq8GFeTAa/Drq3uqSxKCmo+vgN7FEIdhD/9XLJW/G24yUkcpd/ cvzKGq8WgMHHnzE7/Y8348Pvjt0lPgN1OJUjeNjZRZpbERpdWTr0Ru1qK7+o2o6Ziz VWJC4noxp9Oa81Bj1I4n+gsuVBXZtOTtqy83weKpsBFAPA8bCpj3Cibl5a2vdElEQw U/PLYLPmHTXZSH/nFPhiNPhUdaJ0LUBHkYB357y5CJggKxqzQD2m9Wl8Vz46sPtJOX JpjtdOhFXSMopTAS3/vbpe0rzIb1Zu41gtDTl/hggT7rW+UC/YXh84U7M5agBYEftg tXl/hvkRSQEhQ== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 03/22] riscv: vdso: Add time-related vDSO common flow for vdso32 Date: Thu, 18 May 2023 09:09:54 -0400 Message-Id: <20230518131013.3366406-4-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061122_824415_B4388651 X-CRM114-Status: GOOD ( 15.68 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren This patch adds time-related vDSO common flow for vdso32, and it's an addition to commit: ad5d1122b82f ("riscv: use vDSO common flow to reduce the latency of the time-related functions"). Then we could reduce the latency of collecting clock information for u32ilp32 (native 32-bit userspace ecosystem), just like what we've done for u64lp64. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 4 +- arch/riscv/include/asm/vdso/gettimeofday.h | 79 ++++++++++++++++++++++ arch/riscv/include/uapi/asm/unistd.h | 1 + arch/riscv/kernel/vdso/Makefile | 39 +++++------ arch/riscv/kernel/vdso/vgettimeofday.c | 39 +++++++++-- 5 files changed, 134 insertions(+), 28 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 643884620cd6..4d4fac81390f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -75,7 +75,7 @@ config RISCV select GENERIC_PTDUMP if MMU select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD - select GENERIC_TIME_VSYSCALL if MMU && 64BIT + select GENERIC_TIME_VSYSCALL if MMU select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL @@ -103,7 +103,7 @@ config RISCV select HAVE_FUNCTION_ARG_ACCESS_API select HAVE_FUNCTION_ERROR_INJECTION select HAVE_GCC_PLUGINS - select HAVE_GENERIC_VDSO if MMU && 64BIT + select HAVE_GENERIC_VDSO if MMU select HAVE_IRQ_TIME_ACCOUNTING select HAVE_KPROBES if !XIP_KERNEL select HAVE_KPROBES_ON_FTRACE if !XIP_KERNEL diff --git a/arch/riscv/include/asm/vdso/gettimeofday.h b/arch/riscv/include/asm/vdso/gettimeofday.h index a7ae8576797b..0dcb6c5c4111 100644 --- a/arch/riscv/include/asm/vdso/gettimeofday.h +++ b/arch/riscv/include/asm/vdso/gettimeofday.h @@ -36,6 +36,7 @@ int gettimeofday_fallback(struct __kernel_old_timeval *_tv, } #endif +#if __SIZEOF_POINTER__ == 8 #ifdef __NR_clock_gettime static __always_inline long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) @@ -71,6 +72,84 @@ int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) return ret; } #endif + +#elif __SIZEOF_POINTER__ == 4 + +#define BUILD_VDSO32 1 + +#ifdef __NR_clock_gettime64 +static __always_inline +long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) +{ + register clockid_t clkid asm("a0") = _clkid; + register struct __kernel_timespec *ts asm("a1") = _ts; + register long ret asm("a0"); + register long nr asm("a7") = __NR_clock_gettime64; + + asm volatile ("ecall\n" + : "=r" (ret) + : "r"(clkid), "r"(ts), "r"(nr) + : "memory"); + + return ret; +} +#endif + +#ifdef __NR_clock_getres_time64 +static __always_inline +int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) +{ + register clockid_t clkid asm("a0") = _clkid; + register struct __kernel_timespec *ts asm("a1") = _ts; + register long ret asm("a0"); + register long nr asm("a7") = __NR_clock_getres_time64; + + asm volatile ("ecall\n" + : "=r" (ret) + : "r"(clkid), "r"(ts), "r"(nr) + : "memory"); + + return ret; +} +#endif + +#ifdef __NR_clock_gettime +static __always_inline +int clock_gettime32_fallback(clockid_t _clkid, struct old_timespec32 *_ts) +{ + register clockid_t clkid asm("a0") = _clkid; + register struct old_timespec32 *ts asm("a1") = _ts; + register long ret asm("a0"); + register long nr asm("a7") = __NR_clock_gettime; + + asm volatile ("ecall\n" + : "=r" (ret) + : "r"(clkid), "r"(ts), "r"(nr) + : "memory"); + + return ret; +} +#endif + +#ifdef __NR_clock_getres +static __always_inline +int clock_getres32_fallback(clockid_t _clkid, struct old_timespec32 *_ts) +{ + register clockid_t clkid asm("a0") = _clkid; + register struct old_timespec32 *ts asm("a1") = _ts; + register long ret asm("a0"); + register long nr asm("a7") = __NR_clock_getres; + + asm volatile ("ecall\n" + : "=r" (ret) + : "r"(clkid), "r"(ts), "r"(nr) + : "memory"); + + return ret; +} +#endif + +#endif /* __SIZEOF_POINTER__ */ #endif /* CONFIG_GENERIC_TIME_VSYSCALL */ static __always_inline u64 __arch_get_hw_counter(s32 clock_mode, diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h index 950ab3fd4409..0ee86ef907e4 100644 --- a/arch/riscv/include/uapi/asm/unistd.h +++ b/arch/riscv/include/uapi/asm/unistd.h @@ -22,6 +22,7 @@ #define __ARCH_WANT_SYS_CLONE3 #define __ARCH_WANT_MEMFD_SECRET +#define __ARCH_WANT_TIME32_SYSCALLS #include diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile index e3c3bf669c7b..42338a2c26a7 100644 --- a/arch/riscv/kernel/vdso/Makefile +++ b/arch/riscv/kernel/vdso/Makefile @@ -31,20 +31,20 @@ $(obj)/%.so: $(obj)/%.so.dbg FORCE quiet_cmd_vdso_install = INSTALL $@ cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@ -# Symbols present in the vdso -ifdef CONFIG_VDSO64 -vdso64-as-syms = rt_sigreturn -vdso64-as-syms += getcpu -vdso64-as-syms += flush_icache -vdso64-as-syms += sys_hwprobe +vdso-as-syms = rt_sigreturn +vdso-as-syms += getcpu +vdso-as-syms += flush_icache +vdso-as-syms += sys_hwprobe -vdso64-cc-syms = vgettimeofday -vdso64-cc-syms += hwprobe +vdso-cc-syms = vgettimeofday +vdso-cc-syms += hwprobe -obj-as-vdso64 = $(patsubst %, %-64.o, $(vdso64-as-syms)) note-64.o +# Symbols present in the vdso +ifdef CONFIG_VDSO64 +obj-as-vdso64 = $(patsubst %, %-64.o, $(vdso-as-syms)) note-64.o obj-as-vdso64 := $(addprefix $(obj)/, $(obj-as-vdso64)) -obj-cc-vdso64 = $(patsubst %, %-64.o, $(vdso64-cc-syms)) +obj-cc-vdso64 = $(patsubst %, %-64.o, $(vdso-cc-syms)) obj-cc-vdso64 := $(addprefix $(obj)/, $(obj-cc-vdso64)) targets += $(obj-as-vdso64) $(obj-cc-vdso64) vdso64.so vdso64.so.dbg vdso64.lds @@ -57,7 +57,7 @@ LDFLAGS_vdso64.so.dbg = -shared -S -soname=linux-vdso64.so.1 \ # Make sure only to export the intended __vdso_xxx symbol offsets. quiet_cmd_vdso64ld = VDSO64LD $@ cmd_vdso64ld = $(VDSO_LD) $(ld_flags) $(VDSO64_LD_FLAGS) -T $(filter-out FORCE,$^) -o $@.tmp && \ - $(OBJCOPY) $(patsubst %, -G __vdso_%, $(vdso64-as-syms) $(vdso64-cc-syms)) $@.tmp $@ && \ + $(OBJCOPY) $(patsubst %, -G __vdso_%, $(vdso-as-syms) $(vdso-cc-syms)) $@.tmp $@ && \ rm $@.tmp # actual build commands @@ -96,20 +96,13 @@ vdso64_install: vdso64.so endif ifdef CONFIG_VDSO32 -vdso32-as-syms = rt_sigreturn -vdso32-as-syms += getcpu -vdso32-as-syms += flush_icache -vdso32-as-syms += sys_hwprobe - -vdso32-cc-syms += hwprobe - VDSO32_CC_FLAGS := -march=rv32g -mabi=ilp32 VDSO32_LD_FLAGS := -melf32lriscv -obj-as-vdso32 = $(patsubst %, %-32.o, $(vdso32-as-syms)) note-32.o +obj-as-vdso32 = $(patsubst %, %-32.o, $(vdso-as-syms)) note-32.o obj-as-vdso32 := $(addprefix $(obj)/, $(obj-as-vdso32)) -obj-cc-vdso32 = $(patsubst %, %-32.o, $(vdso32-cc-syms)) +obj-cc-vdso32 = $(patsubst %, %-32.o, $(vdso-cc-syms)) obj-cc-vdso32 := $(addprefix $(obj)/, $(obj-cc-vdso32)) targets += $(obj-as-vdso32) $(obj-cc-vdso32) vdso32.so vdso32.so.dbg vdso32.lds @@ -123,7 +116,7 @@ LDFLAGS_vdso32.so.dbg = -shared -S -soname=linux-vdso32.so.1 \ # Make sure only to export the intended __vdso_xxx symbol offsets. quiet_cmd_vdso32ld = VDSO32LD $@ cmd_vdso32ld = $(VDSO_LD) $(ld_flags) $(VDSO32_LD_FLAGS) -T $(filter-out FORCE,$^) -o $@.tmp && \ - $(OBJCOPY) $(patsubst %, -G __vdso_%, $(vdso32-as-syms) $(vdso32-cc-syms)) $@.tmp $@ && \ + $(OBJCOPY) $(patsubst %, -G __vdso_%, $(vdso-as-syms) $(vdso-cc-syms)) $@.tmp $@ && \ rm $@.tmp # actual build commands @@ -142,6 +135,10 @@ $(obj-cc-vdso32): %-32.o: %.c FORCE CFLAGS_hwprobe-32.o += -fPIC +CFLAGS_vgettimeofday-32.o += -fPIC -include $(c-gettimeofday-y) +# Disable -pg to prevent insert call site +CFLAGS_REMOVE_vgettimeofday-32.o = $(CC_FLAGS_FTRACE) + # Generate VDSO offsets using helper script gen-vdso32sym := $(srctree)/$(src)/gen_vdso32_offsets.sh quiet_cmd_vdso32sym = VDSO32SYM $@ diff --git a/arch/riscv/kernel/vdso/vgettimeofday.c b/arch/riscv/kernel/vdso/vgettimeofday.c index cc0d80699c31..056b465eb161 100644 --- a/arch/riscv/kernel/vdso/vgettimeofday.c +++ b/arch/riscv/kernel/vdso/vgettimeofday.c @@ -9,6 +9,14 @@ #include #include +extern +int __vdso_gettimeofday(struct __kernel_old_timeval *tv, struct timezone *tz); +int __vdso_gettimeofday(struct __kernel_old_timeval *tv, struct timezone *tz) +{ + return __cvdso_gettimeofday(tv, tz); +} + +#if __SIZEOF_POINTER__ == 8 extern int __vdso_clock_gettime(clockid_t clock, struct __kernel_timespec *ts); int __vdso_clock_gettime(clockid_t clock, struct __kernel_timespec *ts) @@ -17,15 +25,36 @@ int __vdso_clock_gettime(clockid_t clock, struct __kernel_timespec *ts) } extern -int __vdso_gettimeofday(struct __kernel_old_timeval *tv, struct timezone *tz); -int __vdso_gettimeofday(struct __kernel_old_timeval *tv, struct timezone *tz) +int __vdso_clock_getres(clockid_t clock_id, struct __kernel_timespec *res); +int __vdso_clock_getres(clockid_t clock_id, struct __kernel_timespec *res) { - return __cvdso_gettimeofday(tv, tz); + return __cvdso_clock_getres(clock_id, res); +} +#elif __SIZEOF_POINTER__ == 4 +extern +int __vdso_clock_gettime(clockid_t clock, struct old_timespec32 *ts); +int __vdso_clock_gettime(clockid_t clock, struct old_timespec32 *ts) +{ + return __cvdso_clock_gettime32(clock, ts); +} + +int __vdso_clock_gettime64(clockid_t clock, struct __kernel_timespec *ts); +int __vdso_clock_gettime64(clockid_t clock, struct __kernel_timespec *ts) +{ + return __cvdso_clock_gettime(clock, ts); } extern -int __vdso_clock_getres(clockid_t clock_id, struct __kernel_timespec *res); -int __vdso_clock_getres(clockid_t clock_id, struct __kernel_timespec *res) +int __vdso_clock_getres(clockid_t clock_id, struct old_timespec32 *res); +int __vdso_clock_getres(clockid_t clock_id, struct old_timespec32 *res) +{ + return __cvdso_clock_getres_time32(clock_id, res); +} + +extern +int __vdso_clock_getres64(clockid_t clock_id, struct __kernel_timespec *res); +int __vdso_clock_getres64(clockid_t clock_id, struct __kernel_timespec *res) { return __cvdso_clock_getres(clock_id, res); } +#endif From patchwork Thu May 18 13:09:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 596E4C77B7D for ; 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Thu, 18 May 2023 13:11:36 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdPp-00D263-0G for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:11:34 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8CC1B64F4C; Thu, 18 May 2023 13:11:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B023C433D2; Thu, 18 May 2023 13:11:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415492; bh=kwYbV+xRqnM3gD5wja5IP2IYhT3BPYOFw/sxTmqeyds=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tebfDu2ciCGlWfmOzk3QjqBAf9k6FxRFj7jmur4lv4YYgmCqMwYndQMkm/TX5ALdr ahSuRZujS7dWo/DAxOKxBUAyoU2L7N5xr8A0BvnwSqYyibaEpV8BhHb94puApoRjfN 0wJpP+cKegCUiSc3U4UPwgoIzrXWQze32a23f7IDPdtkunSTAJgoYFkRL1ycW0/Isq 3t+c9hz2PtbDnszFGKOPxXjZgXL1mfQWMblibSnBovz/83Borj9U0Mf+6/2KifouyE oz7PCD3ulfIeKgtZ+BrOCR8DT4EGQCxUw0Wvzb6d8X1HWDulB2UMy5eHOeJnNkulsN fb9+hL6VaPVCA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 04/22] clocksource: riscv: s64ilp32: Use __riscv_xlen instead of CONFIG_32BIT Date: Thu, 18 May 2023 09:09:55 -0400 Message-Id: <20230518131013.3366406-5-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061133_162129_8FC27B5C X-CRM114-Status: GOOD ( 11.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren When s64ilp32 enabled, CONFIG_32BIT=y but __riscv_xlen=64. So we must use __riscv_xlen to detect real machine XLEN for CSR access. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- drivers/clocksource/timer-riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5f0f10c7e222..459a634012ce 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -37,7 +37,7 @@ static int riscv_clock_next_event(unsigned long delta, csr_set(CSR_IE, IE_TIE); if (static_branch_likely(&riscv_sstc_available)) { -#if defined(CONFIG_32BIT) +#if __riscv_xlen == 32 csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); csr_write(CSR_STIMECMPH, next_tval >> 32); #else From patchwork Thu May 18 13:09:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1A6EC77B7D for ; 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Thu, 18 May 2023 13:11:49 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdQ1-00D2AK-2A for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:11:47 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3217964F4C; Thu, 18 May 2023 13:11:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A2BDC433A8; Thu, 18 May 2023 13:11:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415504; bh=mUvKPYb9kXtM63DkJk8xrIjB0iU3kTZ7V5k0fuwWhWM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LAVh1Lb9pxkCaMxZsXlZjAaOVNnfqMWUypTw/mgPxDp9wVkFSJW6yeudTgDzuMXBW rPf1VbQ2MTu83fXUaDZGGUcG7JJZqO5GEHXzAgTcCd6/ggG6/o4OqMArG2ljWbg5Hc /xFFvQXmcLVINwx/6dxrg14W3ygTEtRFCTH3oYG4JzNw4T27EvjWN1P4B+LhXImH4k /R1yTD73cP7CCmTUFLr70LBufwduUHhgw1LNnl9tLm2vhRatVIsiITYFu2Lg6FMsrK Kmw1Cy84gm+j2XEE+84BPl7E/dTXxh2AdUGHQ5Hb9ijeSKhexzX1IHdX0ss61BODgq fn8eV3L8pojZA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 05/22] riscv: s64ilp32: Introduce xlen_t Date: Thu, 18 May 2023 09:09:56 -0400 Message-Id: <20230518131013.3366406-6-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061145_787643_55667908 X-CRM114-Status: GOOD ( 20.39 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren When s64ilp32 landed, we couldn't use CONFIG_64/32BIT to distingue XLEN data types. Because the xlen is 64, but the long & pointer is 32 for s64ilp32, and s64ilp32 is a 32BIT from the software view. So introduce a new data type - "xlen_t" and use __riscv_xlen instead of CONFIG_64/32BIT ifdef macro. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/csr.h | 58 ++++++++++-------- arch/riscv/include/asm/processor.h | 8 +-- arch/riscv/include/asm/ptrace.h | 96 +++++++++++++++--------------- arch/riscv/include/asm/timex.h | 10 ++-- arch/riscv/kernel/cpufeature.c | 4 +- arch/riscv/kernel/process.c | 4 +- arch/riscv/kernel/signal.c | 6 +- arch/riscv/kernel/traps.c | 4 +- arch/riscv/lib/memset.S | 4 +- arch/riscv/mm/fault.c | 2 +- 10 files changed, 104 insertions(+), 92 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 7c2b8cdb7b77..adc3c866d353 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -30,37 +30,41 @@ #define SR_XS_CLEAN _AC(0x00010000, UL) #define SR_XS_DIRTY _AC(0x00018000, UL) -#ifndef CONFIG_64BIT +#if __riscv_xlen == 32 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, ULL) /* FS/XS dirty */ #endif -#ifdef CONFIG_64BIT -#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ -#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ -#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ +#if __riscv_xlen == 64 +#define SR_UXL _AC(0x300000000, ULL) /* XLEN mask for U-mode */ +#define SR_UXL_32 _AC(0x100000000, ULL) /* XLEN = 32 for U-mode */ +#define SR_UXL_64 _AC(0x200000000, ULL) /* XLEN = 64 for U-mode */ #endif /* SATP flags */ -#ifndef CONFIG_64BIT +#if __riscv_xlen == 32 #define SATP_PPN _AC(0x003FFFFF, UL) #define SATP_MODE_32 _AC(0x80000000, UL) #define SATP_ASID_BITS 9 #define SATP_ASID_SHIFT 22 #define SATP_ASID_MASK _AC(0x1FF, UL) #else -#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) -#define SATP_MODE_39 _AC(0x8000000000000000, UL) -#define SATP_MODE_48 _AC(0x9000000000000000, UL) -#define SATP_MODE_57 _AC(0xa000000000000000, UL) +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, ULL) +#define SATP_MODE_39 _AC(0x8000000000000000, ULL) +#define SATP_MODE_48 _AC(0x9000000000000000, ULL) +#define SATP_MODE_57 _AC(0xa000000000000000, ULL) #define SATP_ASID_BITS 16 #define SATP_ASID_SHIFT 44 -#define SATP_ASID_MASK _AC(0xFFFF, UL) +#define SATP_ASID_MASK _AC(0xFFFF, ULL) #endif /* Exception cause high bit - is an interrupt if set */ +#if __riscv_xlen == 32 #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) +#else +#define CAUSE_IRQ_FLAG (_AC(1, ULL) << (__riscv_xlen - 1)) +#endif /* Interrupt causes (minus the high bit) */ #define IRQ_S_SOFT 1 @@ -103,8 +107,8 @@ #define PMP_L 0x80 /* HSTATUS flags */ -#ifdef CONFIG_64BIT -#define HSTATUS_VSXL _AC(0x300000000, UL) +#if __riscv_xlen == 64 +#define HSTATUS_VSXL _AC(0x300000000, ULL) #define HSTATUS_VSXL_SHIFT 32 #endif #define HSTATUS_VTSR _AC(0x00400000, UL) @@ -132,12 +136,12 @@ #define HGATP64_MODE_SHIFT 60 #define HGATP64_VMID_SHIFT 44 -#define HGATP64_VMID_MASK _AC(0x03FFF00000000000, UL) -#define HGATP64_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define HGATP64_VMID_MASK _AC(0x03FFF00000000000, ULL) +#define HGATP64_PPN _AC(0x00000FFFFFFFFFFF, ULL) #define HGATP_PAGE_SHIFT 12 -#ifdef CONFIG_64BIT +#if __riscv_xlen == 64 #define HGATP_PPN HGATP64_PPN #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT #define HGATP_VMID_MASK HGATP64_VMID_MASK @@ -342,9 +346,15 @@ #ifndef __ASSEMBLY__ +#if __riscv_xlen == 64 +typedef u64 xlen_t; +#else +typedef u32 xlen_t; +#endif + #define csr_swap(csr, val) \ ({ \ - unsigned long __v = (unsigned long)(val); \ + xlen_t __v = (xlen_t)(val); \ __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ @@ -353,7 +363,7 @@ #define csr_read(csr) \ ({ \ - register unsigned long __v; \ + register xlen_t __v; \ __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ : "=r" (__v) : \ : "memory"); \ @@ -362,7 +372,7 @@ #define csr_write(csr, val) \ ({ \ - unsigned long __v = (unsigned long)(val); \ + xlen_t __v = (xlen_t)(val); \ __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ @@ -370,7 +380,7 @@ #define csr_read_set(csr, val) \ ({ \ - unsigned long __v = (unsigned long)(val); \ + xlen_t __v = (xlen_t)(val); \ __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ @@ -379,7 +389,7 @@ #define csr_set(csr, val) \ ({ \ - unsigned long __v = (unsigned long)(val); \ + xlen_t __v = (xlen_t)(val); \ __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ @@ -387,7 +397,7 @@ #define csr_read_clear(csr, val) \ ({ \ - unsigned long __v = (unsigned long)(val); \ + xlen_t __v = (xlen_t)(val); \ __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ : "=r" (__v) : "rK" (__v) \ : "memory"); \ @@ -396,7 +406,7 @@ #define csr_clear(csr, val) \ ({ \ - unsigned long __v = (unsigned long)(val); \ + xlen_t __v = (xlen_t)(val); \ __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..829000d6de94 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -36,10 +36,10 @@ struct thread_struct { /* Callee-saved registers */ unsigned long ra; unsigned long sp; /* Kernel mode stack */ - unsigned long s[12]; /* s[0]: frame pointer */ + xlen_t s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; -}; +} __attribute__((__aligned__(sizeof(xlen_t)))); /* Whitelist the fstate from the task_struct for hardened usercopy */ static inline void arch_thread_struct_whitelist(unsigned long *offset, @@ -57,8 +57,8 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset, ((struct pt_regs *)(task_stack_page(tsk) + THREAD_SIZE \ - ALIGN(sizeof(struct pt_regs), STACK_ALIGN))) -#define KSTK_EIP(tsk) (task_pt_regs(tsk)->epc) -#define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp) +#define KSTK_EIP(tsk) (ulong)(task_pt_regs(tsk)->epc) +#define KSTK_ESP(tsk) (ulong)(task_pt_regs(tsk)->sp) /* Do necessary setup to start up a newly executed thread. */ diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h index b5b0adcc85c1..54cdeec8ee79 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -13,53 +13,53 @@ #ifndef __ASSEMBLY__ struct pt_regs { - unsigned long epc; - unsigned long ra; - unsigned long sp; - unsigned long gp; - unsigned long tp; - unsigned long t0; - unsigned long t1; - unsigned long t2; - unsigned long s0; - unsigned long s1; - unsigned long a0; - unsigned long a1; - unsigned long a2; - unsigned long a3; - unsigned long a4; - unsigned long a5; - unsigned long a6; - unsigned long a7; - unsigned long s2; - unsigned long s3; - unsigned long s4; - unsigned long s5; - unsigned long s6; - unsigned long s7; - unsigned long s8; - unsigned long s9; - unsigned long s10; - unsigned long s11; - unsigned long t3; - unsigned long t4; - unsigned long t5; - unsigned long t6; + xlen_t epc; + xlen_t ra; + xlen_t sp; + xlen_t gp; + xlen_t tp; + xlen_t t0; + xlen_t t1; + xlen_t t2; + xlen_t s0; + xlen_t s1; + xlen_t a0; + xlen_t a1; + xlen_t a2; + xlen_t a3; + xlen_t a4; + xlen_t a5; + xlen_t a6; + xlen_t a7; + xlen_t s2; + xlen_t s3; + xlen_t s4; + xlen_t s5; + xlen_t s6; + xlen_t s7; + xlen_t s8; + xlen_t s9; + xlen_t s10; + xlen_t s11; + xlen_t t3; + xlen_t t4; + xlen_t t5; + xlen_t t6; /* Supervisor/Machine CSRs */ - unsigned long status; - unsigned long badaddr; - unsigned long cause; + xlen_t status; + xlen_t badaddr; + xlen_t cause; /* a0 value before the syscall */ - unsigned long orig_a0; + xlen_t orig_a0; }; #define PTRACE_SYSEMU 0x1f #define PTRACE_SYSEMU_SINGLESTEP 0x20 -#ifdef CONFIG_64BIT -#define REG_FMT "%016lx" +#if __riscv_xlen == 64 +#define REG_FMT "%016llx" #else -#define REG_FMT "%08lx" +#define REG_FMT "%08x" #endif #define user_mode(regs) (((regs)->status & SR_PP) == 0) @@ -69,12 +69,12 @@ struct pt_regs { /* Helpers for working with the instruction pointer */ static inline unsigned long instruction_pointer(struct pt_regs *regs) { - return regs->epc; + return (unsigned long)regs->epc; } static inline void instruction_pointer_set(struct pt_regs *regs, unsigned long val) { - regs->epc = val; + regs->epc = (xlen_t)val; } #define profile_pc(regs) instruction_pointer(regs) @@ -82,40 +82,40 @@ static inline void instruction_pointer_set(struct pt_regs *regs, /* Helpers for working with the user stack pointer */ static inline unsigned long user_stack_pointer(struct pt_regs *regs) { - return regs->sp; + return (unsigned long)regs->sp; } static inline void user_stack_pointer_set(struct pt_regs *regs, unsigned long val) { - regs->sp = val; + regs->sp = (xlen_t)val; } /* Valid only for Kernel mode traps. */ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) { - return regs->sp; + return (unsigned long)regs->sp; } /* Helpers for working with the frame pointer */ static inline unsigned long frame_pointer(struct pt_regs *regs) { - return regs->s0; + return (unsigned long)regs->s0; } static inline void frame_pointer_set(struct pt_regs *regs, unsigned long val) { - regs->s0 = val; + regs->s0 = (xlen_t)val; } static inline unsigned long regs_return_value(struct pt_regs *regs) { - return regs->a0; + return (unsigned long)regs->a0; } static inline void regs_set_return_value(struct pt_regs *regs, unsigned long val) { - regs->a0 = val; + regs->a0 = (xlen_t)val; } extern int regs_query_register_offset(const char *name); diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index d6a7428f6248..b610819c7ff4 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -8,7 +8,7 @@ #include -typedef unsigned long cycles_t; +typedef xlen_t cycles_t; #ifdef CONFIG_RISCV_M_MODE @@ -62,12 +62,12 @@ static inline u32 get_cycles_hi(void) #endif /* !CONFIG_RISCV_M_MODE */ -#ifdef CONFIG_64BIT +#if __riscv_xlen == 64 static inline u64 get_cycles64(void) { return get_cycles(); } -#else /* CONFIG_64BIT */ +#else /* __riscv_xlen == 64 */ static inline u64 get_cycles64(void) { u32 hi, lo; @@ -79,12 +79,12 @@ static inline u64 get_cycles64(void) return ((u64)hi << 32) | lo; } -#endif /* CONFIG_64BIT */ +#endif /* __riscv_xlen == 64 */ #define ARCH_HAS_READ_CURRENT_TIMER static inline int read_current_timer(unsigned long *timer_val) { - *timer_val = get_cycles(); + *timer_val = (unsigned long)get_cycles(); return 0; } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 52585e088873..5de6418b7588 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -126,10 +126,10 @@ void __init riscv_fill_hwcap(void) } temp = isa; -#if IS_ENABLED(CONFIG_32BIT) +#if IS_ENABLED(CONFIG_32BIT) && !IS_ENABLED(CONFIG_ARCH_RV64ILP32) if (!strncmp(isa, "rv32", 4)) isa += 4; -#elif IS_ENABLED(CONFIG_64BIT) +#else if (!strncmp(isa, "rv64", 4)) isa += 4; #endif diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e2a060066730..ab01b51a5bb9 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -45,8 +45,8 @@ void __show_regs(struct pt_regs *regs) show_regs_print_info(KERN_DEFAULT); if (!user_mode(regs)) { - pr_cont("epc : %pS\n", (void *)regs->epc); - pr_cont(" ra : %pS\n", (void *)regs->ra); + pr_cont("epc : %pS\n", (void *)(ulong)regs->epc); + pr_cont(" ra : %pS\n", (void *)(ulong)regs->ra); } pr_cont("epc : " REG_FMT " ra : " REG_FMT " sp : " REG_FMT "\n", diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 2e365084417e..f142a9eeec36 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -109,7 +109,7 @@ SYSCALL_DEFINE0(rt_sigreturn) /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; - frame = (struct rt_sigframe __user *)regs->sp; + frame = (struct rt_sigframe __user *)kernel_stack_pointer(regs); if (!access_ok(frame, sizeof(*frame))) goto badframe; @@ -135,7 +135,9 @@ SYSCALL_DEFINE0(rt_sigreturn) pr_info_ratelimited( "%s[%d]: bad frame in %s: frame=%p pc=%p sp=%p\n", task->comm, task_pid_nr(task), __func__, - frame, (void *)regs->epc, (void *)regs->sp); + frame, + (void *)instruction_pointer(regs), + (void *)kernel_stack_pointer(regs)); } force_sig(SIGSEGV); return 0; diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8c258b78c925..efc6b649985a 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -98,7 +98,7 @@ void do_trap(struct pt_regs *regs, int signo, int code, unsigned long addr) if (show_unhandled_signals && unhandled_signal(tsk, signo) && printk_ratelimit()) { pr_info("%s[%d]: unhandled signal %d code 0x%x at 0x" REG_FMT, - tsk->comm, task_pid_nr(tsk), signo, code, addr); + tsk->comm, task_pid_nr(tsk), signo, code, (xlen_t)addr); print_vma_addr(KERN_CONT " in ", instruction_pointer(regs)); pr_cont("\n"); __show_regs(regs); @@ -236,7 +236,7 @@ void handle_break(struct pt_regs *regs) current->thread.bad_cause = regs->cause; if (user_mode(regs)) - force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->epc); + force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)instruction_pointer(regs)); #ifdef CONFIG_KGDB else if (notify_die(DIE_TRAP, "EBREAK", regs, 0, regs->cause, SIGTRAP) == NOTIFY_STOP) diff --git a/arch/riscv/lib/memset.S b/arch/riscv/lib/memset.S index 34c5360c6705..34be7bf51731 100644 --- a/arch/riscv/lib/memset.S +++ b/arch/riscv/lib/memset.S @@ -38,7 +38,7 @@ WEAK(memset) or a1, a3, a1 slli a3, a1, 16 or a1, a3, a1 -#ifdef CONFIG_64BIT +#if __riscv_xlen == 64 slli a3, a1, 32 or a1, a3, a1 #endif @@ -58,7 +58,7 @@ WEAK(memset) /* Jump into loop body */ /* Assumes 32-bit instruction lengths */ la a5, 3f -#ifdef CONFIG_64BIT +#if __riscv_xlen == 64 srli a4, a4, 1 #endif add a5, a5, a4 diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 3aba72ec1742..1b0bd0683766 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -28,7 +28,7 @@ static void die_kernel_fault(const char *msg, unsigned long addr, bust_spinlocks(1); pr_alert("Unable to handle kernel %s at virtual address " REG_FMT "\n", msg, - addr); + (xlen_t)addr); bust_spinlocks(0); die(regs, "Oops"); From patchwork Thu May 18 13:09:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DEA06C77B7A for ; Thu, 18 May 2023 13:12:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 18 May 2023 13:11:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25509C433D2; Thu, 18 May 2023 13:11:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415515; bh=H3qRrc+Swbkb9xjGRDiBZp2YLKEOjr9L7yAe3XbxQAc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PF1LX07AYPEcI1S34Swg/YAvpiv/8q+1WM0ePfVK4OiIFzXg9ryk5cdpN0hr51Y2p ji+YyEyhIpKdPWIJ1YqPhMNdE3hwVfa7gWZSTEifU5EK/QQo6amzN+jKuZRzBhYvSt OclNJkPp9AuOtK3MmSe1Dm1QBrZWW/7H/TL7xJOhKh6HvtqOUx+gDIy1I83AZpCUSF gRtVcmz/smsNoZdXJ/GvB591xYetaY0ca5qgLImxoJ+pay7S3KHQlcnFGwnDgHbOWi tCcQNQIEGCF4BC5FlLlCwFHEh37zARMkRlbPbpQYmKlvwz11rN3xqVOm0pmUAZtNIB jKlCjJMI5Bv3Q== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 06/22] irqchip: riscv: s64ilp32: Use __riscv_xlen instead of CONFIG_32BIT Date: Thu, 18 May 2023 09:09:57 -0400 Message-Id: <20230518131013.3366406-7-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061156_783578_B27DC383 X-CRM114-Status: GOOD ( 12.83 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren When s64ilp32 enabled, CONFIG_32BIT=y but __riscv_xlen=64. So we must use __riscv_xlen to detect real machine XLEN for CSR access. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- drivers/irqchip/irq-riscv-intc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 499e5f81b3fe..18f3c837e488 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -21,7 +21,7 @@ static struct irq_domain *intc_domain; static asmlinkage void riscv_intc_irq(struct pt_regs *regs) { - unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; + xlen_t cause = regs->cause & ~CAUSE_IRQ_FLAG; if (unlikely(cause >= BITS_PER_LONG)) panic("unexpected interrupt cause"); @@ -113,7 +113,7 @@ static int __init riscv_intc_init(struct device_node *node, if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) return 0; - intc_domain = irq_domain_add_linear(node, BITS_PER_LONG, + intc_domain = irq_domain_add_linear(node, __riscv_xlen, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); From patchwork Thu May 18 13:09:58 2023 Content-Type: text/plain; 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Thu, 18 May 2023 13:11:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415526; bh=2yJXkd2hwfR0ToSY6iQDYPlEkk80m0hSWx77JwFLWNM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FHiXdUubawrcsGRCSebfkII36mJn6Bezsg4mGrpfXAfcUI8FC+UTxqM0kKMt86Aij w5MZIrc8ft6FKEJJPKNUHDBPEx/bnBYOKLK0q07NGMaQ5L/t95TMQS6BfbfSdpRHSI r3cMD/7LIKmJD21+KeM0lnmwFGVLf5Qm6JUgg1czx+jn/rzlTLfjvAL/kZ4IPGHRat gJcf73V5ZGJXJnUH2nRrtJqreD3LwAhzyxGTJgbDa5v0UPb+4g2DDQKZQcpNShtL09 TXBs8g7irmjfnnEbOWpWcM0znHPzfZeg59rnaK3TnYI+BMSIKpLCPEh9htVrmP/5R4 AGAv/8A32cLtA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 07/22] riscv: s64ilp32: Add sbi support Date: Thu, 18 May 2023 09:09:58 -0400 Message-Id: <20230518131013.3366406-8-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061208_015648_632D7285 X-CRM114-Status: GOOD ( 13.88 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The sbi uses xlen as base argument elements to connect m-mode and s-mode. The previous implementation assumes sizeof(xlen_t) = sizeof(long), but the s64ilp32's are different. So modify the sbi code suitable with the s64ilp32 change. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/cpu_ops_sbi.h | 4 ++-- arch/riscv/include/asm/sbi.h | 24 ++++++++++++------------ arch/riscv/kernel/cpu_ops_sbi.c | 4 ++-- arch/riscv/kernel/sbi.c | 24 ++++++++++++------------ 4 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/riscv/include/asm/cpu_ops_sbi.h b/arch/riscv/include/asm/cpu_ops_sbi.h index d6e4665b3195..d967adad6b48 100644 --- a/arch/riscv/include/asm/cpu_ops_sbi.h +++ b/arch/riscv/include/asm/cpu_ops_sbi.h @@ -19,8 +19,8 @@ extern const struct cpu_operations cpu_ops_sbi; * @stack_ptr: A pointer to the hart specific sp */ struct sbi_hart_boot_data { - void *task_ptr; - void *stack_ptr; + xlen_t task_ptr; + xlen_t stack_ptr; }; #endif diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 945b7be249c1..d31135715f0e 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -123,16 +123,16 @@ enum sbi_ext_pmu_fid { }; union sbi_pmu_ctr_info { - unsigned long value; + xlen_t value; struct { - unsigned long csr:12; - unsigned long width:6; + xlen_t csr:12; + xlen_t width:6; #if __riscv_xlen == 32 - unsigned long reserved:13; + xlen_t reserved:13; #else - unsigned long reserved:45; + xlen_t reserved:45; #endif - unsigned long type:1; + xlen_t type:1; }; }; @@ -254,15 +254,15 @@ enum sbi_pmu_ctr_type { extern unsigned long sbi_spec_version; struct sbiret { - long error; - long value; + xlen_t error; + xlen_t value; }; void sbi_init(void); -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, - unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, - unsigned long arg5); +struct sbiret sbi_ecall(int ext, int fid, xlen_t arg0, + xlen_t arg1, xlen_t arg2, + xlen_t arg3, xlen_t arg4, + xlen_t arg5); void sbi_console_putchar(int ch); int sbi_console_getchar(void); diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c index efa0f0816634..01a1e270ec1d 100644 --- a/arch/riscv/kernel/cpu_ops_sbi.c +++ b/arch/riscv/kernel/cpu_ops_sbi.c @@ -71,8 +71,8 @@ static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) /* Make sure tidle is updated */ smp_mb(); - bdata->task_ptr = tidle; - bdata->stack_ptr = task_stack_page(tidle) + THREAD_SIZE; + bdata->task_ptr = (ulong)tidle; + bdata->stack_ptr = (ulong)task_stack_page(tidle) + THREAD_SIZE; /* Make sure boot data is updated */ smp_mb(); hsm_data = __pa(bdata); diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 5c87db8fdff2..b649562aff61 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -22,21 +22,21 @@ static int (*__sbi_rfence)(int fid, const struct cpumask *cpu_mask, unsigned long start, unsigned long size, unsigned long arg4, unsigned long arg5) __ro_after_init; -struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, - unsigned long arg1, unsigned long arg2, - unsigned long arg3, unsigned long arg4, - unsigned long arg5) +struct sbiret sbi_ecall(int ext, int fid, xlen_t arg0, + xlen_t arg1, xlen_t arg2, + xlen_t arg3, xlen_t arg4, + xlen_t arg5) { struct sbiret ret; - register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); - register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); - register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); - register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3); - register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4); - register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5); - register uintptr_t a6 asm ("a6") = (uintptr_t)(fid); - register uintptr_t a7 asm ("a7") = (uintptr_t)(ext); + register xlen_t a0 asm ("a0") = arg0; + register xlen_t a1 asm ("a1") = arg1; + register xlen_t a2 asm ("a2") = arg2; + register xlen_t a3 asm ("a3") = arg3; + register xlen_t a4 asm ("a4") = arg4; + register xlen_t a5 asm ("a5") = arg5; + register xlen_t a6 asm ("a6") = fid; + register xlen_t a7 asm ("a7") = ext; asm volatile ("ecall" : "+r" (a0), "+r" (a1) : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) From patchwork Thu May 18 13:09:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8258C77B7A for ; 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Thu, 18 May 2023 13:12:24 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdQc-00D2Od-2W for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:12:24 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5428564F52; Thu, 18 May 2023 13:12:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61FCFC433EF; Thu, 18 May 2023 13:12:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415541; bh=z5mkr//0fNawn45SMn5US81wCUZHNT6No8cwVZ30STk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dpq2AALe0mn8e3ICXMEMakWoQf7l4LZI9XJRL/KK8OthBuOAkkVBTJ2R5CWP7TUiJ Lijji9TT0GYg9fBUfTLk6wPK4WXm+jxmpEbBajfcmdzmeRiy0ygmmAsUBKmbllOfBm GnZ+bAVUV7Wyjr+nH981VRaTHsDByS7vGYmUPcEtDXWsZSvAZolKa4MH222LURagYw uPbNeSwfdDlP5bA43XtY6Onzy+BfMiZeJw1Yzm2DsAiO+M2GjYFej3rCH4OuDLXcD6 4jGrdnCY/T2Ybpkves9qxyv/jU92PgqrXB11ZASrYjazL2MnM291C7EyiNIopSXqXE IqaXJF5DKqkRA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 08/22] riscv: s64ilp32: Add asid support Date: Thu, 18 May 2023 09:09:59 -0400 Message-Id: <20230518131013.3366406-9-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061222_902112_87D226E2 X-CRM114-Status: GOOD ( 12.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The s32ilp32 uses 9 bits as asid_bits because of the xlen=32 limitation of CSR. The xlen of s64ilp32 is 64 bits in width, and the SATP CSR format is the same for Sv32, Sv39, Sv48, and Sv57. So this patch makes asid mechanism support s64ilp32 with maximum num_asids. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/mm/context.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 80ce9caba8d2..696a7ca41f55 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -20,9 +20,9 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator); -static unsigned long asid_bits; +static xlen_t asid_bits; static unsigned long num_asids; -static unsigned long asid_mask; +static xlen_t asid_mask; static atomic_long_t current_version; @@ -225,14 +225,18 @@ static inline void set_mm(struct mm_struct *mm, unsigned int cpu) static int __init asids_init(void) { - unsigned long old; + xlen_t old; /* Figure-out number of ASID bits in HW */ old = csr_read(CSR_SATP); asid_bits = old | (SATP_ASID_MASK << SATP_ASID_SHIFT); csr_write(CSR_SATP, asid_bits); asid_bits = (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK; - asid_bits = fls_long(asid_bits); +#if __riscv_xlen == 64 + asid_bits = fls64(asid_bits); +#else + asid_bits = fls(asid_bits); +#endif csr_write(CSR_SATP, old); /* @@ -265,9 +269,9 @@ static int __init asids_init(void) static_branch_enable(&use_asid_allocator); pr_info("ASID allocator using %lu bits (%lu entries)\n", - asid_bits, num_asids); + (ulong)asid_bits, num_asids); } else { - pr_info("ASID allocator disabled (%lu bits)\n", asid_bits); + pr_info("ASID allocator disabled (%lu bits)\n", (ulong)asid_bits); } return 0; From patchwork Thu May 18 13:10:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1792C77B7A for ; Thu, 18 May 2023 13:12:41 +0000 (UTC) DKIM-Signature: v=1; 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Thu, 18 May 2023 13:12:37 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 27B7464F5F; Thu, 18 May 2023 13:12:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F3BA8C433D2; Thu, 18 May 2023 13:12:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415553; bh=OdCg9R21eQviBmoMElf1uoCtA04hFkvb/xuB1wotl0I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c1NzFB+d9XO/F7FqxVDFeI5zors7BqJYtoF1hS4l/7VjpOzY1hddMiwLSALRaRyCy bYji2sLtYtbbykYoDXu9hyd9INlWbNEMJ4V1vUPYT2UHRFqoIAwf/Rzb7KlgvMbJlt JnuEaddtGzO4Sqxt2eiI90JJjsyY9TlavKrt16mnNVvcjK0aG8I6NuhwrckPen9Ufp 4mpbNjPWww4fBjdz9v7E06eXt2nDgJmGTDLGo5xBByXJGN54gfIeKqHzLM1KOBetv1 8wMnKleNvdDO3UlijO7Z7lBRtD8w4cqYoVflLtJx1rPvpRBYzx3hYdLCnsxCX1wDSS E6uqTqLzAYY2Q== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 09/22] riscv: s64ilp32: Introduce PTR_L and PTR_S Date: Thu, 18 May 2023 09:10:00 -0400 Message-Id: <20230518131013.3366406-10-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061235_716012_D039C1CD X-CRM114-Status: GOOD ( 12.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren REG_L and REG_S can't satisfy s64ilp32 situation, because its __SIZEOF_POINTER__*8 != __riscv_xlen. So we introduce new PTR_L and PTR_S macro to help head.S and entry.S deal with the pointer data type and replace all REG_L/S by PTR_L/S to fit the current algorithm in memcpy, memove, memset, strcmp, strlen and strncmp. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/asm.h | 5 +++++ arch/riscv/kernel/entry.S | 24 ++++++++++++------------ arch/riscv/kernel/head.S | 8 ++++---- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h index 114bbadaef41..1cf20027bdbd 100644 --- a/arch/riscv/include/asm/asm.h +++ b/arch/riscv/include/asm/asm.h @@ -38,6 +38,7 @@ #define RISCV_SZPTR "8" #define RISCV_LGPTR "3" #endif +#define __PTR_SEL(a, b) __ASM_STR(a) #elif __SIZEOF_POINTER__ == 4 #ifdef __ASSEMBLY__ #define RISCV_PTR .word @@ -48,10 +49,14 @@ #define RISCV_SZPTR "4" #define RISCV_LGPTR "2" #endif +#define __PTR_SEL(a, b) __ASM_STR(b) #else #error "Unexpected __SIZEOF_POINTER__" #endif +#define PTR_L __PTR_SEL(ld, lw) +#define PTR_S __PTR_SEL(sd, sw) + #if (__SIZEOF_INT__ == 4) #define RISCV_INT __ASM_STR(.word) #define RISCV_SZINT __ASM_STR(4) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 3fbb100bc9e4..9d8a94fec097 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -25,19 +25,19 @@ SYM_CODE_START(handle_exception) _restore_kernel_tpsp: csrr tp, CSR_SCRATCH - REG_S sp, TASK_TI_KERNEL_SP(tp) + PTR_S sp, TASK_TI_KERNEL_SP(tp) #ifdef CONFIG_VMAP_STACK addi sp, sp, -(PT_SIZE_ON_STACK) srli sp, sp, THREAD_SHIFT andi sp, sp, 0x1 bnez sp, handle_kernel_stack_overflow - REG_L sp, TASK_TI_KERNEL_SP(tp) + PTR_L sp, TASK_TI_KERNEL_SP(tp) #endif _save_context: - REG_S sp, TASK_TI_USER_SP(tp) - REG_L sp, TASK_TI_KERNEL_SP(tp) + PTR_S sp, TASK_TI_USER_SP(tp) + PTR_L sp, TASK_TI_KERNEL_SP(tp) addi sp, sp, -(PT_SIZE_ON_STACK) REG_S x1, PT_RA(sp) REG_S x3, PT_GP(sp) @@ -53,7 +53,7 @@ _save_context: */ li t0, SR_SUM | SR_FS - REG_L s0, TASK_TI_USER_SP(tp) + PTR_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 csrr s2, CSR_EPC csrr s3, CSR_TVAL @@ -96,7 +96,7 @@ _save_context: add t0, t1, t0 /* Check if exception code lies within bounds */ bgeu t0, t2, 1f - REG_L t0, 0(t0) + PTR_L t0, 0(t0) jr t0 1: tail do_trap_unknown @@ -121,7 +121,7 @@ SYM_CODE_START_NOALIGN(ret_from_exception) /* Save unwound kernel stack pointer in thread_info */ addi s0, sp, PT_SIZE_ON_STACK - REG_S s0, TASK_TI_KERNEL_SP(tp) + PTR_S s0, TASK_TI_KERNEL_SP(tp) /* * Save TP into the scratch register , so we can find the kernel data @@ -239,7 +239,7 @@ restore_caller_reg: REG_S x5, PT_T0(sp) save_from_x6_to_x31 - REG_L s0, TASK_TI_KERNEL_SP(tp) + PTR_L s0, TASK_TI_KERNEL_SP(tp) csrr s1, CSR_STATUS csrr s2, CSR_EPC csrr s3, CSR_TVAL @@ -283,8 +283,8 @@ SYM_FUNC_START(__switch_to) li a4, TASK_THREAD_RA add a3, a0, a4 add a4, a1, a4 - REG_S ra, TASK_THREAD_RA_RA(a3) - REG_S sp, TASK_THREAD_SP_RA(a3) + PTR_S ra, TASK_THREAD_RA_RA(a3) + PTR_S sp, TASK_THREAD_SP_RA(a3) REG_S s0, TASK_THREAD_S0_RA(a3) REG_S s1, TASK_THREAD_S1_RA(a3) REG_S s2, TASK_THREAD_S2_RA(a3) @@ -298,8 +298,8 @@ SYM_FUNC_START(__switch_to) REG_S s10, TASK_THREAD_S10_RA(a3) REG_S s11, TASK_THREAD_S11_RA(a3) /* Restore context from next->thread */ - REG_L ra, TASK_THREAD_RA_RA(a4) - REG_L sp, TASK_THREAD_SP_RA(a4) + PTR_L ra, TASK_THREAD_RA_RA(a4) + PTR_L sp, TASK_THREAD_SP_RA(a4) REG_L s0, TASK_THREAD_S0_RA(a4) REG_L s1, TASK_THREAD_S1_RA(a4) REG_L s2, TASK_THREAD_S2_RA(a4) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4bf6c449d78b..27d134ee754f 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -42,7 +42,7 @@ ENTRY(_start) /* Image load offset (0MB) from start of RAM for M-mode */ .dword 0 #else -#if __riscv_xlen == 64 +#ifdef CONFIG_64BIT /* Image load offset(2MB) from start of RAM */ .dword 0x200000 #else @@ -75,7 +75,7 @@ relocate_enable_mmu: /* Relocate return address */ la a1, kernel_map XIP_FIXUP_OFFSET a1 - REG_L a1, KERNEL_MAP_VIRT_ADDR(a1) + PTR_L a1, KERNEL_MAP_VIRT_ADDR(a1) la a2, _start sub a1, a1, a2 add ra, ra, a1 @@ -346,8 +346,8 @@ clear_bss_done: */ .Lwait_for_cpu_up: /* FIXME: We should WFI to save some energy here. */ - REG_L sp, (a1) - REG_L tp, (a2) + PTR_L sp, (a1) + PTR_L tp, (a2) beqz sp, .Lwait_for_cpu_up beqz tp, .Lwait_for_cpu_up fence From patchwork Thu May 18 13:10:01 2023 Content-Type: text/plain; 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Thu, 18 May 2023 13:12:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415563; bh=K6yzC4DxTrto6TIigKOf2HSRiKwOssJzxGPb5qsG5uk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oXJAwAIukQyUqKfJu7LCrvsuxh/2lr7uu5dOljJseAAxlywm7yBd0VVked85CNfjq IuuSjQ3DcQgJRFeh45p3dQgYfRpVz2tNQolXVKu9rK0sZ2MgE0882A/1QHYou7eh07 4XNgn+8fsLlgrSHNcB3MocDEWrzhpRblVSC8K2jrSn0CbS7jrAdUasfwC32+By7tc0 7f/1X9uwq+ZwYRbv8qHiTjboPIJEija8peqdWLq59oc44Q9Ca+TaUuK8KWZYNnf5Hd dl7nEC2nrfl05jQzwP2H1hXitACGVH5WlldFt/AFHIws3dqz6Xaxb08Lxc3x8D3btO j29hJzbTHERLA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 10/22] riscv: s64ilp32: Enable user space runtime environment Date: Thu, 18 May 2023 09:10:01 -0400 Message-Id: <20230518131013.3366406-11-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061245_049206_3BFF82F4 X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren RV64ILP32 uses the same setting from COMPAT mode for the user space runtime environment. They all have the same 2GB TASK_SIZE. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/csr.h | 2 -- arch/riscv/include/asm/pgtable.h | 8 +++++++- arch/riscv/kernel/process.c | 4 +++- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index adc3c866d353..7558e0808af4 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -36,11 +36,9 @@ #define SR_SD _AC(0x8000000000000000, ULL) /* FS/XS dirty */ #endif -#if __riscv_xlen == 64 #define SR_UXL _AC(0x300000000, ULL) /* XLEN mask for U-mode */ #define SR_UXL_32 _AC(0x100000000, ULL) /* XLEN = 32 for U-mode */ #define SR_UXL_64 _AC(0x200000000, ULL) /* XLEN = 64 for U-mode */ -#endif /* SATP flags */ #if __riscv_xlen == 32 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 3303fc03d724..d7b8eff0ade9 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -830,26 +830,32 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) * - 0x9fc00000 (~2.5GB) for RV32. * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu + * - 0x80000000 ( 2GB) for COMPAT and RV64ILP32 * * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V * Instruction Set Manual Volume II: Privileged Architecture" states that * "load and store effective addresses, which are 64bits, must have bits * 63–48 all equal to bit 47, or else a page-fault exception will occur." */ +#define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) + #ifdef CONFIG_64BIT #define TASK_SIZE_64 (PGDIR_SIZE * PTRS_PER_PGD / 2) #define TASK_SIZE_MIN (PGDIR_SIZE_L3 * PTRS_PER_PGD / 2) #ifdef CONFIG_COMPAT -#define TASK_SIZE_32 (_AC(0x80000000, UL) - PAGE_SIZE) #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ TASK_SIZE_32 : TASK_SIZE_64) #else #define TASK_SIZE TASK_SIZE_64 #endif +#else +#ifdef CONFIG_ARCH_RV64ILP32 +#define TASK_SIZE TASK_SIZE_32 #else #define TASK_SIZE FIXADDR_START +#endif #define TASK_SIZE_MIN TASK_SIZE #endif diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index ab01b51a5bb9..e033dbe5b5eb 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -125,13 +125,15 @@ void start_thread(struct pt_regs *regs, unsigned long pc, regs->epc = pc; regs->sp = sp; -#ifdef CONFIG_64BIT regs->status &= ~SR_UXL; +#ifdef CONFIG_64BIT if (is_compat_task()) regs->status |= SR_UXL_32; else regs->status |= SR_UXL_64; +#else + regs->status |= SR_UXL_32; #endif } From patchwork Thu May 18 13:10:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F9DDC7EE2C for ; Thu, 18 May 2023 13:13:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 18 May 2023 13:12:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 790E8C433A7; Thu, 18 May 2023 13:12:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415575; bh=gcDd0R4XsxsPBucDmYK1iap8GL8ZX5NOiXczxwUZldM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Uu7DJ5RUzqXpTaSuArwglr0rWJYmKTwNtwf/L5azEkL3TnZGpmnZn3fJXUSHUmWpZ dJVivDkIzOHwZOSDa13HbwD6EBl2CPnbpPqmOKR666K2piHTT4NtNULOC3f32AASrE IL7+haD4mgaXB9yLIiarp0uMJAmejmJYqyIEfNMIJgLsVblo4fwUNFeiEu5O1OOvFI OQ4KfeHqtKP5n99HlbyH3fGyXKQJw1mYJbnoFSIXe4fGIsBdqj5OzyqYlrbPjBTpYk /Rv9fPyUwOKT/FJbwRM9rtywAfkUqR3vXa6cu6tZ9IYe6pQ/ThCT2LtfDtqAGmv0ZV E+dV50MoDYR8Q== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 11/22] riscv: s64ilp32: Add ebpf jit support Date: Thu, 18 May 2023 09:10:02 -0400 Message-Id: <20230518131013.3366406-12-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061256_937953_8A0E0EB2 X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The s64ilp32 uses the rv64 ISA instruction set, not the rv32 ISA. So bpf_jit_comp32.c can't be used for s64ilp32, and we use bpf_jit_comp64.c instead. This patch makes s64ilp32 ebpf jit correct and improves the performance because bpf_jit_comp32.c has significant gaps in mapping ebpf 64-bit ISA. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/extable.h | 2 +- arch/riscv/net/Makefile | 6 +++--- arch/riscv/net/bpf_jit_comp64.c | 10 +++++----- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/include/asm/extable.h b/arch/riscv/include/asm/extable.h index 512012d193dc..3ad79a7989e2 100644 --- a/arch/riscv/include/asm/extable.h +++ b/arch/riscv/include/asm/extable.h @@ -34,7 +34,7 @@ do { \ bool fixup_exception(struct pt_regs *regs); -#if defined(CONFIG_BPF_JIT) && defined(CONFIG_ARCH_RV64I) +#if defined(CONFIG_BPF_JIT) && !defined(CONFIG_ARCH_RV32I) bool ex_handler_bpf(const struct exception_table_entry *ex, struct pt_regs *regs); #else static inline bool diff --git a/arch/riscv/net/Makefile b/arch/riscv/net/Makefile index 9a1e5f0a94e5..907edce21acc 100644 --- a/arch/riscv/net/Makefile +++ b/arch/riscv/net/Makefile @@ -2,8 +2,8 @@ obj-$(CONFIG_BPF_JIT) += bpf_jit_core.o -ifeq ($(CONFIG_ARCH_RV64I),y) - obj-$(CONFIG_BPF_JIT) += bpf_jit_comp64.o -else +ifeq ($(CONFIG_ARCH_RV32I),y) obj-$(CONFIG_BPF_JIT) += bpf_jit_comp32.o +else + obj-$(CONFIG_BPF_JIT) += bpf_jit_comp64.o endif diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c index f5a668736c79..5a65cd01c73c 100644 --- a/arch/riscv/net/bpf_jit_comp64.c +++ b/arch/riscv/net/bpf_jit_comp64.c @@ -125,7 +125,7 @@ static u8 rv_tail_call_reg(struct rv_jit_context *ctx) static bool is_32b_int(s64 val) { - return -(1L << 31) <= val && val < (1L << 31); + return -(1LL << 31) <= val && val < (1LL << 31); } static bool in_auipc_jalr_range(s64 val) @@ -134,15 +134,15 @@ static bool in_auipc_jalr_range(s64 val) * auipc+jalr can reach any signed PC-relative offset in the range * [-2^31 - 2^11, 2^31 - 2^11). */ - return (-(1L << 31) - (1L << 11)) <= val && - val < ((1L << 31) - (1L << 11)); + return (-(1LL << 31) - (1LL << 11)) <= val && + val < ((1LL << 31) - (1LL << 11)); } /* Emit fixed-length instructions for address */ static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx) { - u64 ip = (u64)(ctx->insns + ctx->ninsns); - s64 off = addr - ip; + ulong ip = (ulong)(ctx->insns + ctx->ninsns); + s64 off = (ulong)addr - ip; s64 upper = (off + (1 << 11)) >> 12; s64 lower = off & 0xfff; From patchwork Thu May 18 13:10:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2C94C77B7A for ; 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And s64ilp32 is an ELF32 based the same as s32ilp32. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/uapi/asm/elf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index d696d6610231..962e8ec8fe05 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -24,7 +24,7 @@ typedef __u64 elf_fpreg_t; typedef union __riscv_fp_state elf_fpregset_t; #define ELF_NFPREG (sizeof(struct __riscv_d_ext_state) / sizeof(elf_fpreg_t)) -#if __riscv_xlen == 64 +#if __SIZEOF_POINTER__ == 8 #define ELF_RISCV_R_SYM(r_info) ELF64_R_SYM(r_info) #define ELF_RISCV_R_TYPE(r_info) ELF64_R_TYPE(r_info) #else From patchwork Thu May 18 13:10:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D652BC77B7A for ; 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Thu, 18 May 2023 13:13:20 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdRV-00D2ke-1a for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:13:20 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0AD3064F36; Thu, 18 May 2023 13:13:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3FA3FC4339B; Thu, 18 May 2023 13:13:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415596; bh=it/txvlY5/L57R5itWfhNoNKfONs7t6egYUyVObkMZY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fu30wSyFsEk4AzAWQrWkefaN5GBStqjKJ+S3xJm90Aj9gpTam01WCSkm9IRyy3BeU irjDzBzWYaP/ZaTR+BOle+q9IC1eZEe4KkuJGTFwao++OZpA53GT9++zVzUKGxYRzL zlFgocF4KScOb7vkpUKs/keoHoihtjDWB2KZ3DL6Arauk6NJfUAtiDM+tk9Anb680x PdThj9dHO3hw/y+j+J+YofQk9cU40VP3vHXSB8JoP7Xqf3yn6z56kO/AVyGmVVCY9c sTXbVULljhjm63Bq21tX80E+oQaInLrpwCtOin5JGfYI/Nl7MUMUqpyWjETf7jBV/k VZdzOywzG2uAw== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 13/22] riscv: s64ilp32: Add ARCH RV64 ILP32 compiling framework Date: Thu, 18 May 2023 09:10:04 -0400 Message-Id: <20230518131013.3366406-14-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061317_576013_ACDE53A1 X-CRM114-Status: GOOD ( 10.93 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Just the same as ARCH_RV64I & ARCH_RV32I, add ARCH_RV64ILP32 config for s64ilp32 and turn on the s64ilp32 compile switch in the arch/riscv/Makefile. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 6 ++++++ arch/riscv/Makefile | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4d4fac81390f..d824fcf3cc1c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -300,6 +300,12 @@ config ARCH_RV64I select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 select SWIOTLB if MMU +config ARCH_RV64ILP32 + bool "RV64ILP32" + depends on NONPORTABLE + select 32BIT + select MMU + endchoice # We must be able to map all physical memory into the kernel, but the compiler diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index dafe958c4217..d47ba6b09b41 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -57,6 +57,7 @@ endif # ISA string setting riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima +riscv-march-$(CONFIG_ARCH_RV64ILP32) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c @@ -107,7 +108,11 @@ stack_protector_prepare: prepare0 endif # arch specific predefines for sparse +ifeq ($(CONFIG_ARCH_RV64ILP32),y) +CHECKFLAGS += -D__riscv +else CHECKFLAGS += -D__riscv -D__riscv_xlen=$(BITS) +endif # Default target when executing plain make boot := arch/riscv/boot From patchwork Thu May 18 13:10:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 464C7C77B7A for ; Thu, 18 May 2023 13:13:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=N4DNGSiHDhAHnD7JyYDq1HMYIqMs0ZrFI4k+TTymjs8=; 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Thu, 18 May 2023 13:13:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415606; bh=loRMXj/Jtry2vTMuauCwislja/wKPX3g/6GWiON8UaY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FMf3iV5NkSovwuZFZhmG8wW/MPKahKbqdP5Dz/Z+o3EXnXIfegc2QlXPk7bzgeN2l DJgsF9iOo0D2T7AzHweeXKvY6bDppptTPFktLCXt7aFdVBVeume3q2a4ZCkftoLbWn QCYBP8Y11fDgTty+VzA/r9+yC2d+9rSavL9eG4KhUA2s+Cp/RIE62txAh8q7wB/lej H1ku9o7kheYQajxN7Nt8ZGB7nXuO8xJXUuArCmlTgqizjEdvSTb+cEQ3SMX/1OKQyF 0oVij/BuCiRQBsVS5BlcSISiG4TOPfyEwGdojb6e6KesfoMdxCLeFbGjSK730Hl2w3 ze4z32o3tXTJQ== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 14/22] riscv: s64ilp32: Add MMU_SV39 mode support for 32BIT Date: Thu, 18 May 2023 09:10:05 -0400 Message-Id: <20230518131013.3366406-15-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061327_696697_BC939968 X-CRM114-Status: GOOD ( 24.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren There is no MMU_SV32 support in xlen=64 ISA generally, but s64ilp32 selects 32BIT, which uses MMU_SV32 default. This commit enables MMU_SV39 for 32BIT to satisfy the 4GB mapping requirement. The Sv39 is the mandatory MMU mode in RVA20S64 and RVA22S64, so we needn't care about Sv48 & Sv57. We use duplicate remapping to solve the address sign extension problem from the compiler. Make the address of 0xffffffff80000000 equal to 0x80000000 by pg_dir[2] = pg_dir[510] and pg_dir[3] = pg_dir[511] of the page table. Why didn't we prevent address sign extension in the compiler? - Additional zero extension reduces the performance - Prevent complex and unnecessary work for compiler guys. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 10 ++++++- arch/riscv/include/asm/page.h | 24 ++++++++++++----- arch/riscv/include/asm/pgtable-64.h | 42 ++++++++++++++--------------- arch/riscv/include/asm/pgtable.h | 18 ++++++++----- arch/riscv/kernel/cpu.c | 4 +-- arch/riscv/mm/fault.c | 11 ++++++++ arch/riscv/mm/init.c | 29 ++++++++++++++++---- 7 files changed, 96 insertions(+), 42 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d824fcf3cc1c..9c458496ec3a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -233,7 +233,7 @@ config FIX_EARLYCON_MEM config PGTABLE_LEVELS int - default 5 if 64BIT + default 5 if !MMU_SV32 default 2 config LOCKDEP_SUPPORT @@ -293,6 +293,8 @@ config ARCH_RV32I select GENERIC_LIB_ASHRDI3 select GENERIC_LIB_LSHRDI3 select GENERIC_LIB_UCMPDI2 + select MMU + select MMU_SV32 config ARCH_RV64I bool "RV64I" @@ -531,6 +533,12 @@ config FPU If you don't know what to do here, say Y. +config MMU_SV32 + bool "MMU using Sv32 mode" + depends on ARCH_RV32I + help + Say N here if you have a 64-bit processor without satp-sv32 mode support. + endmenu # "Platform type" menu "Kernel features" diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index b55ba20903ec..7c535e88cf91 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -61,16 +61,28 @@ void clear_page(void *page); /* Page Global Directory entry */ typedef struct { - unsigned long pgd; +#ifndef CONFIG_MMU_SV32 + u64 pgd; +#else + u32 pgd; +#endif } pgd_t; /* Page Table entry */ typedef struct { - unsigned long pte; +#ifndef CONFIG_MMU_SV32 + u64 pte; +#else + u32 pte; +#endif } pte_t; typedef struct { - unsigned long pgprot; +#ifndef CONFIG_MMU_SV32 + u64 pgprot; +#else + u32 pgprot; +#endif } pgprot_t; typedef struct page *pgtable_t; @@ -83,10 +95,10 @@ typedef struct page *pgtable_t; #define __pgd(x) ((pgd_t) { (x) }) #define __pgprot(x) ((pgprot_t) { (x) }) -#ifdef CONFIG_64BIT -#define PTE_FMT "%016lx" +#ifndef CONFIG_MMU_SV32 +#define PTE_FMT "%016llx" #else -#define PTE_FMT "%08lx" +#define PTE_FMT "%08x" #endif #ifdef CONFIG_64BIT diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index 7a5097202e15..3da589de28a0 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -45,7 +45,7 @@ extern bool pgtable_l5_enabled; /* Page 4th Directory entry */ typedef struct { - unsigned long p4d; + u64 p4d; } p4d_t; #define p4d_val(x) ((x).p4d) @@ -54,7 +54,7 @@ typedef struct { /* Page Upper Directory entry */ typedef struct { - unsigned long pud; + u64 pud; } pud_t; #define pud_val(x) ((x).pud) @@ -63,7 +63,7 @@ typedef struct { /* Page Middle Directory entry */ typedef struct { - unsigned long pmd; + u64 pmd; } pmd_t; #define pmd_val(x) ((x).pmd) @@ -76,7 +76,7 @@ typedef struct { * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 * N MT RSV PFN reserved for SW D A G U X W R V */ -#define _PAGE_PFN_MASK GENMASK(53, 10) +#define _PAGE_PFN_MASK GENMASK_ULL(53, 10) /* * [63] Svnapot definitions: @@ -120,8 +120,8 @@ enum napot_cont_order { * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory * 11 - Rsvd Reserved for future standard use */ -#define _PAGE_NOCACHE_SVPBMT (1UL << 61) -#define _PAGE_IO_SVPBMT (1UL << 62) +#define _PAGE_NOCACHE_SVPBMT (1ULL << 61) +#define _PAGE_IO_SVPBMT (1ULL << 62) #define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT) /* @@ -131,10 +131,10 @@ enum napot_cont_order { * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable * 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable */ -#define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60)) -#define _PAGE_NOCACHE_THEAD 0UL -#define _PAGE_IO_THEAD (1UL << 63) -#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59)) +#define _PAGE_PMA_THEAD ((1ULL << 62) | (1ULL << 61) | (1ULL << 60)) +#define _PAGE_NOCACHE_THEAD 0ULL +#define _PAGE_IO_THEAD (1ULL << 63) +#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1ULL << 59)) static inline u64 riscv_page_mtmask(void) { @@ -165,7 +165,7 @@ static inline u64 riscv_page_io(void) #define _PAGE_MTMASK riscv_page_mtmask() /* Set of bits to preserve across pte_modify() */ -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ +#define _PAGE_CHG_MASK (~(u64)(_PAGE_PRESENT | _PAGE_READ | \ _PAGE_WRITE | _PAGE_EXEC | \ _PAGE_USER | _PAGE_GLOBAL | \ _PAGE_MTMASK)) @@ -206,12 +206,12 @@ static inline void pud_clear(pud_t *pudp) set_pud(pudp, __pud(0)); } -static inline pud_t pfn_pud(unsigned long pfn, pgprot_t prot) +static inline pud_t pfn_pud(u64 pfn, pgprot_t prot) { return __pud((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); } -static inline unsigned long _pud_pfn(pud_t pud) +static inline u64 _pud_pfn(pud_t pud) { return __page_val_to_pfn(pud_val(pud)); } @@ -246,16 +246,16 @@ static inline bool mm_pud_folded(struct mm_struct *mm) #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) -static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot) +static inline pmd_t pfn_pmd(u64 pfn, pgprot_t prot) { - unsigned long prot_val = pgprot_val(prot); + u64 prot_val = pgprot_val(prot); ALT_THEAD_PMA(prot_val); return __pmd((pfn << _PAGE_PFN_SHIFT) | prot_val); } -static inline unsigned long _pmd_pfn(pmd_t pmd) +static inline u64 _pmd_pfn(pmd_t pmd) { return __page_val_to_pfn(pmd_val(pmd)); } @@ -263,13 +263,13 @@ static inline unsigned long _pmd_pfn(pmd_t pmd) #define mk_pmd(page, prot) pfn_pmd(page_to_pfn(page), prot) #define pmd_ERROR(e) \ - pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) + pr_err("%s:%d: bad pmd " PTE_FMT ".\n", __FILE__, __LINE__, pmd_val(e)) #define pud_ERROR(e) \ - pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e)) + pr_err("%s:%d: bad pud " PTE_FMT ".\n", __FILE__, __LINE__, pud_val(e)) #define p4d_ERROR(e) \ - pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e)) + pr_err("%s:%d: bad p4d " PTE_FMT ".\n", __FILE__, __LINE__, p4d_val(e)) static inline void set_p4d(p4d_t *p4dp, p4d_t p4d) { @@ -309,12 +309,12 @@ static inline void p4d_clear(p4d_t *p4d) set_p4d(p4d, __p4d(0)); } -static inline p4d_t pfn_p4d(unsigned long pfn, pgprot_t prot) +static inline p4d_t pfn_p4d(u64 pfn, pgprot_t prot) { return __p4d((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); } -static inline unsigned long _p4d_pfn(p4d_t p4d) +static inline u64 _p4d_pfn(p4d_t p4d) { return __page_val_to_pfn(p4d_val(p4d)); } diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index d7b8eff0ade9..c5e915f21354 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -34,7 +34,11 @@ * Half of the kernel address space (1/4 of the entries of the page global * directory) is for the direct mapping. */ +#if IS_ENABLED(CONFIG_ARCH_RV64ILP32) && !IS_ENABLED(CONFIG_MMU_SV32) +#define KERN_VIRT_SIZE (PTRS_PER_PGD * PMD_SIZE) +#else #define KERN_VIRT_SIZE ((PTRS_PER_PGD / 2 * PGDIR_SIZE) / 2) +#endif #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) #define VMALLOC_END PAGE_OFFSET @@ -86,11 +90,7 @@ #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) #define FIXADDR_TOP PCI_IO_START -#ifdef CONFIG_64BIT #define FIXADDR_SIZE PMD_SIZE -#else -#define FIXADDR_SIZE PGDIR_SIZE -#endif #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) #endif @@ -110,11 +110,11 @@ #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) -#ifdef CONFIG_64BIT +#ifndef CONFIG_MMU_SV32 #include #else #include -#endif /* CONFIG_64BIT */ +#endif /* !CONFIG_MMU_SV32 */ #include @@ -524,7 +524,11 @@ static inline int ptep_set_access_flags(struct vm_area_struct *vma, static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long address, pte_t *ptep) { +#ifndef CONFIG_MMU_SV32 + pte_t pte = __pte(atomic64_xchg((atomic64_t *)ptep, 0)); +#else pte_t pte = __pte(atomic_long_xchg((atomic_long_t *)ptep, 0)); +#endif page_table_check_pte_clear(mm, address, pte); @@ -538,7 +542,7 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, { if (!pte_young(*ptep)) return 0; - return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep)); + return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, (unsigned long *)&pte_val(*ptep)); } #define __HAVE_ARCH_PTEP_SET_WRPROTECT diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3df38052dcbd..1c8d880a5c7e 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -241,9 +241,9 @@ static void print_mmu(struct seq_file *f) char sv_type[16]; #ifdef CONFIG_MMU -#if defined(CONFIG_32BIT) +#if defined(CONFIG_MMU_SV32) strncpy(sv_type, "sv32", 5); -#elif defined(CONFIG_64BIT) +#else if (pgtable_l5_enabled) strncpy(sv_type, "sv57", 5); else if (pgtable_l4_enabled) diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c index 1b0bd0683766..56eae0deefd2 100644 --- a/arch/riscv/mm/fault.c +++ b/arch/riscv/mm/fault.c @@ -131,7 +131,18 @@ static inline void vmalloc_fault(struct pt_regs *regs, int code, unsigned long a no_context(regs, addr); return; } +#if !IS_ENABLED(CONFIG_MMU_SV32) && IS_ENABLED(CONFIG_ARCH_RV64ILP32) + /* + * The pg_dir[2,510,3,511] has been set during early + * boot, so we only make a check here. + */ + if (pgd_val(*pgd) != pgd_val(*pgd_k)) { + no_context(regs, addr); + return; + } +#else set_pgd(pgd, *pgd_k); +#endif p4d_k = p4d_offset(pgd_k, addr); if (!p4d_present(*p4d_k)) { diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index bce899b180cd..3ee5b80affce 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -43,8 +43,12 @@ EXPORT_SYMBOL(kernel_map); #ifdef CONFIG_64BIT u64 satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39; #else +#ifndef CONFIG_MMU_SV32 +u64 satp_mode __ro_after_init = SATP_MODE_39; +#else u64 satp_mode __ro_after_init = SATP_MODE_32; #endif +#endif EXPORT_SYMBOL(satp_mode); bool pgtable_l4_enabled = IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_XIP_KERNEL); @@ -60,7 +64,12 @@ unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)] EXPORT_SYMBOL(empty_zero_page); extern char _start[]; +#if IS_ENABLED(CONFIG_ARCH_RV64ILP32) && !IS_ENABLED(CONFIG_MMU_SV32) +#define DTB_EARLY_BASE_VA PGDIR_SIZE +#else #define DTB_EARLY_BASE_VA (ADDRESS_SPACE_END - (PTRS_PER_PGD / 2 * PGDIR_SIZE) + 1) +#endif + void *_dtb_early_va __initdata; uintptr_t _dtb_early_pa __initdata; @@ -656,16 +665,26 @@ void __init create_pgd_mapping(pgd_t *pgdp, pgd_next_t *nextp; phys_addr_t next_phys; uintptr_t pgd_idx = pgd_index(va); +#if !IS_ENABLED(CONFIG_MMU_SV32) && IS_ENABLED(CONFIG_ARCH_RV64ILP32) + uintptr_t pgd_idh = pgd_index(sign_extend64((u64)va, 31)); +#endif if (sz == PGDIR_SIZE) { - if (pgd_val(pgdp[pgd_idx]) == 0) + if (pgd_val(pgdp[pgd_idx]) == 0) { pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(pa), prot); +#if !IS_ENABLED(CONFIG_MMU_SV32) && IS_ENABLED(CONFIG_ARCH_RV64ILP32) + pgdp[pgd_idh] = pfn_pgd(PFN_DOWN(pa), prot); +#endif + } return; } if (pgd_val(pgdp[pgd_idx]) == 0) { next_phys = alloc_pgd_next(va); pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); +#if !IS_ENABLED(CONFIG_MMU_SV32) && IS_ENABLED(CONFIG_ARCH_RV64ILP32) + pgdp[pgd_idh] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); +#endif nextp = get_pgd_next_virt(next_phys); memset(nextp, 0, PAGE_SIZE); } else { @@ -918,9 +937,9 @@ static void __init create_fdt_early_page_table(pgd_t *pgdir, uintptr_t dtb_pa) uintptr_t pa = dtb_pa & ~(PMD_SIZE - 1); create_pgd_mapping(early_pg_dir, DTB_EARLY_BASE_VA, - IS_ENABLED(CONFIG_64BIT) ? early_dtb_pgd_next : pa, + !IS_ENABLED(CONFIG_MMU_SV32) ? early_dtb_pgd_next : pa, PGDIR_SIZE, - IS_ENABLED(CONFIG_64BIT) ? PAGE_TABLE : PAGE_KERNEL); + !IS_ENABLED(CONFIG_MMU_SV32) ? PAGE_TABLE : PAGE_KERNEL); if (pgtable_l5_enabled) create_p4d_mapping(early_dtb_p4d, DTB_EARLY_BASE_VA, @@ -930,7 +949,7 @@ static void __init create_fdt_early_page_table(pgd_t *pgdir, uintptr_t dtb_pa) create_pud_mapping(early_dtb_pud, DTB_EARLY_BASE_VA, (uintptr_t)early_dtb_pmd, PUD_SIZE, PAGE_TABLE); - if (IS_ENABLED(CONFIG_64BIT)) { + if (!IS_ENABLED(CONFIG_MMU_SV32)) { create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA, pa, PMD_SIZE, PAGE_KERNEL); create_pmd_mapping(early_dtb_pmd, DTB_EARLY_BASE_VA + PMD_SIZE, @@ -1149,7 +1168,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) fix_bmap_epmd = fixmap_pmd[pmd_index(__fix_to_virt(FIX_BTMAP_END))]; if (pmd_val(fix_bmap_spmd) != pmd_val(fix_bmap_epmd)) { WARN_ON(1); - pr_warn("fixmap btmap start [%08lx] != end [%08lx]\n", + pr_warn("fixmap btmap start [" PTE_FMT "] != end [" PTE_FMT "]\n", pmd_val(fix_bmap_spmd), pmd_val(fix_bmap_epmd)); pr_warn("fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n", fix_to_virt(FIX_BTMAP_BEGIN)); From patchwork Thu May 18 13:10:06 2023 Content-Type: text/plain; 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Thu, 18 May 2023 13:13:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415618; bh=fON6vf7tjch1Eg4H78YVWT75FX1UOvgM+cdcVq8dSsg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u23kMThXHmJ++BOnqpsZjjQZeLcF6BmMabQ66dcskKDbNxmgadWJ009CTKZ0ZXFO8 9wmPSgVwfHWqv57McbVpBTo4mvjnqaZkcPO7fLJ/IhhKQuEryBsw7uMNKb+eIvL9IU s/X2wT4/I5Nx02zvv6wVapEHBnLfFwa+m6DY4PlGXKNMlQooK2tjDYTvY17nN0DTyp rQY4XIlND+PHAHUlGvtIWTP7eWyXNpXmhy4Fc3W23JN2nKnQlCbWZMvw1mM7dvdEMn zqDiNXPmTMFKL29ygB/3ORIbk1AwJaKjrCswBNswWrSUibYKu7cMymqqkiU+dfD17L 16jkhw2h2BCUA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 15/22] riscv: s64ilp32: Enable native atomic64 Date: Thu, 18 May 2023 09:10:06 -0400 Message-Id: <20230518131013.3366406-16-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061339_871509_CCBE5517 X-CRM114-Status: GOOD ( 10.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The traditional rv32 Linux (s32ilp32) uses a generic version of the lib/atomic64.c, which are inaccurate atomic64 primitives and couldn't co-work with READ_ONCE/WRITE_ONCE, atomic_8/16/32. The s64ilp32 could use native AMO instructions to implement accurate atomic64 primitives. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/atomic.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9c458496ec3a..33fe624ef6d3 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -60,7 +60,7 @@ config RISCV select CPU_PM if CPU_IDLE select EDAC_SUPPORT select GENERIC_ARCH_TOPOLOGY - select GENERIC_ATOMIC64 if !64BIT + select GENERIC_ATOMIC64 if ARCH_RV32I select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_EARLY_IOREMAP select GENERIC_ENTRY diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 0dfe9d857a76..edfa6a74fe04 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -16,6 +16,12 @@ # endif #endif +#ifdef CONFIG_ARCH_RV64ILP32 +typedef struct { + s64 counter; +} atomic64_t; +#endif + #include #include From patchwork Thu May 18 13:10:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63F6AC77B7D for ; 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Thu, 18 May 2023 13:13:53 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdS3-00D32l-0F for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:13:52 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 998AC64F46; Thu, 18 May 2023 13:13:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 566E6C433A1; Thu, 18 May 2023 13:13:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415630; bh=8Y/3tw7LBtz2gYHWlOFw83dhZ7e45+M8w9YD/Nh3m5E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FXqmOW0KY+kh3dWehn3iktiaucY523D75j1oLEu2DkJNTYeHrG0CTGeI+pQW5p9WT 1VhHU8LKJg4V8guunv0uOqgA/bIkKJOerF+5A4BtxBY2lyKbPLXTc5wPcJSH9FXtjt syM7rD68B1355HMu7rGTlmhLpynWC52buCnMOTkGGe24fYGTyiauFRixNFibs0613T 5ys81zV8nXJbNU1Ypt5BY/i8IHnPTJypnlsgdrIQfEjxBD7huYczviHNM8U0bA2pR5 ydMN/D5jsIdvQ6d45fn5yx6DatgXTxVkPS5HyWR//xLGcPvG0FgCgCrPzlS3aFR0aD TvLYgcecSet9A== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 16/22] riscv: s64ilp32: Add TImode (128 int) support Date: Thu, 18 May 2023 09:10:07 -0400 Message-Id: <20230518131013.3366406-17-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061351_156439_EEBC0D65 X-CRM114-Status: GOOD ( 10.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The s64ilp32 uses 64bit compiler, so it could support “Tetra Integer” mode, which represents a sixteen-byte (128) integer. It's the first 32BIT linux support TImode :) Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 1 + arch/riscv/lib/Makefile | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 33fe624ef6d3..e0c3dee68510 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -305,6 +305,7 @@ config ARCH_RV64I config ARCH_RV64ILP32 bool "RV64ILP32" depends on NONPORTABLE + select ARCH_SUPPORTS_INT128 if !$(cc-option,$(m64-flag) -D__SIZEOF_INT128__=0) select 32BIT select MMU diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 26cb2502ecf8..68af463795e1 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -9,5 +9,6 @@ lib-y += strncmp.o lib-$(CONFIG_MMU) += uaccess.o lib-$(CONFIG_64BIT) += tishift.o lib-$(CONFIG_RISCV_ISA_ZICBOZ) += clear_page.o +lib-$(CONFIG_ARCH_RV64ILP32) += tishift.o obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o From patchwork Thu May 18 13:10:08 2023 Content-Type: text/plain; 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Thu, 18 May 2023 13:13:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415640; bh=1Q2OacXMgaOE1GaE82tcNP9mKmi++bzDbv1pyxwUhQs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E58RuOsyjDm0MSwqlPq2VfQw6WjfUgQVPzQemHtJ/mDL9a2shJvWKDryIjGnpK05X keC8NjhdHnpy5I71eEfiJMFTPpQ9k5iHl3josQCI8r9MZd8+adNza+aDLARO/5KGe9 dfE1rnK/7jCAE14U89IFb5B2/CfJWk2VmHkFbSFBjUh2RrwjpzbTp6U2XVScSw7FU2 6kroejxVAfIp7cjFoeQUkSdcjdkCbm3o09VBhCychkxxAxmdcZEIVz+GbgrEWHJyZi lMVRCRRErqxFb1hO5UmUj+ne/WYlU1JkFaxd1vrwKijk1neFq97kvrWVhX0neSaJ7D PBW6h3qYogesg== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 17/22] riscv: s64ilp32: Implement cmpxchg_double Date: Thu, 18 May 2023 09:10:08 -0400 Message-Id: <20230518131013.3366406-18-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061402_106965_A1F89A87 X-CRM114-Status: GOOD ( 13.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The s64ilp32 has the ability to exclusively load and store (ld/sd) a pair of words from an address. Then the SLUB can take advantage of a cmpxchg_double implementation to avoid taking some locks. This patch provides an implementation of cmpxchg_double for 64-bit pairs, and activates the logic required for the SLUB to use these functions (HAVE_ALIGNED_STRUCT_PAGE and HAVE_CMPXCHG_DOUBLE). Similar commit: 5284e1b4bc8a ("arm64: xchg: Implement cmpxchg_double") Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 2 ++ arch/riscv/include/asm/cmpxchg.h | 53 ++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e0c3dee68510..51853f883fc5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -78,6 +78,7 @@ config RISCV select GENERIC_TIME_VSYSCALL if MMU select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO select HARDIRQS_SW_RESEND + select HAVE_ALIGNED_STRUCT_PAGE if SLUB && ARCH_RV64ILP32 select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT && !XIP_KERNEL @@ -96,6 +97,7 @@ config RISCV select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU select HAVE_ARCH_VMAP_STACK if MMU && 64BIT select HAVE_ASM_MODVERSIONS + select HAVE_CMPXCHG_DOUBLE if ARCH_RV64ILP32 select HAVE_CONTEXT_TRACKING_USER select HAVE_DEBUG_KMEMLEAK select HAVE_DMA_CONTIGUOUS if MMU diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 12debce235e5..808730d151e7 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_CMPXCHG_H #include +#include #include #include @@ -360,4 +361,56 @@ arch_cmpxchg_relaxed((ptr), (o), (n)); \ }) +#ifdef CONFIG_ARCH_RV64ILP32 +#define system_has_cmpxchg_double() 1 + +#define __cmpxchg_double_check(ptr1, ptr2) \ +({ \ + if (sizeof(*(ptr1)) != 4) \ + BUILD_BUG(); \ + if (sizeof(*(ptr2)) != 4) \ + BUILD_BUG(); \ + VM_BUG_ON((ulong *)(ptr2) - (ulong *)(ptr1) != 1); \ + VM_BUG_ON(((ulong)ptr1 & 0x7) != 0); \ +}) + +#define __cmpxchg_double(old1, old2, new1, new2, ptr) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + register unsigned int __ret; \ + u64 __old; \ + u64 __new; \ + u64 __tmp; \ + switch (sizeof(*(ptr))) { \ + case 4: \ + __old = ((u64)old2 << 32) | (u64)old1; \ + __new = ((u64)new2 << 32) | (u64)new1; \ + __asm__ __volatile__ ( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (__tmp), "=&r" (__ret), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + __ret = (__old == __tmp); \ + break; \ + default: \ + BUILD_BUG(); \ + } \ + __ret; \ +}) + +#define arch_cmpxchg_double(ptr1, ptr2, o1, o2, n1, n2) \ +({ \ + int __ret; \ + __cmpxchg_double_check(ptr1, ptr2); \ + __ret = __cmpxchg_double((ulong)(o1), (ulong)(o2), \ + (ulong)(n1), (ulong)(n2), \ + ptr1); \ + __ret; \ +}) +#endif + #endif /* _ASM_RISCV_CMPXCHG_H */ From patchwork Thu May 18 13:10:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6763C77B7D for ; Thu, 18 May 2023 13:14:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 18 May 2023 13:14:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 867F1C433EF; Thu, 18 May 2023 13:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415652; bh=MyHJegve8NZNKQPZ+1otBp4zGgUGxsJifmAO8XUsjmQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zku0hQdEV1exPT3SP1wIQ3khOpfFtF+qMJJdeGimM00UCnJ1z3lRyLxy9ZeaD2GA7 kvoGNPfdoFZBUI8hyocJ1TK5nCnDerh6/rWdFQpX0MMpjQSpxJ1CXOfKRYjiccD3io FtdTmfxlGx/TOtpIclqH9RrchewsGAgtATU3mwpvt9agtw7b2QVRk1nG0JR14UNyJ7 fg2V4YuaXuF4bmFv5DoNlcrrJScjph1XlhNBoBbIU2eEZ4T3czhDyVHPfiU1uV8QjI LxnVDvrIPbL1FwdEXwlde2XnhMZ4T3p3eHq766tK8/WKOHqP1rmj8aIwCynqDNeSnu wpQLSaWkHWYFw== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 18/22] riscv: s64ilp32: Disable KVM Date: Thu, 18 May 2023 09:10:09 -0400 Message-Id: <20230518131013.3366406-19-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061413_235070_53AF6A64 X-CRM114-Status: UNSURE ( 9.35 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Disable the KVM host feature for s64ilp32 first, and let's work on this feature after the s64ilp32 main feature is merged. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Anup Patel --- arch/riscv/kvm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index d5a658a047a7..a91ce7e0b754 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -20,6 +20,7 @@ if VIRTUALIZATION config KVM tristate "Kernel-based Virtual Machine (KVM) support (EXPERIMENTAL)" depends on RISCV_SBI && MMU + depends on !ARCH_RV64ILP32 select KVM_GENERIC_HARDWARE_ENABLING select MMU_NOTIFIER select PREEMPT_NOTIFIERS From patchwork Thu May 18 13:10:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BE2BC77B7A for ; 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Thu, 18 May 2023 13:14:29 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdSa-00D3JA-1n for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:14:26 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2433A64F4C; Thu, 18 May 2023 13:14:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03258C433D2; Thu, 18 May 2023 13:14:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415663; bh=AwoQnmBHOr8wX0BVa478M177ccT62CL+qVUXJhTICuI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WGfQ4mTsDn9k0q6IINE7XDk0tKpDcaHJHIxootwL5i8ZJ0N7q3ng58l2ZjEY516m9 FKQw5tQCYBZakdMpIBAXpl2tc5W2YLS5RMM1pzt/wdz6TubznYeCa/b00k6pTNsDmR sc6hIPHQvtW9muFdbki2SUqga9mE3IzTx9htIZf3NlWlEZ4PQum9xN95fiZrmzSEZ9 7OkUxnDfttaUxZJhhF2ZPadDhwpxojueC1k4ARxqVNlNJGOAruHtt4FtqbP1fMei9I dF84cS/k70zpGSTYTyErDjUgaKm43y7gCp4bHwDDt79Ejta9aJeaugb8egsLEIIwzm CL8SNUms7jvfg== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren , Randy Dunlap Subject: [RFC PATCH 19/22] riscv: Cleanup rv32_defconfig Date: Thu, 18 May 2023 09:10:10 -0400 Message-Id: <20230518131013.3366406-20-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061424_634000_44C1C644 X-CRM114-Status: GOOD ( 11.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Remove unnecessary configs to make rv32_defconfig have a minimal difference from the defconfig. CONFIG_ARCH_RV32I selects the CONFIG_32BIT, so putting it in the file is unnecessary. Also, there is no need to comment on CONFIG_PORTABLE; it should come from carelessness. Next rv64ilp32_defconfig would like: CONFIG_ARCH_RV64ILP32=y CONFIG_NONPORTABLE=y Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Randy Dunlap Cc: Palmer Dabbelt --- arch/riscv/configs/32-bit.config | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/configs/32-bit.config b/arch/riscv/configs/32-bit.config index f6af0f708df4..eb87885c8640 100644 --- a/arch/riscv/configs/32-bit.config +++ b/arch/riscv/configs/32-bit.config @@ -1,4 +1,2 @@ CONFIG_ARCH_RV32I=y -CONFIG_32BIT=y -# CONFIG_PORTABLE is not set CONFIG_NONPORTABLE=y From patchwork Thu May 18 13:10:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5CB8C77B7D for ; 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Thu, 18 May 2023 13:14:37 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzdSl-00D3NZ-16 for linux-riscv@lists.infradead.org; Thu, 18 May 2023 13:14:36 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E3DDE64F4D; Thu, 18 May 2023 13:14:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 591ACC4339B; Thu, 18 May 2023 13:14:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415674; bh=qCpMPb52tthAzWjTWrS3Ez2Gh56jo5/cV/qoXhNQ0vM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SLWWWIPvdfekKIZ2DxDQt3ndwgs9Elm0COQLac0Rt9k1JespW6tf+PvRnJOQVd7tg lncnDcGrZbv7tZRJqImpTAd0dGU0mlf7gW2HmKzWHk7/voeo3Nx55OuPWH0mxjAwA/ 0CvUsOr48QIsVUrcLiY/Jk04fBahXRUnwHGUVhNQ65P3p0QVW0MtMu6d3JzqbdeIJU TSx0eo63ZrKxmVnbIQOB33Vzs0D4X9Ds0UGZMS+i6RB9lblXdE1VEcvKNoPp0puZ1s 8wiPjcn2n+bAjfX4rTVMn3OGCVhwhS8MWg0zREQSOha7VukOMSvbaIuFNO9QMhzLvn 5DvA0X36Fyv2w== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 20/22] riscv: s64ilp32: Add rv64ilp32_defconfig Date: Thu, 18 May 2023 09:10:11 -0400 Message-Id: <20230518131013.3366406-21-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061435_420470_B7ED4AD0 X-CRM114-Status: GOOD ( 12.28 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren Follow the rv32_defconfig rule to add rv64ilp32_defconfig; the only difference is: -CONFIG_ARCH_RV32I=y +CONFIG_ARCH_RV64ILP32=y Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Makefile | 4 ++++ arch/riscv/configs/64ilp32.config | 2 ++ 2 files changed, 6 insertions(+) create mode 100644 arch/riscv/configs/64ilp32.config diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index d47ba6b09b41..22b62de62192 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -187,3 +187,7 @@ rv32_defconfig: PHONY += rv32_nommu_virt_defconfig rv32_nommu_virt_defconfig: $(Q)$(MAKE) -f $(srctree)/Makefile nommu_virt_defconfig 32-bit.config + +PHONY += rv64ilp32_defconfig +rv64ilp32_defconfig: + $(Q)$(MAKE) -f $(srctree)/Makefile defconfig 64ilp32.config diff --git a/arch/riscv/configs/64ilp32.config b/arch/riscv/configs/64ilp32.config new file mode 100644 index 000000000000..7d836aa2fae7 --- /dev/null +++ b/arch/riscv/configs/64ilp32.config @@ -0,0 +1,2 @@ +CONFIG_ARCH_RV64ILP32=y +CONFIG_NONPORTABLE=y From patchwork Thu May 18 13:10:12 2023 Content-Type: text/plain; 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Thu, 18 May 2023 13:14:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415685; bh=Se41gQju7esb4eo2kifFLRU4bWbFiAHi/+vBMhWFQy0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MH7FFdjhv5/hwrAsCy6lfMY4l1Pv83IQ3w11GbxsYD7Ik2s+QS8pDGhZ6tyd1KEsU Xz3FO+/ymMs95ohrSpWHUn5SoUBC0hv0Ej83cPs/kmPU8agDD15hAISzoxm/ffXp1V YtuRbt1TUwzUk559iBRqmIcU/wY+KE9jBmTfAGtMndWJkwkk6ezO3f5D5tOpxWX/Jz P4YM2DZn0pWXFKnp9QoA7XZFX4UMltBJgdhSQS+ROAXz4qwryh9z2lwmEqbyuTORNB Peuj6Bg8E/egQtYpwH90ipyySQSrTPJfYH/PsolmL2DeIRbeQA/K+AATERyx9p+/97 u687mEIT/evLQ== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 21/22] riscv: s64ilp32: Correct the rv64ilp32 stackframe layout Date: Thu, 18 May 2023 09:10:12 -0400 Message-Id: <20230518131013.3366406-22-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061446_552682_DD566C1A X-CRM114-Status: GOOD ( 10.41 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren The callee saved fp & ra are xlen size, not long size. This patch corrects the layout for the struct stackframe. echo c > /proc/sysrq-trigger Before the patch: sysrq: Trigger a crash Kernel panic - not syncing: sysrq triggered crash CPU: 0 PID: 102 Comm: sh Not tainted 6.3.0-rc1-00084-g9e2ba938797e-dirty #2 Hardware name: riscv-virtio,qemu (DT) Call Trace: ---[ end Kernel panic - not syncing: sysrq triggered crash ]--- After the patch: sysrq: Trigger a crash Kernel panic - not syncing: sysrq triggered crash CPU: 0 PID: 102 Comm: sh Not tainted 6.3.0-rc1-00084-g9e2ba938797e-dirty #1 Hardware name: riscv-virtio,qemu (DT) Call Trace: [] dump_backtrace+0x1e/0x26 [] show_stack+0x2e/0x3c [] dump_stack_lvl+0x40/0x5a [] dump_stack+0x16/0x1e [] panic+0x10c/0x2a8 [] sysrq_reset_seq_param_set+0x0/0x76 [] __handle_sysrq+0x9c/0x19c [] write_sysrq_trigger+0x64/0x78 [] proc_reg_write+0x4a/0xa2 [] vfs_write+0xac/0x308 [] ksys_write+0x62/0xda [] sys_write+0xe/0x16 [] do_trap_ecall_u+0xd8/0xda [] ret_from_exception+0x0/0x66 ---[ end Kernel panic - not syncing: sysrq triggered crash ]--- Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/include/asm/stacktrace.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/stacktrace.h b/arch/riscv/include/asm/stacktrace.h index f7e8ef2418b9..cea8aafbecca 100644 --- a/arch/riscv/include/asm/stacktrace.h +++ b/arch/riscv/include/asm/stacktrace.h @@ -8,7 +8,13 @@ struct stackframe { unsigned long fp; +#ifdef CONFIG_ARCH_RV64ILP32 + unsigned long pad1; +#endif unsigned long ra; +#ifdef CONFIG_ARCH_RV64ILP32 + unsigned long pad2; +#endif }; extern void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs, From patchwork Thu May 18 13:10:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guo Ren X-Patchwork-Id: 13246818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F508C77B7D for ; Thu, 18 May 2023 13:15:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 18 May 2023 13:14:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67B72C4339C; Thu, 18 May 2023 13:14:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415696; bh=lQTH6fQXqgDOV13+OOf/m8+ReoWieEMsKkpHvX1KsBk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U6EWjbahGfHXvROjB2vQAPwqJYGK9YXMzzTxQLwkq71y9CcePnOM9o0N6RgIJxBAA iTUw77TFtCy266dawOWVsx7sYBg81q/acOunzlByttuu/7hUXMU6bAdWUJ7eOvEQgU 3It9oF8OK6aVWRyoLzt3nCb15zQ4TaRdM2/T7/NKOFw0Jcs8EDOLPfiSuZYUmrZnzE fbsFQvX+QYCwyd2VkmID9Zbj0EnVj2cHi1nzb1M6HAeGrGFDVk/Au69twErCk4x7+s JeniPBb8OhNwQRv4lKBbLI+UqzRKL20bsZWqfA8S6smJl087/UeJQBxf7ivFSyJJGH lfg8CnyC2mhlA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 22/22] riscv: s64ilp32: Temporary workaround solution to gcc problem Date: Thu, 18 May 2023 09:10:13 -0400 Message-Id: <20230518131013.3366406-23-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_061457_537199_291679A6 X-CRM114-Status: GOOD ( 11.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Guo Ren There is an existing problem in 64ilp32 gcc that combines two pointers in one register. Liao is solving that problem. Before he finishes the job, we could prevent it with a simple noinline attribute, fortunately. struct path { struct vfsmount *mnt; struct dentry *dentry; } __randomize_layout; struct nameidata { struct path path; struct qstr last; struct path root; ... } __randomize_layout; struct nameidata *nd ... nd->path = nd->root; 6c88 ld a0,24(s1) ^^ // Wrong arg of mntget e088 sd a0,0(s1) // Need inserting "lw a0,0(s1)" here mntget(path->mnt); 2a6150ef jal c01ce946 Any gcc helps are welcome :) Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: LiaoShihua --- fs/namei.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/namei.c b/fs/namei.c index edfedfbccaef..22a2ef77e074 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -541,7 +541,7 @@ EXPORT_SYMBOL(inode_permission); * * Given a path increment the reference count to the dentry and the vfsmount. */ -void path_get(const struct path *path) +void noinline path_get(const struct path *path) { mntget(path->mnt); dget(path->dentry);