From patchwork Thu May 18 18:45:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247258 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5631CC7EE2A for ; Thu, 18 May 2023 18:57:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gfo2Fd/QE0SX2rkfg0SnxWgQedMPVncRJQWsqNyC2wM=; b=Ktj6KJdT9+IK4Z uf8EzDuxyxHd16UO+PMOLexC0yxzW334h54Bv3Eaoym1UkYkLU5g470wPtIZm+BKuGooYolJKdINF Xl21izcbYcXGNZOG1F13HJJrrCpWIYZ9gQx3govXK+n0oFMbN+/t8hovJIHuKTP54LNUczAK7E+6O Wx06hLSoNpKn7eLF5/A0pvFNeJJqGmZ3ke0Rt5GyDztcGYn2NWuBhZh4BPlRd8/LiHf1vsFTyVPT4 juKrby3HKMsHN1ZcMwFeznkVy+8D7I6l10hrsPmuDdgu9BNXN0FEXacBA9DJZpdLix/DJassq+rq4 GDZOFM8+QLxqIRIlLTFQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzio6-00DssJ-06; Thu, 18 May 2023 18:56:58 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzio4-00DsrS-03 for linux-riscv@lists.infradead.org; Thu, 18 May 2023 18:56:57 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8D1F661017; Thu, 18 May 2023 18:56:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 371ABC433A1; Thu, 18 May 2023 18:56:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436215; bh=hH6Or+D9CJEmJbCMZBOXhGK6nn9vuBMRv9LnXKOB0J4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qLyl0D4TopzJyU9z00h+qUgzbvSNep9xMKXs82tfn2tXobCqsXKxFun0hWCXKKrhi 2Y5YBJez9Iy550P/WzkKhFWjRzuD0CVk16r1eeG9+odRnAsKUJk01JdR3EdedXAMU9 d36D2huVwKnUyJwx4bG5FWdfEcNnHM4zGBwbFkMuAu13QYHNDKThVG2kPvL3xq9wNg FtFoCZftuQ55acPYFUfjcjynVMBJ1f/g3BYPBgmK/EZ0ypIkai4uxt10EE3LqHC2wl t9nh4q7/ZE0TQ0lgu8RVDA+4ndCAbYzakt9Zz4zqh37fHXrOYuDghWLNL+s5eyWijr wSFfn/LWmPsSw== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 1/9] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Date: Fri, 19 May 2023 02:45:33 +0800 Message-Id: <20230518184541.2627-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115656_096522_42AC176C X-CRM114-Status: UNSURE ( 9.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add compatible string for T-HEAD TH1520 plic. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Reviewed-by: Guo Ren --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index f75736a061af..0fa9b862e4a5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - thead,th1520-plic - const: thead,c900-plic - items: - const: sifive,plic-1.0.0 From patchwork Thu May 18 18:45:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247259 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8465C7EE2A for ; Thu, 18 May 2023 18:57:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DU0zmBP/vlLLm6AsfCKQDGL3gwY0FeNgz+yBo/bt7TU=; b=kDTXasUPBj+W4E EJv2We571X8h0dh7LThbR6gCagl1c+l885TXE5VmJaLEPyQUEZWPZmSNNuLH8KaZpVWnGeDjmn7wo xCTTYJFblJTlqd2XfQM0qzDPENAl5ao1DGJrs0icbVBIopVihwwR3Kc8VFB7GxxHAoCVt5Dxbk2U7 Q1QYmmf4BClxDiWkXk0aW28vuL7D3TZNNvV/ffsGzS2wZikrQapH/iOUIUKVy7m+6yvMBP2G7zjG5 IZAvMU4+vE20/bPYaKNnYMEqgMNebX2fqVRyScEsv2HHaT2cxi+zGEOEwJP6mpelUtEtYVG2+rZe2 ag060VdL8PCI88vd+qSQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzio9-00Dstd-24; Thu, 18 May 2023 18:57:01 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzio7-00Dssk-0p for linux-riscv@lists.infradead.org; Thu, 18 May 2023 18:57:00 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C26F361B56; Thu, 18 May 2023 18:56:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 66F9BC433A0; Thu, 18 May 2023 18:56:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436218; bh=KmkRRVkb2zPg16/+5SP/TqktZEzO+CbiEGfvCZls0Vs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EDdT7AyS81YPAnffSgoZvef1gPV9a5EzUleOkNdMKnOCnVW6oLa9L+jqaWFy1y6DM UNlmgX+OumKc4rqRDnunVnrjm2OM17/479A7ed75G1/7a1sZ1vFLoXuWSXO+Y+XcEl XpJbGdD2AxW6wM37rBW0ZdW59dydpuNwrglrUXdgk4N02oYas/6fKzdrsPoNnJNc5L YqNDGzEtWzCPv3b16VqmBOwnOTZkg9jVlBY7bl+v22GWuHTcj1vfmNzOmPG6LDv9wN 7kOJAfN2ZztrUtISdoGBSD4x8QcMKKkdPxllRGE+tiJGb51EmK3trcDlt/5dHrG8cn XI6D2GSmacMsg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 2/9] dt-bindings: timer: Add T-HEAD TH1520 clint Date: Fri, 19 May 2023 02:45:34 +0800 Message-Id: <20230518184541.2627-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115659_334130_E73E0B78 X-CRM114-Status: UNSURE ( 9.77 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add compatible string for the T-HEAD TH1520 clint. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 94bef9424df1..388d3385d7eb 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - thead,th1520-clint - const: thead,c900-clint - items: - const: sifive,clint0 From patchwork Thu May 18 18:45:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247260 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43ACCC7EE23 for ; Thu, 18 May 2023 18:57:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=taxnSJ7HIi6S/FDWUH+p70J0ScnM5zZ5onzV0dK5toE=; b=l4UuDfxxx2hf5D XMX7iVlfCK6qtbvVbssiNjAWqg9xC253aTeJs9llmZcdBKm3WniUIkQykSNQMlK/n2yDcdzo/pdmQ YQAowVOAZgI7x2N2dw+4NhP7FS96ZGfowL6AIQYxHL3sgZ7AzOc+fqpnFHmjV543Ns3YpPQtoqqv0 sKoOJEEH7kj4BiwPHZWoddTXMEjzMa75XbsKE8VPZblcIk7xKbyRX6EUtbeDCSXaSiY0+CFUTgLfw cvWK3kJGhg8f6Iz0qhVIpJ2S5tkBL+xVCq0Z8dv9Al5EAeeIFL8piyfww0DTue5dcyCjAejDRob4M bDpE0qjQ0NJOsMNA+jPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzioD-00DsvN-13; Thu, 18 May 2023 18:57:05 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzioA-00DsuL-2z for linux-riscv@lists.infradead.org; Thu, 18 May 2023 18:57:04 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6A0C165146; Thu, 18 May 2023 18:57:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9743AC4339E; Thu, 18 May 2023 18:56:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436221; bh=ayCUu7VWTParlzqlhysZ/3yMoFf8bKiG9G6ke1+jMJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bk41F/OJXLE+OA+bkypJqEMkcA4OcdwSmKYtN4q6m6SVlGG9YWXwH7FfaQClnLhwB SFOmC8XoQ9wUmaOsHiPreGL8eUEYVNmUDPijwPOJDy9Lczx3zXZ+KohWgdUDBZ4zZk 8FkVWqpsiaSsT9jHknJmsTvhZa3tg0RaZpNyohe4c+4Rnf1e6SSL0lec9vcPauXmmX YKEOmhM0edn3+YfkOFjNOoWeoov0Qa1ibfk0ks3ghjYgozf9W2xzpFuRYlHov6Jz0Y Bx9zzwPWh+SjoaMPSedIZNonW1Q1tT7ZxdszhpyWbxR5RjtUSYbTlGEeKoC/21I0Ku JvW03+ywiDL1A== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 3/9] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Date: Fri, 19 May 2023 02:45:35 +0800 Message-Id: <20230518184541.2627-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115703_003775_2BE0E91F X-CRM114-Status: GOOD ( 11.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Several SoMs and boards are available that feature the T-HEAD TH1520 SoC. Document the compatible strings. Signed-off-by: Jisheng Zhang --- .../devicetree/bindings/riscv/thead.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml new file mode 100644 index 000000000000..e62f6821372e --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/thead.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD SoC-based boards + +maintainers: + - Jisheng Zhang + +description: + T-HEAD SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A + items: + - enum: + - sipeed,lichee-pi-4a + - const: sipeed,lichee-module-4a + - const: thead,th1520 + +additionalProperties: true + +... From patchwork Thu May 18 18:45:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247261 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BCF4C77B7A for ; Thu, 18 May 2023 18:57:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yc5QEpmAFO5z/lNq9uC+i0JXC0qcf3TjGDmtPc4oKG8=; b=Ha9qhiMEMERXxR HgxObgHA0hDT4Pksg/CxnIYkPakFP3xGT5Y2+Nb5ByoJOgFs8+raGSQo4K/bSuPJgqbj0s1IKfN3I dkTzrCdgpCmz/K9cUbGo9he7k5u6nVndfU2mGoCorL4AgwEGQKS5nbAXDlvWi94ZNmmMd5kAeV8DQ WmvkkiSb2A4jyzYQfkwoX4TjsjI4fLRsaAsAJx3gCdsZEEJpRG2Nr3jeDmGW7GADU+HMQwc+bYXZp 2aTSCLGn6nym0mDbd8XwwX5bLbK4R+w2N6sxGFyjUGNM6Bx6zncVa21H8PO+gehEn5jm17BFf4fFX 9cEoYLUhkn7ekd4FBFSQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzioF-00DsxD-3B; Thu, 18 May 2023 18:57:07 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzioD-00DsvW-2F for linux-riscv@lists.infradead.org; Thu, 18 May 2023 18:57:07 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 34E69651AD; Thu, 18 May 2023 18:57:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C7685C4339B; Thu, 18 May 2023 18:57:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436224; bh=Nt5XnCpe1ezvh1ILRVySirsoVP1f3952Ou9DF76XFOQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hVM9QbkTan5hxlgEYa3QeGODzjLKHMp6w/OAt9LlH6FCGSltcldDO0BUtI3oF8UFm taDbaDlW+RNfTO7NitSBmHqK2wkbjgvosrUL1y3C2jB7u1ilVrMoRLixfBR2hnO2Mp /mUC6OVpYa0Me9zmuh9bT+2tVSe8JWiMesvZdVwv26q6K2m+xstiPeQtherWnNU8h2 UoMncU6IRtgNfNJRqm4X+y2uhNhcNneHsN6Ya4WY+HCICFGs45E3zI2alqvhHfG7DJ +b/6CWh6Sa6bZGjzNx3rySyjUjIh8UabaISQkizjpxFtTNv4MOtzlNLLAYoSqg+eMC puwni+5V6oMyQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset Date: Fri, 19 May 2023 02:45:36 +0800 Message-Id: <20230518184541.2627-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115705_810165_EA70250D X-CRM114-Status: GOOD ( 15.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware. Signed-off-by: Jisheng Zhang --- .../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml diff --git a/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file mode 100644 index 000000000000..ba8c87583b6b --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD cpu reset controller + +maintainers: + - Jisheng Zhang + +description: | + The secondary CPUs in T-HEAD SMP capable platforms need some special + handling. The first one is to write the warm reset entry to entry + register. The second one is write a SoC specific control value to + a SoC specific control reg. The last one is to clone some CSRs for + secondary CPUs to ensure these CSRs' values are the same as the + main boot CPU. + +properties: + $nodename: + pattern: "^cpurst" + + compatible: + oneOf: + - description: CPU reset on T-HEAD TH1520 SoC + items: + - const: thead,reset-th1520 + + entry-reg: + $ref: /schemas/types.yaml#/definitions/uint64 + description: | + The entry reg address. + + entry-cnt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The entry reg count. + + control-reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The control reg address. + + control-val: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The value to be set into the control reg. + + csr-copy: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + The CSR registers to be cloned during CPU warm reset. + +required: + - compatible + +additionalProperties: false + +examples: + - | + cpurst: cpurst@ffff019050 { + compatible = "thead,reset-th1520"; + entry-reg = <0xff 0xff019050>; + entry-cnt = <4>; + control-reg = <0xff 0xff015004>; + control-val = <0x1c>; + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; + }; From patchwork Thu May 18 18:45:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247262 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71A68C7EE23 for ; Thu, 18 May 2023 18:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=m46+R1mgrrqrk+hJwdIXy9BS8gmbrp3BdMd+hlQKF1Y=; b=10Nfr9UrPYccLi OO2Sfwe6B0EInKFmswSlVtRcqIWyFrfrQRuzn8RvXhl/SRZEcKfoUmSaZC2DSiDJbPtH7CUD27hEU eotrko1PtaMD6Xger6gJNgm8Qej2LX/gkjAXWuj8rtxuHr3Fv82JcU6zv5ZTUsuRAMK0miqLmczj+ KwppojahigTu3lNpNKOlE9Gl3sbQvmgt16dudTl9FIzKzOqBdYiJ1B4K7zW8s2Ru5/+9vC3YJAhvi DNg+6R+fh5rS5OCUPB4A3KesdvwZDS8ks/Wscpr8BQa6mGhTSOZoapfyGr29/rI6q7HjKf/ubY1Ju WO0P3mI0N1xDhbwaO31g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzioJ-00Dsz0-1r; Thu, 18 May 2023 18:57:11 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzioH-00Dsxv-14 for linux-riscv@lists.infradead.org; Thu, 18 May 2023 18:57:10 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D924D651BF; Thu, 18 May 2023 18:57:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03542C4331E; Thu, 18 May 2023 18:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436227; bh=Hxt77XTd4sJ4iSsW4a+tGjggeRmSDhhjr46ffLnz1is=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ozM0GDlhAZV8HvMUYO9tXWmKQKFJ9BVbHZS3eBKkSx/LEFwoXPchpJCjWLpb4zp5K exANsNP2OcsiyOaErwuldCtwi97q3hKqXFUXC5e9rXiiX/u5WFwp9KD2rc0tTv6eWP o9GzOQYbCiH2x4EGtMDkWy0hd1hUMHiI9bDqfGu2E5w9njF9Q90a+FpJED1rUXLWGx ICt8X8CP4RQxC00MmpdH/7bWShTEqX2d9XcEJJ2zo267E7fJgybAKWTsLKNhcmyEXq RFPVyuLF7YlNMHb7rB7hjWivqCR5d/pMnh9ES2G0fMqXPQw9ikRg9PzpGwWVklQwak jh/dLVW4bHlug== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 5/9] riscv: Add the T-HEAD SoC family Kconfig option Date: Fri, 19 May 2023 02:45:37 +0800 Message-Id: <20230518184541.2627-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115709_417688_EBD3B9D7 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT From patchwork Thu May 18 18:45:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247263 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC25CC7EE23 for ; Thu, 18 May 2023 18:57:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bpTD+H+LddprKLSasiLiLoPlmol7YkGMpMIHhIPy8yw=; b=HULPg6bPJeR2q5 fHJkGtHZry6tP6t6FGEch7HFat82TdvfWsqLLpmCI06KYyQrdLGwZA40wx9GSEnefj4MGY73nWi1T JCRx8b4U6o9Ksp/7DSaf+G855SxhWJjiyQ7fxaAxZSy/aac39ynV1ArK66HqUqnLzr2ZWUrRK1GNz mfWDOf0jKhiTUGU548nI/Ri3FWFJ4EuSTQc+El2hC2P2zGYpl4LOx5ZGJnOUKqB5kIE9eumYu2NeS sMdItbodIVAxTt5aWRJoz1LkJzDVqdDLgc1i9+iBylSKWkqWOXQ5V8XvpLd/pv/8POhogkU1aVmxy crcoQJRTcC44CYfkLfVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzioN-00Dt17-0c; Thu, 18 May 2023 18:57:15 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzioK-00DszL-0C for linux-riscv@lists.infradead.org; Thu, 18 May 2023 18:57:14 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 919F7651AF; Thu, 18 May 2023 18:57:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3488EC4339B; Thu, 18 May 2023 18:57:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436231; bh=2rqP/5lp09dAs7KjFgn+qsNlAk61u7AjjbQzzAEXDO4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mgzU+3JvEg3f3/WI7IahDByEXfCY/IMaC31gfTa1PEtYadTOkA/BYLXfGxGdCP5W+ vep3pxz6tSfoQHV4tj296b++HH/77rQMO1wUNxBk9nB5zVMUFKFjHXdj1phymwUSsv TZO1m06sIiCyGWwFvd3Dhaq8q0cBoZm1mdxsqu8yU3ivymoSqVfu7xFR+xZrQeZwm9 mD/kGG6uM6iG428MohooytX0efxznEv4Ti3PVN8tpBJjOGRiFrlxi6gUoMEszQr/oR Cygog7u24I2O1p0A+6fFxQ9WljciQpALcVWtcKEHcmpI7vCA4sgPEaeE7lfKmJxVaG QyPAatJ8HaJ2A== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 6/9] riscv: dts: add initial T-HEAD TH1520 SoC device tree Date: Fri, 19 May 2023 02:45:38 +0800 Message-Id: <20230518184541.2627-7-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115712_190757_BC9D3DD8 X-CRM114-Status: GOOD ( 12.93 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add initial device tree for the TH1520 RISC-V SoC by T-HEAD. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++++++++++ 1 file changed, 451 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi new file mode 100644 index 000000000000..60754d7c6319 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + compatible = "thead,th1520"; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <3000000>; + + c910_0: cpu@0 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <0>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_1: cpu@1 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <1>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_2: cpu@2 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <2>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + c910_3: cpu@3 { + compatible = "thead,c910", "riscv"; + device_type = "cpu"; + riscv,isa = "rv64imafdc"; + reg = <3>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <512>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <512>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&c910_0>; + }; + + core1 { + cpu = <&c910_1>; + }; + + core2 { + cpu = <&c910_2>; + }; + + core3 { + cpu = <&c910_3>; + }; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <1048576>; + cache-sets = <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_24m"; + #clock-cells = <0>; + }; + + osc_32k: 32k-oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + + apb_clk: apb-clk-clock { + compatible = "fixed-clock"; + clock-output-names = "apb_clk"; + #clock-cells = <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible = "fixed-clock"; + clock-output-names = "uart_sclk"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpurst: cpurst { + compatible = "thead,reset-th1520"; + entry-reg = <0xff 0xff019050>; + entry-cnt = <4>; + control-reg = <0xff 0xff015004>; + control-val = <0x1c>; + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; + }; + + plic: interrupt-controller@ffd8000000 { + compatible = "thead,th1520-plic", "thead,c900-plic"; + reg = <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <240>; + }; + + clint: timer@ffdc000000 { + compatible = "thead,th1520-clint", "thead,c900-clint"; + reg = <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7014000 0x0 0x4000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f00000 0x0 0x4000>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xe7f04000 0x0 0x4000>; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f34000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xe7f38000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec005000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xec006000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart2: serial@ffec010000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xec010000 0x0 0x4000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + dmac0: dma-controller@ffefc00000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0xff 0xefc00000 0x0 0x1000>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb_clk>, <&apb_clk>; + clock-names = "core-clk", "cfgr-clk"; + #dma-cells = <1>; + dma-channels = <4>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,dma-masters = <1>; + snps,data-width = <4>; + snps,axi-max-burst-len = <16>; + status = "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc32028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xefc3203c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f08000 0x0 0x4000>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible = "snps,dw-apb-uart"; + reg = <0xff 0xf7f0c000 0x0 0x4000>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_sclk>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33000 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33014 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc33028 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible = "snps,dw-apb-timer"; + reg = <0xff 0xffc3303c 0x0 0x14>; + clocks = <&apb_clk>; + clock-names = "timer"; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff41000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + ao_gpio1: gpio@fffff52000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xff 0xfff52000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portf: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; From patchwork Thu May 18 18:45:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247264 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6C0EC7EE25 for ; Thu, 18 May 2023 18:57:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Thu, 18 May 2023 18:57:16 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C780C651B0; Thu, 18 May 2023 18:57:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67568C433A7; Thu, 18 May 2023 18:57:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436234; bh=SPhHXPcnyMrXjaiP7DOxwbB5VjmdUJq9U0kUEmDjQ0w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kahOTcxTy32CFM9eHd/MHg6lpg/GXB3H9L5itF0hjkwIgLWkXf14++KVJUXdJsHhx 2hSOWca+EOez7Tsd73O5z396YvhAC2TJwFiUIm51230K1jbg0ts8DXU2EML0wimE7y CCuZT5F6PT1KeRQdFIssnO0sC42+p5sG0mCB/Zir3xQvV724B35dt74iEMtLs5x0dP Ftg/9JWwfTIpc+GWix2ZSbBX9iA5zYgE7Zk7wmNH5Zdlfp2l2PRENKUKXIsYRjGcng FuSLVOCLPMoNgR/FHr5IXiEUe96qyaIzc5zGp2gh3FN+/23CozongCD3Wy2P9YiEnx L35M74T2aOEYA== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 7/9] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Date: Fri, 19 May 2023 02:45:39 +0800 Message-Id: <20230518184541.2627-8-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115715_353392_9ED619E7 X-CRM114-Status: GOOD ( 15.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/th1520-lichee-module-4a.dtsi | 38 +++++++++++++++++++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..1e884868ccba 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -2,6 +2,7 @@ subdir-y += allwinner subdir-y += sifive subdir-y += starfive +subdir-y += thead subdir-y += canaan subdir-y += microchip subdir-y += renesas diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile new file mode 100644 index 000000000000..e311fc9a5939 --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi new file mode 100644 index 000000000000..4b0249ac710f --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model = "Sipeed Lichee Module 4A"; + compatible = "sipeed,lichee-module-4a", "thead,th1520"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&apb_clk { + clock-frequency = <62500000>; +}; + +&uart_sclk { + clock-frequency = <100000000>; +}; + +&dmac0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts new file mode 100644 index 000000000000..a1248b2ee3a3 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include "th1520-lichee-module-4a.dtsi" + +/ { + model = "Sipeed Lichee Pi 4A"; + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; From patchwork Thu May 18 18:45:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247265 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52F0BC7EE23 for ; Thu, 18 May 2023 18:57:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; 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Thu, 18 May 2023 18:57:19 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0317E651AF; Thu, 18 May 2023 18:57:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DC6AC433A0; Thu, 18 May 2023 18:57:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436237; bh=vxBYR6LtHdTWo59agyMO2DjmnNEXIpF3f4ssS0Pr5DU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Km1I+KHyYtnUN0pmY1DDp07p0EmyV4uwgUlqNQjv0THFIX/Z+sDhlyrED7Snmr5wG EBwNATQzc89st4HbSJmDYMmrm3w5yciXzJkyjUc+sHSRI2QyKKTCULLkts4umpWAPE p4BxzkN2XkbTv1TzN86ZSgOUu6hTmJk3+/q4/QMDejKNDiIUzJYtXfm2+2RY0/bv0D UkhQ4NdCtw5rhpLhGbdcsmSM9lmdgliu5oHuN4yitls/IWMiqrzlzN7B8GFzYRiIar fvM366GxuOHSbd2dOom/rA2HjSkRZegJ5yQrRcbVnbJWK+qeAac5OuPgLLE5MR42l2 Uw2Bj7cE/XPlQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 8/9] MAINTAINERS: add entry for T-HEAD RISC-V SoC Date: Fri, 19 May 2023 02:45:40 +0800 Message-Id: <20230518184541.2627-9-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115718_498274_E2577D62 X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, I would like to maintain the T-HEAD RISC-V SoC support. Signed-off-by: Jisheng Zhang Acked-by: Conor Dooley --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e0ad886d3163..6df20c65798a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18162,6 +18162,12 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c +RISC-V THEAD SoC SUPPORT +M: Jisheng Zhang +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/thead/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang From patchwork Thu May 18 18:45:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13247266 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDAD3C7EE23 for ; Thu, 18 May 2023 18:57:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Y0hordrSOrnG1BECaAqMvzLbDhhe1a750AnnXd+8SIY=; b=UR66NNi7V/BH7o WFbH9Xd9f+Xk0ZaoCxGIxJI0PNp118q5oyLwGbfdoaXu+u9cTt7ZvCHVLe9vqY2wO/S/GBT+oE3XV ZNid1LqT0OZIat6riHLzSyBT03vZYmrzOjfqeZmMnj9pbuzo93rcPRDGJBtAnO0bUpeWNZBoSOy7F fhyHg6bEUPtOQ+W444920MS9Chrb/x3hGm9tNc0jXZFQjYUPWiuUTcN2758OP3keN51quKYHUdl0p CHWN1ALkUJu3LV0C/9t51lCc6XCW+3aAUpSZz7ED4WxT+Ixqbgiie/0O7z6KZbr8Xq4Tjb83k8FY/ 1DcKScEvnwilPhjsNFQw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pzioW-00Dt7S-0Y; Thu, 18 May 2023 18:57:24 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pzioT-00Dt5w-2z for linux-riscv@lists.infradead.org; Thu, 18 May 2023 18:57:23 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7588E651B0; Thu, 18 May 2023 18:57:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE1CDC4339B; Thu, 18 May 2023 18:57:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436240; bh=+8gBhUykoZM8TrvHxezwEoqx6vcc9txPAEKaZGcJ4uo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZfU52L68DqN1YEclN4xauwvlvDjt1TExLclICt6uv1q20JIejrXEOSecNLjbfZqz7 JJQ+6OMTx6RM13fMAta6Iuy5IdDry0ywDr6F6d59rPIKbgFmHvXHVvFT1OxXgXEoHX nkIDH5iXcHMbI2hhQg9j+8iNBjOpS4tBHXxm66FjoMCKw0liH8kyALT0X62UFJ3wFE VWpEA7TfQb79Vae3ejwi0fhTTCiooz2bgyEbWKar20iS3LJu6dvxWvavBUys/djyFi 8CpqtjNAOU1D1zoTmrNPTCt2hOWang2hhmG/IYk4q8gMfeTpksG/mXoNvxHUrh9qS9 QZZns6KoH2r9A== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC Date: Fri, 19 May 2023 02:45:41 +0800 Message-Id: <20230518184541.2627-10-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230518_115722_008638_D988FCF1 X-CRM114-Status: GOOD ( 10.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Yangtao Li , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Wei Fu Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Acked-by: Guo Ren --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..109e4b5b003c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -27,6 +27,7 @@ CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_THEAD=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y