From patchwork Sun May 21 22:28:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E713C7EE23 for ; Sun, 21 May 2023 22:29:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231216AbjEUW3b (ORCPT ); Sun, 21 May 2023 18:29:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbjEUW3a (ORCPT ); Sun, 21 May 2023 18:29:30 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CE8DE3; Sun, 21 May 2023 15:29:29 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMPLji009157; Sun, 21 May 2023 22:29:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=LtCWgoSeg2IVr0yifkpkcLi30+ylQs9PMCOVzVX4M0s=; b=JvmL+6PkvVuHiuCA/RLWuR5iQXx+h1oImARg5AmCmjNUzDknwi08v6cBZBhBOkTX+Lz2 dtF01wLz2e/tfisb03nFJWPJrEi7r3u9/jlrkgUgymir0i1sNzQlgig7XUSQOQEBtwM4 oOl4wIRpuJjgpGcR6L04WH9QsJoKqkCSv4BB1ApnkDGSilS8kPcptzH6Jp3zQO7ERffY rt3/lQarUhUQMRrwC7/Mb1kzaiju2tt7NE32xVj6HpG+1As3fT9Q4lO0ItvaA8d2oHde ae/y/QGZpp1xYlJW6TDZr7WqDPo9K2kC/9/6I64ZVnEbYxKIkYdak7ORch29/YfV45PZ Uw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qppkdj8cu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:24 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMTNTH025424 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:23 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:16 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 01/13] dt-bindings: remoteproc: qcom: Add support for multipd model Date: Mon, 22 May 2023 03:58:40 +0530 Message-ID: <20230521222852.5740-2-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KeF7L1x08_YwqFNNVY_42006eraE6GaI X-Proofpoint-GUID: KeF7L1x08_YwqFNNVY_42006eraE6GaI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 adultscore=0 phishscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210202 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add new binding document for multipd model remoteproc. IPQ5018, IPQ9574 follows multipd model. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - Fixed all comments and rebased for TOT. - Changed to BSD-3-Clause based on internal open source team suggestion. - Added firmware-name. .../bindings/remoteproc/qcom,multipd-pil.yaml | 265 ++++++++++++++++++ 1 file changed, 265 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml -- 2.17.1 diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml new file mode 100644 index 000000000000..3257f27dc569 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml @@ -0,0 +1,265 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,multipd-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Multipd Secure Peripheral Image Loader + +maintainers: + - Bjorn Andersson + - Mathieu Poirier + +description: + Multipd Peripheral Image Loader loads firmware and boots Q6 pd, WCSS pd + remoteproc's on the Qualcomm IPQ5018, IPQ9574 SoC. Pd means protection + domain. It's similar to process in Linux. Here QDSP6 processor runs each + wifi radio functionality on a separate process. One process can't access + other process resources, so this is termed as PD i.e protection domain. + +properties: + compatible: + enum: + - qcom,ipq5018-q6-mpd + - qcom,ipq9574-q6-mpd + + reg: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + description: Firmware name of the Hexagon core + + interrupts-extended: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Shutdown Q6 + - description: Stop Q6 + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: shutdown + - const: stop + + memory-region: + items: + - description: Q6 pd reserved region + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the Modem. + +patternProperties: + "^pd-1|pd-2|pd-3": + type: object + description: + In Multipd model, WCSS pd depends on Q6 pd i.e Q6 pd should be up before + WCSS. It can be achieved by keeping wcss pd node as subnode of Q6 + device node. + + properties: + compatible: + enum: + - qcom,ipq5018-wcss-ahb-mpd + - qcom,ipq9574-wcss-ahb-mpd + - qcom,ipq5018-wcss-pcie-mpd + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Firmware name of the Hexagon core + + interrupts-extended: + items: + - description: Fatal interrupt + - description: Ready interrupt + - description: Spawn acknowledge interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: fatal + - const: ready + - const: spawn-ack + - const: stop-ack + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Shutdown WCSS pd + - description: Stop WCSS pd + - description: Spawn WCSS pd + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: shutdown + - const: stop + - const: spawn + + required: + - compatible + - firmware-name + - interrupts-extended + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + + unevaluatedProperties: false + +required: + - compatible + - firmware-name + - reg + - interrupts-extended + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + - memory-region + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-q6-mpd + then: + properties: + firmware-name: + items: + - const: IPQ5018/q6_fw.mdt + - const: IPQ5018/m3_fw.mdt + - const: qcn6122/m3_fw.mdt + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-q6-mpd + then: + properties: + firmware-name: + items: + - const: IPQ9574/q6_fw.mdt + - const: IPQ9574/m3_fw.mdt + +unevaluatedProperties: false + +examples: + - | + #include + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq5018-q6-mpd"; + reg = <0x0cd00000 0x4040>; + firmware-name = "IPQ5018/q6_fw.mdt", + "IPQ5018/m3_fw.mdt", + "qcn6122/m3_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + + pd-1 { + compatible = "qcom,ipq5018-wcss-ahb-mpd"; + firmware-name = "IPQ5018/q6_fw.mdt"; + interrupts-extended = <&wcss_smp2p_in 8 0>, + <&wcss_smp2p_in 9 0>, + <&wcss_smp2p_in 12 0>, + <&wcss_smp2p_in 11 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + + pd-2 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + firmware-name = "IPQ5018/q6_fw.mdt"; + interrupts-extended = <&wcss_smp2p_in 16 0>, + <&wcss_smp2p_in 17 0>, + <&wcss_smp2p_in 20 0>, + <&wcss_smp2p_in 19 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 16>, + <&wcss_smp2p_out 17>, + <&wcss_smp2p_out 18>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + + pd-3 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + firmware-name = "IPQ5018/q6_fw.mdt"; + interrupts-extended = <&wcss_smp2p_in 24 0>, + <&wcss_smp2p_in 25 0>, + <&wcss_smp2p_in 28 0>, + <&wcss_smp2p_in 27 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 24>, + <&wcss_smp2p_out 25>, + <&wcss_smp2p_out 26>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + }; From patchwork Sun May 21 22:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2149EC7EE2D for ; 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Sun, 21 May 2023 22:29:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMTU5S011992 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:30 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:23 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 02/13] dt-bindings: mailbox: qcom: Add IPQ5018 APCS compatible Date: Mon, 22 May 2023 03:58:41 +0530 Message-ID: <20230521222852.5740-3-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pTYfU-PZquQsRerAw5KiGG79M5_pACiH X-Proofpoint-ORIG-GUID: pTYfU-PZquQsRerAw5KiGG79M5_pACiH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 suspectscore=0 mlxlogscore=981 priorityscore=1501 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210202 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add compatible for the Qualcomm IPQ5018 APCS block. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Krzysztof Kozlowski --- Changes in V2: - As suggested by Kathirvan & Krzysztof, used fallback mechanism similar to IPQ5332 .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 32d7bbc98cac..d2e25ff6db7f 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - qcom,ipq5018-apcs-apps-global - qcom,ipq5332-apcs-apps-global - qcom,ipq8074-apcs-apps-global - qcom,ipq9574-apcs-apps-global From patchwork Sun May 21 22:28:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A771AC7EE26 for ; Sun, 21 May 2023 22:29:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230033AbjEUW3v (ORCPT ); Sun, 21 May 2023 18:29:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbjEUW3s (ORCPT ); Sun, 21 May 2023 18:29:48 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52B10FA; Sun, 21 May 2023 15:29:43 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMML31028912; Sun, 21 May 2023 22:29:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=AlR4QyVfcIgJ6x55mNFmT3exos4scNjNlpCxwzjxjLA=; b=ndrnh7htsRu40q7uHlzngz2PvdVbLwQ0jbX9D2DDiIkkiJ9SccQQL7t7kF1//eMIdstw Y2QqljExzqzY4inUqdSt8YxKxxRkjS+s6NVKSCzf0s4OwV1QI4F8Tv145RZYe7V3HAQb +ZYJv6ZWdOesrB/jJx/p+r/wspq1la3CeV9awVtqywwy/yNzPOuT/AoGiZnaWxqDUc17 tz8m1cmPG+WB3PNviu78SzO2rXsnGG5gLCOMoWHJBOmdLRQ+95WcEQSOo07Cg2iQhxlr 0d9Rn+FRw9/sdwyh9Fb4DvgLj4S/ylEQBtfbPJ3QNNtWEFcynjPGlbQrmICTjIWqKay3 XA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qpn7f2bn6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:39 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMTcnC000416 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:38 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:30 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 03/13] dt-bindings: arm: qcom: Document the Qualcomm rdp432-c1 board Date: Mon, 22 May 2023 03:58:42 +0530 Message-ID: <20230521222852.5740-4-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _lEeghYucllB2mwYTnq7k9-7wAS_W1XR X-Proofpoint-ORIG-GUID: _lEeghYucllB2mwYTnq7k9-7wAS_W1XR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210202 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Document the Qualcomm rdp432-c1 board based on IPQ5018 Soc. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - Renamed mp03.5-c1 to rdp432-c1 Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 33a9a97d7b5b..53ae2b6b2da6 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -337,6 +337,7 @@ properties: - items: - enum: - qcom,ipq5018-rdp432-c2 + - qcom,ipq5018-rdp432-c1 - const: qcom,ipq5018 - items: From patchwork Sun May 21 22:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B91EC77B7C for ; Sun, 21 May 2023 22:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231298AbjEUWaL (ORCPT ); Sun, 21 May 2023 18:30:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230171AbjEUWaK (ORCPT ); Sun, 21 May 2023 18:30:10 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77AA01A7; Sun, 21 May 2023 15:29:51 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMMXoU005232; Sun, 21 May 2023 22:29:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=1YCZ/5wb97tOLkbFCh5KgOXccZ7Df9knHccpxVjxQUg=; b=B7mq9Gys1KcXx3qZ7Q37m+Pl6veQNX6YeGc10Xb82Y7j64ghObvbzJI1Q68bmHP/c6zS iC/2bwgo4hSrFbGyBastLQmouc2/+hTtalG4NNguvipeA/4Omk4lwL44K+bkZqVaE/Ev Rx3ao5inG3oPtFY7CKt/oT3iTtKtNThRCCqOHwSDylvReyOES8Wqbq45n+E9w681WS8M surtnOXArXzV6f8FFL6WfUJm/Olq8YnUm11wtz0KnxMDW31c5bEa6iVwXh8EyMdOceBx Fa/B/GDPML1vgkZGIALKZbXUSLZasSPib0Z7FltlhzIZd59eBQZ5ogHIWPzEPkz91dnj Bg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qpqctt5uc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:46 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMTjNt012022 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:29:45 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:38 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 04/13] dt-bindings: clock: qcom: gcc-ipq5018: remove q6 clocks macros Date: Mon, 22 May 2023 03:58:43 +0530 Message-ID: <20230521222852.5740-5-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SYTOSjVrT9cO1ripsdvKpxxAUVgbfqBO X-Proofpoint-GUID: SYTOSjVrT9cO1ripsdvKpxxAUVgbfqBO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Since Q6 firmware takes care of bring up clocks in multipd model, remove bring up clock macros. Signed-off-by: Manikanta Mylavarapu --- include/dt-bindings/clock/qcom,gcc-ipq5018.h | 21 -------------------- 1 file changed, 21 deletions(-) -- 2.17.1 diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h index f3de2fdfeea1..89d81fa1a758 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq5018.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h @@ -74,15 +74,8 @@ #define GCC_PCIE1_AXI_S_CLK 65 #define GCC_PCIE1_PIPE_CLK 66 #define GCC_PRNG_AHB_CLK 67 -#define GCC_Q6_AXIM_CLK 68 -#define GCC_Q6_AXIM2_CLK 69 -#define GCC_Q6_AXIS_CLK 70 -#define GCC_Q6_AHB_CLK 71 -#define GCC_Q6_AHB_S_CLK 72 #define GCC_Q6_TSCTR_1TO2_CLK 73 #define GCC_Q6SS_ATBM_CLK 74 -#define GCC_Q6SS_PCLKDBG_CLK 75 -#define GCC_Q6SS_TRIG_CLK 76 #define GCC_QDSS_AT_CLK 77 #define GCC_QDSS_CFG_AHB_CLK 78 #define GCC_QDSS_DAP_AHB_CLK 79 @@ -109,7 +102,6 @@ #define GCC_SYS_NOC_PCIE1_AXI_CLK 100 #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101 #define GCC_SYS_NOC_USB0_AXI_CLK 102 -#define GCC_SYS_NOC_WCSS_AHB_CLK 103 #define GCC_UBI0_AXI_CLK 104 #define GCC_UBI0_CFG_CLK 105 #define GCC_UBI0_CORE_CLK 106 @@ -127,19 +119,6 @@ #define GCC_USB0_MOCK_UTMI_CLK 118 #define GCC_USB0_PHY_CFG_AHB_CLK 119 #define GCC_USB0_SLEEP_CLK 120 -#define GCC_WCSS_ACMT_CLK 121 -#define GCC_WCSS_AHB_S_CLK 122 -#define GCC_WCSS_AXI_M_CLK 123 -#define GCC_WCSS_AXI_S_CLK 124 -#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125 -#define GCC_WCSS_DBG_IFC_APB_CLK 126 -#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127 -#define GCC_WCSS_DBG_IFC_ATB_CLK 128 -#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129 -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130 -#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131 -#define GCC_WCSS_DBG_IFC_NTS_CLK 132 -#define GCC_WCSS_ECAHB_CLK 133 #define GCC_XO_CLK 134 #define GCC_XO_CLK_SRC 135 #define GMAC0_RX_CLK_SRC 136 From patchwork Sun May 21 22:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BA5FC7EE2D for ; Sun, 21 May 2023 22:30:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230171AbjEUWaZ (ORCPT ); Sun, 21 May 2023 18:30:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231309AbjEUWaY (ORCPT ); Sun, 21 May 2023 18:30:24 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38C3D102; Sun, 21 May 2023 15:30:01 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMTdlk029606; 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Sun, 21 May 2023 22:29:52 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:45 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 05/13] dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros Date: Mon, 22 May 2023 03:58:44 +0530 Message-ID: <20230521222852.5740-6-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: XJe5fH0wmWXDM3HOWo63yReWy0nh9KfI X-Proofpoint-GUID: XJe5fH0wmWXDM3HOWo63yReWy0nh9KfI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=989 phishscore=0 mlxscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In multipd model Q6 firmware takes care of bringup clocks, so remove them. Signed-off-by: Manikanta Mylavarapu --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 18 ------------------ 1 file changed, 18 deletions(-) -- 2.17.1 diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 8bf26d62c54f..d97a8a68fd33 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -132,16 +132,8 @@ #define GCC_NSSNOC_SNOC_1_CLK 123 #define GCC_QDSS_ETR_USB_CLK 124 #define WCSS_AHB_CLK_SRC 125 -#define GCC_Q6_AHB_CLK 126 -#define GCC_Q6_AHB_S_CLK 127 -#define GCC_WCSS_ECAHB_CLK 128 -#define GCC_WCSS_ACMT_CLK 129 -#define GCC_SYS_NOC_WCSS_AHB_CLK 130 #define WCSS_AXI_M_CLK_SRC 131 -#define GCC_ANOC_WCSS_AXI_M_CLK 132 #define QDSS_AT_CLK_SRC 133 -#define GCC_Q6SS_ATBM_CLK 134 -#define GCC_WCSS_DBG_IFC_ATB_CLK 135 #define GCC_NSSNOC_ATB_CLK 136 #define GCC_QDSS_AT_CLK 137 #define GCC_SYS_NOC_AT_CLK 138 @@ -154,27 +146,18 @@ #define QDSS_TRACECLKIN_CLK_SRC 145 #define GCC_QDSS_TRACECLKIN_CLK 146 #define QDSS_TSCTR_CLK_SRC 147 -#define GCC_Q6_TSCTR_1TO2_CLK 148 -#define GCC_WCSS_DBG_IFC_NTS_CLK 149 #define GCC_QDSS_TSCTR_DIV2_CLK 150 #define GCC_QDSS_TS_CLK 151 #define GCC_QDSS_TSCTR_DIV4_CLK 152 #define GCC_NSS_TS_CLK 153 #define GCC_QDSS_TSCTR_DIV8_CLK 154 #define GCC_QDSS_TSCTR_DIV16_CLK 155 -#define GCC_Q6SS_PCLKDBG_CLK 156 -#define GCC_Q6SS_TRIG_CLK 157 -#define GCC_WCSS_DBG_IFC_APB_CLK 158 -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159 #define GCC_QDSS_DAP_CLK 160 #define GCC_QDSS_APB2JTAG_CLK 161 #define GCC_QDSS_TSCTR_DIV3_CLK 162 #define QPIC_IO_MACRO_CLK_SRC 163 #define GCC_QPIC_IO_MACRO_CLK 164 #define Q6_AXI_CLK_SRC 165 -#define GCC_Q6_AXIM_CLK 166 -#define GCC_WCSS_Q6_TBU_CLK 167 -#define GCC_MEM_NOC_Q6_AXI_CLK 168 #define Q6_AXIM2_CLK_SRC 169 #define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170 #define GCC_NSSNOC_MEMNOC_CLK 171 @@ -199,7 +182,6 @@ #define GCC_UNIPHY2_SYS_CLK 190 #define GCC_CMN_12GPLL_SYS_CLK 191 #define GCC_NSSNOC_XO_DCD_CLK 192 -#define GCC_Q6SS_BOOT_CLK 193 #define UNIPHY_SYS_CLK_SRC 194 #define NSS_TS_CLK_SRC 195 #define GCC_ANOC_PCIE0_1LANE_M_CLK 196 From patchwork Sun May 21 22:28:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFB10C7EE23 for ; Sun, 21 May 2023 22:30:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231358AbjEUWah (ORCPT ); Sun, 21 May 2023 18:30:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231190AbjEUWag (ORCPT ); Sun, 21 May 2023 18:30:36 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59D69198; Sun, 21 May 2023 15:30:13 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMNFZc024542; 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Sun, 21 May 2023 22:30:00 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:29:53 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 06/13] clk: qcom: ipq5018: remove q6 bring up clocks Date: Mon, 22 May 2023 03:58:45 +0530 Message-ID: <20230521222852.5740-7-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: iVat257bFjWbLGtxVBieiEQbAc4IiXkr X-Proofpoint-GUID: iVat257bFjWbLGtxVBieiEQbAc4IiXkr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Since Q6 firmware takes care of it's bring up clocks in multipd model, remove from gcc driver. Signed-off-by: Manikanta Mylavarapu --- drivers/clk/qcom/gcc-ipq5018.c | 414 --------------------------------- 1 file changed, 414 deletions(-) -- 2.17.1 diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 7ac93b1d6b3f..0dab7d94a3ae 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -2225,159 +2225,6 @@ static struct clk_branch gcc_prng_ahb_clk = { }, }; -static struct clk_branch gcc_q6_ahb_clk = { - .halt_reg = 0x59138, - .clkr = { - .enable_reg = 0x59138, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_ahb_s_clk = { - .halt_reg = 0x5914C, - .clkr = { - .enable_reg = 0x5914C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_ahb_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_axim_clk = { - .halt_reg = 0x5913C, - .clkr = { - .enable_reg = 0x5913C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_axim_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_axim2_clk = { - .halt_reg = 0x59150, - .clkr = { - .enable_reg = 0x59150, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_axim2_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_axis_clk = { - .halt_reg = 0x59154, - .clkr = { - .enable_reg = 0x59154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_axis_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_tsctr_1to2_clk = { - .halt_reg = 0x59148, - .clkr = { - .enable_reg = 0x59148, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6_tsctr_1to2_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_atbm_clk = { - .halt_reg = 0x59144, - .clkr = { - .enable_reg = 0x59144, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6ss_atbm_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_pclkdbg_clk = { - .halt_reg = 0x59140, - .clkr = { - .enable_reg = 0x59140, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6ss_pclkdbg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_trig_clk = { - .halt_reg = 0x59128, - .clkr = { - .enable_reg = 0x59128, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_q6ss_trig_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_at_clk = { .halt_reg = 0x29024, .clkr = { @@ -2803,23 +2650,6 @@ static struct clk_branch gcc_sys_noc_usb0_axi_clk = { }, }; -static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { - .halt_reg = 0x26034, - .clkr = { - .enable_reg = 0x26034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_sys_noc_wcss_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_ubi0_axi_clk = { .halt_reg = 0x68200, .halt_check = BRANCH_HALT_DELAY, @@ -3134,227 +2964,6 @@ static struct clk_branch gcc_usb0_pipe_clk = { }, }; -static struct clk_branch gcc_wcss_acmt_clk = { - .halt_reg = 0x59064, - .clkr = { - .enable_reg = 0x59064, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_acmt_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_ahb_s_clk = { - .halt_reg = 0x59034, - .clkr = { - .enable_reg = 0x59034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_ahb_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_axi_m_clk = { - .halt_reg = 0x5903C, - .clkr = { - .enable_reg = 0x5903C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_axi_m_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_axi_s_clk = { - .halt_reg = 0x59068, - .clkr = { - .enable_reg = 0x59068, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wi_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { - .halt_reg = 0x59050, - .clkr = { - .enable_reg = 0x59050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { - .halt_reg = 0x59040, - .clkr = { - .enable_reg = 0x59040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { - .halt_reg = 0x59054, - .clkr = { - .enable_reg = 0x59054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { - .halt_reg = 0x59044, - .clkr = { - .enable_reg = 0x59044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { - .halt_reg = 0x59060, - .clkr = { - .enable_reg = 0x59060, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { - .halt_reg = 0x5905C, - .clkr = { - .enable_reg = 0x5905C, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_dapbus_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { - .halt_reg = 0x59058, - .clkr = { - .enable_reg = 0x59058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { - .halt_reg = 0x59048, - .clkr = { - .enable_reg = 0x59048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_ecahb_clk = { - .halt_reg = 0x59038, - .clkr = { - .enable_reg = 0x59038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { - .name = "gcc_wcss_ecahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_hw *gcc_ipq5018_hws[] = { &gpll0_out_main_div2.hw, &pcnoc_clk_src.hw, @@ -3444,15 +3053,6 @@ static struct clk_regmap *gcc_ipq5018_clks[] = { [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, - [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr, - [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr, - [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, - [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, - [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, - [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, - [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, - [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, @@ -3479,7 +3079,6 @@ static struct clk_regmap *gcc_ipq5018_clks[] = { [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr, [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr, [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr, - [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr, [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr, [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr, @@ -3497,19 +3096,6 @@ static struct clk_regmap *gcc_ipq5018_clks[] = { [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, - [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, - [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr, - [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr, - [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, - [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, - [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, [GCC_XO_CLK] = &gcc_xo_clk.clkr, [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr, From patchwork Sun May 21 22:28:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0835C7EE2E for ; Sun, 21 May 2023 22:30:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231389AbjEUWar (ORCPT ); Sun, 21 May 2023 18:30:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231190AbjEUWan (ORCPT ); Sun, 21 May 2023 18:30:43 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0260E1A5; Sun, 21 May 2023 15:30:24 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMU8lV020403; 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Sun, 21 May 2023 22:30:07 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:00 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 07/13] clk: qcom: ipq9574: remove q6 bring up clocks Date: Mon, 22 May 2023 03:58:46 +0530 Message-ID: <20230521222852.5740-8-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: xjxUvkiMRyCQd4-eRd0zvjTpuEU62pvs X-Proofpoint-GUID: xjxUvkiMRyCQd4-eRd0zvjTpuEU62pvs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 suspectscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In multipd model Q6 firmware takes care of bringup clocks, so remove them from gcc driver. Signed-off-by: Manikanta Mylavarapu --- drivers/clk/qcom/gcc-ipq9574.c | 326 --------------------------------- 1 file changed, 326 deletions(-) -- 2.17.1 diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 1245ac52a17c..e4b0304dd43e 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -2608,24 +2608,6 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = { }, }; -static struct clk_branch gcc_q6ss_boot_clk = { - .halt_reg = 0x25080, - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x25080, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_boot_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_bfdcd_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nssnoc_snoc_clk = { .halt_reg = 0x17028, .clkr = { @@ -2696,91 +2678,6 @@ static struct clk_rcg2 wcss_ahb_clk_src = { }, }; -static struct clk_branch gcc_q6_ahb_clk = { - .halt_reg = 0x25014, - .clkr = { - .enable_reg = 0x25014, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_ahb_s_clk = { - .halt_reg = 0x25018, - .clkr = { - .enable_reg = 0x25018, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_ahb_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_ecahb_clk = { - .halt_reg = 0x25058, - .clkr = { - .enable_reg = 0x25058, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_ecahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_acmt_clk = { - .halt_reg = 0x2505c, - .clkr = { - .enable_reg = 0x2505c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_acmt_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { - .halt_reg = 0x2e030, - .clkr = { - .enable_reg = 0x2e030, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_sys_noc_wcss_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(133333333, P_GPLL0, 6, 0, 0), @@ -2801,23 +2698,6 @@ static struct clk_rcg2 wcss_axi_m_clk_src = { }, }; -static struct clk_branch gcc_anoc_wcss_axi_m_clk = { - .halt_reg = 0x2e0a8, - .clkr = { - .enable_reg = 0x2e0a8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_anoc_wcss_axi_m_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_axi_m_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_qdss_at_clk_src[] = { F(240000000, P_GPLL4, 5, 0, 0), { } @@ -2836,40 +2716,6 @@ static struct clk_rcg2 qdss_at_clk_src = { }, }; -static struct clk_branch gcc_q6ss_atbm_clk = { - .halt_reg = 0x2501c, - .clkr = { - .enable_reg = 0x2501c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_atbm_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { - .halt_reg = 0x2503c, - .clkr = { - .enable_reg = 0x2503c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nssnoc_atb_clk = { .halt_reg = 0x17014, .clkr = { @@ -3106,40 +2952,6 @@ static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { }, }; -static struct clk_branch gcc_q6_tsctr_1to2_clk = { - .halt_reg = 0x25020, - .clkr = { - .enable_reg = 0x25020, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_tsctr_1to2_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { - .halt_reg = 0x25040, - .clkr = { - .enable_reg = 0x25040, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_tsctr_div2_clk = { .halt_reg = 0x2d044, .clkr = { @@ -3314,74 +3126,6 @@ static struct clk_branch gcc_qdss_tsctr_div16_clk = { }, }; -static struct clk_branch gcc_q6ss_pclkdbg_clk = { - .halt_reg = 0x25024, - .clkr = { - .enable_reg = 0x25024, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_pclkdbg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_trig_clk = { - .halt_reg = 0x25068, - .clkr = { - .enable_reg = 0x25068, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_trig_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { - .halt_reg = 0x25038, - .clkr = { - .enable_reg = 0x25038, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { - .halt_reg = 0x25044, - .clkr = { - .enable_reg = 0x25044, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_dapbus_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_dap_clk = { .halt_reg = 0x2d058, .clkr = { @@ -3503,58 +3247,6 @@ static struct clk_rcg2 q6_axi_clk_src = { }, }; -static struct clk_branch gcc_q6_axim_clk = { - .halt_reg = 0x2500c, - .clkr = { - .enable_reg = 0x2500c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_axim_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_q6_tbu_clk = { - .halt_reg = 0x12050, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(6), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_q6_tbu_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mem_noc_q6_axi_clk = { - .halt_reg = 0x19010, - .clkr = { - .enable_reg = 0x19010, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_mem_noc_q6_axi_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_q6_axim2_clk_src[] = { F(342857143, P_GPLL4, 3.5, 0, 0), { } @@ -4102,16 +3794,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, - [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, - [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, - [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, - [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, - [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, - [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, - [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, @@ -4124,27 +3808,18 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, - [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr, - [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, - [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, - [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, - [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, - [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, - [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr, [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr, [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, @@ -4168,7 +3843,6 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, - [GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr, [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr, [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr, [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, From patchwork Sun May 21 22:28:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50448C77B7C for ; Sun, 21 May 2023 22:30:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231372AbjEUWav (ORCPT ); Sun, 21 May 2023 18:30:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231374AbjEUWat (ORCPT ); Sun, 21 May 2023 18:30:49 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED71B106; Sun, 21 May 2023 15:30:33 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMMJ4m023140; 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Sun, 21 May 2023 22:30:15 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:07 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 08/13] firmware: qcom_scm: ipq5018: Add WCSS AHB pd support Date: Mon, 22 May 2023 03:58:47 +0530 Message-ID: <20230521222852.5740-9-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _Y6t_qYZjboKxdPhmdHXt2gNOWXIidGy X-Proofpoint-GUID: _Y6t_qYZjboKxdPhmdHXt2gNOWXIidGy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add support to power up, down & load userpd firmware. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - This patch is generated by Strip off SCM code changes from here https://lore.kernel.org/linux-arm-msm/1678164097-13247-9-git-send-email-quic_mmanikan@quicinc.com/ drivers/firmware/qcom_scm.c | 114 +++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 6 ++ include/linux/firmware/qcom/qcom_scm.h | 3 + 3 files changed, 123 insertions(+) -- 2.17.1 diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index fde33acd46b7..c617e9e671ec 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -643,6 +643,120 @@ int qcom_scm_pas_shutdown(u32 peripheral) } EXPORT_SYMBOL(qcom_scm_pas_shutdown); +/** + * qti_scm_int_radio_powerup - Bring up WCSS AHB userpd + * + * @peripheral: peripheral id + * + * Return 0 on success. + */ +int qti_scm_int_radio_powerup(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_INT_RAD_PWR_UP_CMD_ID, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_int_radio_powerup); + +/** + * qti_scm_int_radio_powerdown() - Shut down WCSS AHB userpd + * + * @peripheral: peripheral id + * + * Returns 0 on success. + */ +int qti_scm_int_radio_powerdown(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_INT_RAD_PWR_DN_CMD_ID, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_int_radio_powerdown); + +/** + * qti_scm_pdseg_memcpy_v2() - copy userpd PIL segments data to dma blocks + * + * @peripheral: peripheral id + * @phno: program header no + * @dma: handle of dma region + * @seg_cnt: no of dma blocks + * + * Returns 0 if trustzone successfully loads userpd PIL segments from dma + * blocks to DDR + */ +int qti_scm_pdseg_memcpy_v2(u32 peripheral, int phno, dma_addr_t dma, + int seg_cnt) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_PD_LOAD_SVC_ID, + .cmd = QCOM_SCM_PD_LOAD_V2_CMD_ID, + .arginfo = QCOM_SCM_ARGS(4, QCOM_SCM_VAL, QCOM_SCM_VAL, + QCOM_SCM_RW, QCOM_SCM_VAL), + .args[0] = peripheral, + .args[1] = phno, + .args[2] = dma, + .args[3] = seg_cnt, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qti_scm_pdseg_memcpy_v2); + /** * qcom_scm_pas_supported() - Check if the peripheral authentication service is * available for the given peripherial diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index e6e512bd57d1..99e3ab2f1986 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -132,6 +132,12 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 +#define QCOM_SCM_PD_LOAD_SVC_ID 0x2 +#define QCOM_SCM_PD_LOAD_CMD_ID 0x16 +#define QCOM_SCM_PD_LOAD_V2_CMD_ID 0x19 +#define QCOM_SCM_INT_RAD_PWR_UP_CMD_ID 0x17 +#define QCOM_SCM_INT_RAD_PWR_DN_CMD_ID 0x18 + #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 250ea4efb7cb..488d6eccb5a4 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -81,6 +81,9 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, extern int qcom_scm_pas_auth_and_reset(u32 peripheral); extern int qcom_scm_pas_shutdown(u32 peripheral); extern bool qcom_scm_pas_supported(u32 peripheral); +int qti_scm_int_radio_powerup(u32 peripheral); +int qti_scm_int_radio_powerdown(u32 peripheral); +int qti_scm_pdseg_memcpy_v2(u32 peripheral, int phno, dma_addr_t dma, int seg_cnt); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); From patchwork Sun May 21 22:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28009C77B7C for ; Sun, 21 May 2023 22:31:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231394AbjEUWbA (ORCPT ); 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Sun, 21 May 2023 22:30:23 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMUMlS000915 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:30:22 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:15 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 09/13] remoteproc: qcom: q6v5: Add multipd interrupts support Date: Mon, 22 May 2023 03:58:48 +0530 Message-ID: <20230521222852.5740-10-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Wsyddai1_M2kw62Enx6NNIh9vxwDvtZI X-Proofpoint-ORIG-GUID: Wsyddai1_M2kw62Enx6NNIh9vxwDvtZI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 spamscore=0 impostorscore=0 mlxscore=0 adultscore=0 suspectscore=0 priorityscore=1501 phishscore=0 mlxlogscore=830 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In multipd model, root & user pd remoteproc's interrupts are different. User pd needs additional interrupts like spawn. Instead of going with qcom_q6v5_init(), we defined a new function to register userpd rproc interrupts in mpd driver. Since userpd rproc uses some of common interrupts like fatal, ready, static is removed from ISR handler and used in userpd interrupt registration. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - This patch is generated by Strip off qcom_q6v5 changes from here https://lore.kernel.org/linux-arm-msm/1678164097-13247-9-git-send-email-quic_mmanikan@quicinc.com/ drivers/remoteproc/qcom_q6v5.c | 37 +++++++++++++++++++++++++++++++--- drivers/remoteproc/qcom_q6v5.h | 11 ++++++++++ 2 files changed, 45 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index 192c7aa0e39e..d535f3365865 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -118,7 +118,7 @@ static irqreturn_t q6v5_wdog_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t q6v5_fatal_interrupt(int irq, void *data) +irqreturn_t q6v5_fatal_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; size_t len; @@ -139,7 +139,7 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t q6v5_ready_interrupt(int irq, void *data) +irqreturn_t q6v5_ready_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; @@ -183,7 +183,16 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t q6v5_stop_interrupt(int irq, void *data) +irqreturn_t q6v5_spawn_interrupt(int irq, void *data) +{ + struct qcom_q6v5 *q6v5 = data; + + complete(&q6v5->spawn_done); + + return IRQ_HANDLED; +} + +irqreturn_t q6v5_stop_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; @@ -220,6 +229,28 @@ int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon) } EXPORT_SYMBOL_GPL(qcom_q6v5_request_stop); +/** + * qcom_q6v5_request_spawn() - request the remote processor to spawn + * @q6v5: reference to qcom_q6v5 context + * + * Return: 0 on success, negative errno on failure + */ +int qcom_q6v5_request_spawn(struct qcom_q6v5 *q6v5) +{ + int ret; + + ret = qcom_smem_state_update_bits(q6v5->spawn_state, + BIT(q6v5->spawn_bit), BIT(q6v5->spawn_bit)); + + ret = wait_for_completion_timeout(&q6v5->spawn_done, 5 * HZ); + + qcom_smem_state_update_bits(q6v5->spawn_state, + BIT(q6v5->spawn_bit), 0); + + return ret == 0 ? -ETIMEDOUT : 0; +} +EXPORT_SYMBOL_GPL(qcom_q6v5_request_spawn); + /** * qcom_q6v5_panic() - panic handler to invoke a stop on the remote * @q6v5: reference to qcom_q6v5 context diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h index 5a859c41896e..4e1bb1a68284 100644 --- a/drivers/remoteproc/qcom_q6v5.h +++ b/drivers/remoteproc/qcom_q6v5.h @@ -18,21 +18,27 @@ struct qcom_q6v5 { struct qcom_smem_state *state; struct qmp *qmp; + struct qcom_smem_state *shutdown_state; + struct qcom_smem_state *spawn_state; struct icc_path *path; unsigned stop_bit; + unsigned shutdown_bit; + unsigned spawn_bit; int wdog_irq; int fatal_irq; int ready_irq; int handover_irq; int stop_irq; + int spawn_irq; bool handover_issued; struct completion start_done; struct completion stop_done; + struct completion spawn_done; int crash_reason; @@ -50,7 +56,12 @@ void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5); int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5); int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5); int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon); +int qcom_q6v5_request_spawn(struct qcom_q6v5 *q6v5); int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout); unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5); +irqreturn_t q6v5_fatal_interrupt(int irq, void *data); +irqreturn_t q6v5_ready_interrupt(int irq, void *data); +irqreturn_t q6v5_spawn_interrupt(int irq, void *data); +irqreturn_t q6v5_stop_interrupt(int irq, void *data); #endif From patchwork Sun May 21 22:28:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02F74C77B7C for ; Sun, 21 May 2023 22:31:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231424AbjEUWbL (ORCPT ); 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Sun, 21 May 2023 22:30:30 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMUTY8001398 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:30:29 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:22 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 10/13] remoteproc: qcom: Add Hexagon based multipd rproc driver Date: Mon, 22 May 2023 03:58:49 +0530 Message-ID: <20230521222852.5740-11-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oyV6nQx3qiqlbJeEhukV9Sn4uPPPQ5QQ X-Proofpoint-ORIG-GUID: oyV6nQx3qiqlbJeEhukV9Sn4uPPPQ5QQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 spamscore=0 impostorscore=0 mlxscore=0 adultscore=0 suspectscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org It adds support to bring up remoteproc's on multipd model. Pd means protection domain. It's similar to process in Linux. Here QDSP6 processor runs each wifi radio functionality on a separate process. One process can't access other process resources, so this is termed as PD i.e protection domain. Here we have two pd's called root and user pd. We can correlate Root pd as root and user pd as user in linux. Root pd has more privileges than user pd. Root will provide services to user pd. From remoteproc driver perspective, root pd corresponds to QDSP6 processor bring up and user pd corresponds to Wifi radio (WCSS) bring up. Here WCSS(user) PD is dependent on Q6(root) PD, so first q6 pd should be up before wcss pd. After wcss pd goes down, q6 pd should be turned off. IPQ5018, IPQ9574 supports multipd remoteproc driver. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - Common functionalities moved to seperate patches - qcom_get_pd_asid() moved to mpd driver - Last DMA block alone memset to zero - Added diagram to show how userpd data is organized and sent to trustzone - Rewritten commit message since most of the content available in cover page - Removed 'remote_id' becuase it's not required for bring up. drivers/remoteproc/Kconfig | 20 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/qcom_common.h | 9 + drivers/remoteproc/qcom_q6v5_mpd.c | 677 ++++++++++++++++++++++++++++ drivers/soc/qcom/mdt_loader.c | 332 ++++++++++++++ include/linux/soc/qcom/mdt_loader.h | 19 + 6 files changed, 1058 insertions(+) create mode 100644 drivers/remoteproc/qcom_q6v5_mpd.c -- 2.17.1 diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index a850e9f486dd..44af5c36f67e 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -234,6 +234,26 @@ config QCOM_Q6V5_PAS CDSP (Compute DSP), MPSS (Modem Peripheral SubSystem), and SLPI (Sensor Low Power Island). +config QCOM_Q6V5_MPD + tristate "Qualcomm Hexagon based MPD model Peripheral Image Loader" + depends on OF && ARCH_QCOM + depends on QCOM_SMEM + depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n + depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n + depends on QCOM_SYSMON || QCOM_SYSMON=n + depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n + depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n + select MFD_SYSCON + select QCOM_MDT_LOADER + select QCOM_PIL_INFO + select QCOM_Q6V5_COMMON + select QCOM_RPROC_COMMON + select QCOM_SCM + help + Say y here to support the Qualcomm Secure Peripheral Image Loader + for the Hexagon based MultiPD model remote processors on e.g. IPQ5018. + This is trustZone wireless subsystem. + config QCOM_Q6V5_WCSS tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader" depends on OF && ARCH_QCOM diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 91314a9b43ce..b64051080ec1 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o +obj-$(CONFIG_QCOM_Q6V5_MPD) += qcom_q6v5_mpd.o obj-$(CONFIG_QCOM_Q6V5_MSS) += qcom_q6v5_mss.o obj-$(CONFIG_QCOM_Q6V5_PAS) += qcom_q6v5_pas.o obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o diff --git a/drivers/remoteproc/qcom_common.h b/drivers/remoteproc/qcom_common.h index 9ef4449052a9..9d9e08aac6ef 100644 --- a/drivers/remoteproc/qcom_common.h +++ b/drivers/remoteproc/qcom_common.h @@ -76,4 +76,13 @@ static inline bool qcom_sysmon_shutdown_acked(struct qcom_sysmon *sysmon) } #endif +#if IS_ENABLED(CONFIG_QCOM_Q6V5_MPD) +s8 qcom_get_pd_asid(struct device_node *node); +#else +static inline s8 qcom_get_pd_asid(struct device_node *node) +{ + return 0; +} +#endif + #endif diff --git a/drivers/remoteproc/qcom_q6v5_mpd.c b/drivers/remoteproc/qcom_q6v5_mpd.c new file mode 100644 index 000000000000..959143960350 --- /dev/null +++ b/drivers/remoteproc/qcom_q6v5_mpd.c @@ -0,0 +1,677 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Linaro Ltd. + * Copyright (C) 2014 Sony Mobile Communications AB + * Copyright (c) 2012-2018, 2021 The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qcom_common.h" +#include "qcom_q6v5.h" + +#include "remoteproc_internal.h" + +#define WCSS_CRASH_REASON 421 +#define WCSS_SMEM_HOST 1 + +#define WCNSS_PAS_ID 6 +#define MPD_WCNSS_PAS_ID 0xD + +#define BUF_SIZE 35 + +#define MAX_FIRMWARE 3 +/** + * enum state - state of a wcss (private) + * @WCSS_NORMAL: subsystem is operating normally + * @WCSS_SHUTDOWN: subsystem has been shutdown + * + */ +enum q6_wcss_state { + WCSS_NORMAL, + WCSS_SHUTDOWN, +}; + +enum { + Q6_IPQ, + WCSS_AHB_IPQ, + WCSS_PCIE_IPQ, +}; + +struct q6_wcss { + struct device *dev; + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; + struct qcom_q6v5 q6; + phys_addr_t mem_phys; + phys_addr_t mem_reloc; + void *mem_region; + size_t mem_size; + int crash_reason_smem; + s8 pd_asid; + enum q6_wcss_state state; + const struct wcss_data *desc; + const char **firmware; +}; + +struct wcss_data { + int (*init_irq)(struct qcom_q6v5 *q6, struct platform_device *pdev, + struct rproc *rproc, int crash_reason, + const char *load_state, + void (*handover)(struct qcom_q6v5 *q6)); + int crash_reason_smem; + u32 version; + const char *ssr_name; + const struct rproc_ops *ops; + bool glink_subdev_required; + bool reset_seq; + u32 pasid; + int (*mdt_load_sec)(struct device *dev, const struct firmware *fw, + const char *fw_name, int pas_id, void *mem_region, + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base); + int (*powerup_scm)(u32 peripheral); + int (*powerdown_scm)(u32 peripheral); +}; + +/** + * qcom_get_pd_asid() - get the pd asid number from DT node + * @node: device tree node + * + * Returns asid if node name has 'pd' string + */ +s8 qcom_get_pd_asid(struct device_node *node) +{ + char *str; + s8 pd_asid; + + if (!node) + return -EINVAL; + + str = strstr(node->name, "pd"); + if (!str) + return 0; + + str += strlen("pd") + 1; + return kstrtos8(str, 10, &pd_asid) ? -EINVAL : pd_asid; +} +EXPORT_SYMBOL(qcom_get_pd_asid); + +static int q6_wcss_start(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + int ret; + struct device_node *upd_np; + struct platform_device *upd_pdev; + struct rproc *upd_rproc; + struct q6_wcss *upd_wcss; + const struct wcss_data *desc = wcss->desc; + + qcom_q6v5_prepare(&wcss->q6); + + ret = qcom_scm_pas_auth_and_reset(desc->pasid); + if (ret) { + dev_err(wcss->dev, "wcss_reset failed\n"); + return ret; + } + + ret = qcom_q6v5_wait_for_start(&wcss->q6, 5 * HZ); + if (ret == -ETIMEDOUT) + dev_err(wcss->dev, "start timed out\n"); + + /* On rootpd restart still user pd wcss state's + * initialized to WCSS_SHUTDOWN and it leads to + * user pd FW load (user pd fw load should happen + * only on user pd restart, not on root pd restart). + * So bring userpd wcss state to default value. + */ + for_each_available_child_of_node(wcss->dev->of_node, upd_np) { + upd_pdev = of_find_device_by_node(upd_np); + if (!upd_pdev) + continue; + upd_rproc = platform_get_drvdata(upd_pdev); + upd_wcss = upd_rproc->priv; + upd_wcss->state = WCSS_NORMAL; + } + return ret; +} + +static int q6_wcss_spawn_pd(struct rproc *rproc) +{ + int ret; + struct q6_wcss *wcss = rproc->priv; + + ret = qcom_q6v5_request_spawn(&wcss->q6); + if (ret == -ETIMEDOUT) { + pr_err("%s spawn timedout\n", rproc->name); + return ret; + } + + ret = qcom_q6v5_wait_for_start(&wcss->q6, msecs_to_jiffies(10000)); + if (ret == -ETIMEDOUT) { + pr_err("%s start timedout\n", rproc->name); + wcss->q6.running = false; + return ret; + } + wcss->q6.running = true; + return ret; +} + +static int wcss_ahb_pcie_pd_start(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + const struct wcss_data *desc = wcss->desc; + int ret; + + if (!desc->reset_seq) + return 0; + + if (desc->powerup_scm) { + ret = desc->powerup_scm(desc->pasid); + if (ret) { + dev_err(wcss->dev, "failed to power up pd\n"); + return ret; + } + } + + ret = q6_wcss_spawn_pd(rproc); + if (ret) + return ret; + + wcss->state = WCSS_NORMAL; + return ret; +} + +static int q6_wcss_stop(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + const struct wcss_data *desc = wcss->desc; + int ret; + + ret = qcom_scm_pas_shutdown(desc->pasid); + if (ret) { + dev_err(wcss->dev, "not able to shutdown\n"); + return ret; + } + qcom_q6v5_unprepare(&wcss->q6); + + return 0; +} + +static int wcss_ahb_pcie_pd_stop(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + struct rproc *rpd_rproc = dev_get_drvdata(wcss->dev->parent); + const struct wcss_data *desc = wcss->desc; + int ret; + + if (!desc->reset_seq) + goto shut_down_rpd; + + if (rproc->state != RPROC_CRASHED && wcss->q6.stop_bit) { + ret = qcom_q6v5_request_stop(&wcss->q6, NULL); + if (ret) { + dev_err(&rproc->dev, "pd not stopped\n"); + return ret; + } + } + + if (desc->powerdown_scm) { + ret = desc->powerdown_scm(desc->pasid); + if (ret) { + dev_err(wcss->dev, "failed to power down pd\n"); + return ret; + } + } + +shut_down_rpd: + rproc_shutdown(rpd_rproc); + + wcss->state = WCSS_SHUTDOWN; + return 0; +} + +static void *q6_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len, + bool *is_iomem) +{ + struct q6_wcss *wcss = rproc->priv; + int offset; + + offset = da - wcss->mem_reloc; + if (offset < 0 || offset + len > wcss->mem_size) + return NULL; + + return wcss->mem_region + offset; +} + +static int q6_wcss_load(struct rproc *rproc, const struct firmware *fw) +{ + struct q6_wcss *wcss = rproc->priv; + const struct firmware *fw_hdl; + int ret; + const struct wcss_data *desc = wcss->desc; + int loop; + + ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware, + desc->pasid, wcss->mem_region, + wcss->mem_phys, wcss->mem_size, + &wcss->mem_reloc); + if (ret) + return ret; + + for (loop = 1; loop < MAX_FIRMWARE; loop++) { + if (!wcss->firmware[loop]) + continue; + + ret = request_firmware(&fw_hdl, wcss->firmware[loop], + wcss->dev); + if (ret) + continue; + + ret = qcom_mdt_load_no_init(wcss->dev, fw_hdl, + wcss->firmware[loop], 0, + wcss->mem_region, + wcss->mem_phys, + wcss->mem_size, + &wcss->mem_reloc); + + release_firmware(fw_hdl); + + if (ret) { + dev_err(wcss->dev, + "can't load %s ret:%d\n", wcss->firmware[loop], ret); + return ret; + } + } + return 0; +} + +/* This function load's userpd firmware. Since Userpd depends on rootpd + * first bring up root pd and then load. User pd firmware load is required + * only during user pd restart because root pd loads user pd FW pil segments + * during it's bringup. + */ +static int wcss_ahb_pcie_pd_load(struct rproc *rproc, const struct firmware *fw) +{ + struct q6_wcss *wcss = rproc->priv, *wcss_rpd; + struct rproc *rpd_rproc = dev_get_drvdata(wcss->dev->parent); + const struct wcss_data *desc = wcss->desc; + int ret; + + wcss_rpd = rpd_rproc->priv; + + /* Boot rootpd rproc */ + ret = rproc_boot(rpd_rproc); + if (ret || wcss->state == WCSS_NORMAL) + return ret; + + return desc->mdt_load_sec(wcss->dev, fw, rproc->firmware, + desc->pasid, wcss->mem_region, + wcss->mem_phys, wcss->mem_size, + &wcss->mem_reloc); +} + +static unsigned long q6_wcss_panic(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + + return qcom_q6v5_panic(&wcss->q6); +} + +static const struct rproc_ops wcss_ahb_pcie_ipq5018_ops = { + .start = wcss_ahb_pcie_pd_start, + .stop = wcss_ahb_pcie_pd_stop, + .load = wcss_ahb_pcie_pd_load, +}; + +static const struct rproc_ops q6_wcss_ipq5018_ops = { + .start = q6_wcss_start, + .stop = q6_wcss_stop, + .da_to_va = q6_wcss_da_to_va, + .load = q6_wcss_load, + .get_boot_addr = rproc_elf_get_boot_addr, + .panic = q6_wcss_panic, +}; + +static int q6_alloc_memory_region(struct q6_wcss *wcss) +{ + struct reserved_mem *rmem = NULL; + struct device_node *node; + struct device *dev = wcss->dev; + const struct wcss_data *desc = wcss->desc; + + if (desc->version == Q6_IPQ) { + node = of_parse_phandle(dev->of_node, "memory-region", 0); + if (node) + rmem = of_reserved_mem_lookup(node); + + of_node_put(node); + + if (!rmem) { + dev_err(dev, "unable to acquire memory-region\n"); + return -EINVAL; + } + } else { + struct rproc *rpd_rproc = dev_get_drvdata(dev->parent); + struct q6_wcss *rpd_wcss = rpd_rproc->priv; + + wcss->mem_phys = rpd_wcss->mem_phys; + wcss->mem_reloc = rpd_wcss->mem_reloc; + wcss->mem_size = rpd_wcss->mem_size; + wcss->mem_region = rpd_wcss->mem_region; + return 0; + } + + wcss->mem_phys = rmem->base; + wcss->mem_reloc = rmem->base; + wcss->mem_size = rmem->size; + wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); + if (!wcss->mem_region) { + dev_err(dev, "unable to map memory region: %pa+%pa\n", + &rmem->base, &rmem->size); + return -EBUSY; + } + + return 0; +} + +static int q6_get_inbound_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, + const char *int_name, + irqreturn_t (*handler)(int irq, void *data)) +{ + int ret, irq; + char *interrupt, *tmp = (char *)int_name; + struct q6_wcss *wcss = q6->rproc->priv; + + irq = platform_get_irq_byname(pdev, int_name); + if (irq < 0) { + if (irq != -EPROBE_DEFER) + dev_err(&pdev->dev, + "failed to retrieve %s IRQ: %d\n", + int_name, irq); + return irq; + } + + if (!strcmp(int_name, "fatal")) { + q6->fatal_irq = irq; + } else if (!strcmp(int_name, "stop-ack")) { + q6->stop_irq = irq; + tmp = "stop_ack"; + } else if (!strcmp(int_name, "ready")) { + q6->ready_irq = irq; + } else if (!strcmp(int_name, "handover")) { + q6->handover_irq = irq; + } else if (!strcmp(int_name, "spawn-ack")) { + q6->spawn_irq = irq; + tmp = "spawn_ack"; + } else { + dev_err(&pdev->dev, "unknown interrupt\n"); + return -EINVAL; + } + + interrupt = devm_kzalloc(&pdev->dev, BUF_SIZE, GFP_KERNEL); + if (!interrupt) + return -ENOMEM; + + snprintf(interrupt, BUF_SIZE, "q6v5_wcss_userpd%d_%s", wcss->pd_asid, tmp); + + ret = devm_request_threaded_irq(&pdev->dev, irq, + NULL, handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + interrupt, q6); + if (ret) { + dev_err(&pdev->dev, "failed to acquire %s irq\n", interrupt); + return ret; + } + return 0; +} + +static int q6_get_outbound_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, + const char *int_name) +{ + struct qcom_smem_state *tmp_state; + unsigned bit; + + tmp_state = qcom_smem_state_get(&pdev->dev, int_name, &bit); + if (IS_ERR(tmp_state)) { + dev_err(&pdev->dev, "failed to acquire %s state\n", int_name); + return PTR_ERR(tmp_state); + } + + if (!strcmp(int_name, "stop")) { + q6->state = tmp_state; + q6->stop_bit = bit; + } else if (!strcmp(int_name, "spawn")) { + q6->spawn_state = tmp_state; + q6->spawn_bit = bit; + } + + return 0; +} + +static int init_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, struct rproc *rproc, + int crash_reason, const char *load_state, + void (*handover)(struct qcom_q6v5 *q6)) +{ + int ret; + + q6->rproc = rproc; + q6->dev = &pdev->dev; + q6->crash_reason = crash_reason; + q6->handover = handover; + + init_completion(&q6->start_done); + init_completion(&q6->stop_done); + init_completion(&q6->spawn_done); + + ret = q6_get_inbound_irq(q6, pdev, "fatal", + q6v5_fatal_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "ready", + q6v5_ready_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "stop-ack", + q6v5_stop_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "spawn-ack", + q6v5_spawn_interrupt); + if (ret) + return ret; + + ret = q6_get_outbound_irq(q6, pdev, "stop"); + if (ret) + return ret; + + ret = q6_get_outbound_irq(q6, pdev, "spawn"); + if (ret) + return ret; + + return 0; +} + +static int q6_wcss_probe(struct platform_device *pdev) +{ + const struct wcss_data *desc; + struct q6_wcss *wcss; + struct rproc *rproc; + int ret; + char *subdev_name; + const char **firmware; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + firmware = devm_kcalloc(&pdev->dev, MAX_FIRMWARE, + sizeof(*firmware), GFP_KERNEL); + if (!firmware) + return -ENOMEM; + + ret = of_property_read_string_array(pdev->dev.of_node, "firmware-name", + firmware, MAX_FIRMWARE); + if (ret < 0) + return ret; + + rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops, + firmware[0], sizeof(*wcss)); + if (!rproc) { + dev_err(&pdev->dev, "failed to allocate rproc\n"); + return -ENOMEM; + } + wcss = rproc->priv; + wcss->dev = &pdev->dev; + wcss->desc = desc; + wcss->firmware = firmware; + + ret = q6_alloc_memory_region(wcss); + if (ret) + goto free_rproc; + + wcss->pd_asid = qcom_get_pd_asid(wcss->dev->of_node); + if (wcss->pd_asid < 0) + goto free_rproc; + + if (desc->init_irq) { + ret = desc->init_irq(&wcss->q6, pdev, rproc, + desc->crash_reason_smem, NULL, NULL); + if (ret) + goto free_rproc; + } + + if (desc->glink_subdev_required) + qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ssr_name); + + subdev_name = (char *)(desc->ssr_name ? desc->ssr_name : pdev->name); + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, subdev_name); + + rproc->auto_boot = false; + ret = rproc_add(rproc); + if (ret) + goto free_rproc; + + platform_set_drvdata(pdev, rproc); + + ret = of_platform_populate(wcss->dev->of_node, NULL, + NULL, wcss->dev); + if (ret) { + dev_err(&pdev->dev, "failed to populate wcss pd nodes\n"); + goto free_rproc; + } + return 0; + +free_rproc: + rproc_free(rproc); + + return ret; +} + +static int q6_wcss_remove(struct platform_device *pdev) +{ + struct rproc *rproc = platform_get_drvdata(pdev); + struct q6_wcss *wcss = rproc->priv; + + qcom_q6v5_deinit(&wcss->q6); + + rproc_del(rproc); + rproc_free(rproc); + + return 0; +} + +static const struct wcss_data q6_ipq5018_res_init = { + .init_irq = qcom_q6v5_init, + .crash_reason_smem = WCSS_CRASH_REASON, + .ssr_name = "q6wcss", + .ops = &q6_wcss_ipq5018_ops, + .version = Q6_IPQ, + .glink_subdev_required = true, + .pasid = MPD_WCNSS_PAS_ID, +}; + +static const struct wcss_data q6_ipq9574_res_init = { + .init_irq = qcom_q6v5_init, + .crash_reason_smem = WCSS_CRASH_REASON, + .ssr_name = "q6wcss", + .ops = &q6_wcss_ipq5018_ops, + .version = Q6_IPQ, + .glink_subdev_required = true, + .pasid = WCNSS_PAS_ID, +}; + +static const struct wcss_data wcss_ahb_ipq5018_res_init = { + .init_irq = init_irq, + .crash_reason_smem = WCSS_CRASH_REASON, + .ops = &wcss_ahb_pcie_ipq5018_ops, + .version = WCSS_AHB_IPQ, + .pasid = MPD_WCNSS_PAS_ID, + .reset_seq = true, + .mdt_load_sec = qcom_mdt_load_pd_seg, + .powerup_scm = qti_scm_int_radio_powerup, + .powerdown_scm = qti_scm_int_radio_powerdown, +}; + +static const struct wcss_data wcss_ahb_ipq9574_res_init = { + .crash_reason_smem = WCSS_CRASH_REASON, + .ops = &wcss_ahb_pcie_ipq5018_ops, + .version = WCSS_AHB_IPQ, + .pasid = WCNSS_PAS_ID, + .mdt_load_sec = qcom_mdt_load, +}; + +static const struct wcss_data wcss_pcie_ipq5018_res_init = { + .init_irq = init_irq, + .crash_reason_smem = WCSS_CRASH_REASON, + .ops = &wcss_ahb_pcie_ipq5018_ops, + .version = WCSS_PCIE_IPQ, + .reset_seq = true, + .mdt_load_sec = qcom_mdt_load_pd_seg, + .pasid = MPD_WCNSS_PAS_ID, +}; + +static const struct of_device_id q6_wcss_of_match[] = { + { .compatible = "qcom,ipq5018-q6-mpd", .data = &q6_ipq5018_res_init }, + { .compatible = "qcom,ipq9574-q6-mpd", .data = &q6_ipq9574_res_init }, + { .compatible = "qcom,ipq5018-wcss-ahb-mpd", + .data = &wcss_ahb_ipq5018_res_init }, + { .compatible = "qcom,ipq9574-wcss-ahb-mpd", + .data = &wcss_ahb_ipq9574_res_init }, + { .compatible = "qcom,ipq5018-wcss-pcie-mpd", + .data = &wcss_pcie_ipq5018_res_init }, + { }, +}; +MODULE_DEVICE_TABLE(of, q6_wcss_of_match); + +static struct platform_driver q6_wcss_driver = { + .probe = q6_wcss_probe, + .remove = q6_wcss_remove, + .driver = { + .name = "qcom-q6-mpd", + .of_match_table = q6_wcss_of_match, + }, +}; +module_platform_driver(q6_wcss_driver); + +MODULE_DESCRIPTION("Hexagon WCSS Multipd Peripheral Image Loader"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 33dd8c315eb7..ab7f60cceafc 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -16,6 +16,56 @@ #include #include #include +#include + +#include "../../remoteproc/qcom_common.h" +#define PDSEG_PAS_ID 0xD + +/** + * struct region - structure passed to TrustZone + * @addr: address of dma region, where dma blocks/chunks address resides + * @blk_size: size of each block + */ +struct region { + u64 addr; + unsigned int blk_size; +}; + +/** + * struct pdseg_dma_mem_info + * @tz_addr: reference to structure passed to trustzone + * @blocks: no of blocks + * @tz_dma: dma handle of tz_addr + * @dma_blk_arr_addr_phys: dma handle of dma_blk_arr_addr + * @dma_blk_arr_addr: VA of dma array, where each index points to + * dma block PA + * @pt: stores VA of each block + * + * + ---- ---- ---- + DMA | | | | | | + blocks ---- ---- ---- + | | | + |-----| | |------- + | | | + Array of -------------- + pointers | | | | dma_blk_arr_addr_phys + -------------- + | + | + Address referred tz_addr->addr + by trustzone + to get dma blocks + */ + +struct pdseg_dma_mem_info { + struct region *tz_addr; + int blocks; + dma_addr_t tz_dma; + dma_addr_t dma_blk_arr_addr_phys; + u64 *dma_blk_arr_addr; + void **pt; +}; static bool mdt_phdr_valid(const struct elf32_phdr *phdr) { @@ -358,6 +408,261 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, return ret; } +static int allocate_dma_mem(struct device *dev, + struct pdseg_dma_mem_info *pd_dma, + int max_size) +{ + dma_addr_t dma_tmp = 0; + int i; + + pd_dma->blocks = DIV_ROUND_UP(max_size, PAGE_SIZE); + + /* Allocate dma memory for structure passed to trust zone */ + pd_dma->tz_addr = dma_alloc_coherent(dev, sizeof(struct region), + &pd_dma->tz_dma, GFP_DMA); + if (!pd_dma->tz_addr) { + pr_err("Error in dma alloc\n"); + return -ENOMEM; + } + + /* Allocate dma memory to store array of blocks PA */ + pd_dma->dma_blk_arr_addr = + dma_alloc_coherent(dev, (pd_dma->blocks * sizeof(u64)), + &pd_dma->dma_blk_arr_addr_phys, GFP_DMA); + if (!pd_dma->dma_blk_arr_addr) { + pr_err("Error in dma alloc\n"); + goto free_tz_dma_alloc; + } + + /* Assign dma block array PA to trustzone structure addr variable */ + memcpy(&pd_dma->tz_addr->addr, &pd_dma->dma_blk_arr_addr_phys, + sizeof(dma_addr_t)); + + /* Allocate memory to store array of blocks VA */ + pd_dma->pt = kzalloc(pd_dma->blocks * sizeof(void *), GFP_KERNEL); + if (!pd_dma->pt) { + pr_err("Error in memory alloc\n"); + goto free_dma_blk_arr_alloc; + } + + for (i = 0; i < pd_dma->blocks; i++) { + /* Allocate dma memory for blocks with PAGE_SIZE each */ + pd_dma->pt[i] = dma_alloc_coherent(dev, PAGE_SIZE, + &dma_tmp, GFP_DMA); + if (!pd_dma->pt[i]) { + pr_err("Error in dma alloc i:%d - blocks:%d\n", i, + pd_dma->blocks); + goto free_mem_alloc; + } + + /* Assign dma block PA to dma_blk_arr_addr */ + memcpy(&pd_dma->dma_blk_arr_addr[i], &dma_tmp, + sizeof(dma_addr_t)); + } + pd_dma->tz_addr->blk_size = PAGE_SIZE; + return 0; + +free_mem_alloc: + i = 0; + while (i < pd_dma->blocks && pd_dma->pt[i]) { + memcpy(&dma_tmp, &pd_dma->dma_blk_arr_addr[i], + sizeof(dma_addr_t)); + dma_free_coherent(dev, PAGE_SIZE, pd_dma->pt[i], dma_tmp); + i++; + } + kfree(pd_dma->pt); +free_dma_blk_arr_alloc: + dma_free_coherent(dev, (pd_dma->blocks * sizeof(u64)), + pd_dma->dma_blk_arr_addr, + pd_dma->dma_blk_arr_addr_phys); +free_tz_dma_alloc: + dma_free_coherent(dev, sizeof(struct region), pd_dma->tz_addr, + pd_dma->tz_dma); + + return -ENOMEM; +} + +static void free_dma_mem(struct device *dev, struct pdseg_dma_mem_info *pd_dma) +{ + int i; + dma_addr_t dma_tmp = 0; + + for (i = 0; i < pd_dma->blocks; i++) { + memcpy(&dma_tmp, &pd_dma->dma_blk_arr_addr[i], + sizeof(dma_addr_t)); + dma_free_coherent(dev, PAGE_SIZE, pd_dma->pt[i], + dma_tmp); + } + + dma_free_coherent(dev, (pd_dma->blocks * sizeof(u64)), + pd_dma->dma_blk_arr_addr, + pd_dma->dma_blk_arr_addr_phys); + + dma_free_coherent(dev, sizeof(struct region), pd_dma->tz_addr, + pd_dma->tz_dma); + kfree(pd_dma->pt); +} + +static int memcpy_pdseg_to_dma_blk(const char *fw_name, struct device *dev, + int ph_no, struct pdseg_dma_mem_info *pd_dma) +{ + const struct firmware *seg_fw; + int ret, offset_tmp = 0, tmp = 0; + size_t size = 0; + + ret = request_firmware(&seg_fw, fw_name, dev); + if (ret) { + dev_err(dev, "failed to load %s\n", fw_name); + return ret; + } + size = seg_fw->size < PAGE_SIZE ? + seg_fw->size : PAGE_SIZE; + while (tmp < pd_dma->blocks && size) { + /* Clear last block and copy data */ + if ((tmp + 1) == pd_dma->blocks) + memset_io(pd_dma->pt[tmp], 0, PAGE_SIZE); + memcpy_toio(pd_dma->pt[tmp], seg_fw->data + offset_tmp, size); + tmp++; + offset_tmp += size; + if ((seg_fw->size - offset_tmp) < PAGE_SIZE) + size = seg_fw->size - offset_tmp; + } + release_firmware(seg_fw); + ret = qti_scm_pdseg_memcpy_v2(PDSEG_PAS_ID, ph_no, pd_dma->tz_dma, + tmp); + if (ret) { + dev_err(dev, "pd seg memcpy scm failed\n"); + return ret; + } + return ret; +} + +static int __qcom_mdt_load_pd_seg(struct device *dev, const struct firmware *fw, + const char *fw_name, int pas_id, void *mem_region, + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base, bool pas_init) +{ + const struct elf32_phdr *phdrs; + const struct elf32_phdr *phdr; + const struct elf32_hdr *ehdr; + phys_addr_t mem_reloc; + phys_addr_t min_addr = PHYS_ADDR_MAX; + ssize_t offset; + bool relocate = false; + int ret = 0; + int i; + u8 pd_asid; + int max_size = 0; + struct pdseg_dma_mem_info pd_dma = {0}; + char *firmware_name; + size_t fw_name_len = strlen(fw_name); + + if (!fw || !mem_region || !mem_phys || !mem_size) + return -EINVAL; + + firmware_name = kstrdup(fw_name, GFP_KERNEL); + if (!firmware_name) + return -ENOMEM; + + pd_asid = qcom_get_pd_asid(dev->of_node); + + ehdr = (struct elf32_hdr *)fw->data; + phdrs = (struct elf32_phdr *)(ehdr + 1); + + for (i = 0; i < ehdr->e_phnum; i++) { + phdr = &phdrs[i]; + + if (!mdt_phdr_valid(phdr)) + continue; + /* + * While doing PD specific reloading, load only that PD + * specific writeable entries. Skip others + */ + if ((QCOM_MDT_PF_ASID(phdr->p_flags) != pd_asid) || + ((phdr->p_flags & PF_W) == 0)) + continue; + + if (phdr->p_flags & QCOM_MDT_RELOCATABLE) + relocate = true; + + if (phdr->p_paddr < min_addr) + min_addr = phdr->p_paddr; + + if (max_size < phdr->p_memsz) + max_size = phdr->p_memsz; + } + + /** + * During userpd PIL segments reloading, Q6 is live. Due to + * this we can't access memory region of PIL segments. So + * create DMA chunks/blocks to store PIL segments data. + */ + ret = allocate_dma_mem(dev, &pd_dma, max_size); + if (ret) + goto out; + + if (relocate) { + /* + * The image is relocatable, so offset each segment based on + * the lowest segment address. + */ + mem_reloc = min_addr; + } else { + /* + * Image is not relocatable, so offset each segment based on + * the allocated physical chunk of memory. + */ + mem_reloc = mem_phys; + } + + for (i = 0; i < ehdr->e_phnum; i++) { + phdr = &phdrs[i]; + + if (!mdt_phdr_valid(phdr)) + continue; + + /* + * While doing PD specific reloading, load only that PD + * specific writeable entries. Skip others + */ + if ((QCOM_MDT_PF_ASID(phdr->p_flags) != pd_asid) || + ((phdr->p_flags & PF_W) == 0)) + continue; + + offset = phdr->p_paddr - mem_reloc; + if (offset < 0 || offset + phdr->p_memsz > mem_size) { + dev_err(dev, "segment outside memory range\n"); + ret = -EINVAL; + break; + } + + if (phdr->p_filesz > phdr->p_memsz) { + dev_err(dev, + "refusing to load segment %d with p_filesz > p_memsz\n", + i); + ret = -EINVAL; + break; + } + + if (phdr->p_filesz) { + snprintf(firmware_name + fw_name_len - 3, 4, "b%02d", i); + + /* copy PIL segments data to dma blocks */ + ret = memcpy_pdseg_to_dma_blk(firmware_name, dev, i, &pd_dma); + if (ret) + goto free_dma; + } + } +free_dma: + free_dma_mem(dev, &pd_dma); + +out: + if (reloc_base) + *reloc_base = mem_reloc; + + return ret; +} + /** * qcom_mdt_load() - load the firmware which header is loaded as fw * @dev: device handle to associate resources with @@ -410,5 +715,32 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, } EXPORT_SYMBOL_GPL(qcom_mdt_load_no_init); +/** + * qcom_mdt_load_pd_seg() - load userpd specific PIL segements + * @dev: device handle to associate resources with + * @fw: firmware object for the mdt file + * @firmware: name of the firmware, for construction of segment file names + * @pas_id: PAS identifier + * @mem_region: allocated memory region to load firmware into + * @mem_phys: physical address of allocated memory region + * @mem_size: size of the allocated memory region + * @reloc_base: adjusted physical address after relocation + * + * Here userpd PIL segements are stitched with rootpd firmware. + * This function reloads userpd specific PIL segments during SSR + * of userpd. + * + * Returns 0 on success, negative errno otherwise. + */ +int qcom_mdt_load_pd_seg(struct device *dev, const struct firmware *fw, + const char *firmware, int pas_id, void *mem_region, + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base) +{ + return __qcom_mdt_load_pd_seg(dev, fw, firmware, pas_id, mem_region, mem_phys, + mem_size, reloc_base, true); +} +EXPORT_SYMBOL_GPL(qcom_mdt_load_pd_seg); + MODULE_DESCRIPTION("Firmware parser for Qualcomm MDT format"); MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/mdt_loader.h index 9e8e60421192..57021236dfc9 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -7,6 +7,11 @@ #define QCOM_MDT_TYPE_MASK (7 << 24) #define QCOM_MDT_TYPE_HASH (2 << 24) #define QCOM_MDT_RELOCATABLE BIT(27) +#define QCOM_MDT_ASID_MASK 0xfu +#define QCOM_MDT_PF_ASID_SHIFT 16 +#define QCOM_MDT_PF_ASID_MASK (QCOM_MDT_ASID_MASK << QCOM_MDT_PF_ASID_SHIFT) +#define QCOM_MDT_PF_ASID(x) \ + (((x) >> QCOM_MDT_PF_ASID_SHIFT) & QCOM_MDT_ASID_MASK) struct device; struct firmware; @@ -27,6 +32,10 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base); +int qcom_mdt_load_pd_seg(struct device *dev, const struct firmware *fw, + const char *firmware, int pas_id, void *mem_region, + phys_addr_t mem_phys, size_t mem_size, + phys_addr_t *reloc_base); void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len, const char *fw_name, struct device *dev); @@ -62,6 +71,16 @@ static inline int qcom_mdt_load_no_init(struct device *dev, return -ENODEV; } +static inline int qcom_mdt_load_pd_seg(struct device *dev, + const struct firmware *fw, + const char *fw_name, int pas_id, + void *mem_region, phys_addr_t mem_phys, + size_t mem_size, + phys_addr_t *reloc_base) +{ + return -ENODEV; +} + static inline void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len, const char *fw_name, struct device *dev) From patchwork Sun May 21 22:28:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3C15C7EE30 for ; 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Sun, 21 May 2023 22:30:38 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMUbvG001421 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:30:37 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:30 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 11/13] arm64: dtsi: qcom: ipq5018: enable nodes required for multipd Date: Mon, 22 May 2023 03:58:50 +0530 Message-ID: <20230521222852.5740-12-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JTtRzheAr9v5Y0EwewG3a5y_PyJ__gly X-Proofpoint-GUID: JTtRzheAr9v5Y0EwewG3a5y_PyJ__gly X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 mlxlogscore=853 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Enable nodes required for multipd remoteproc bring up Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - Corrected syntax like alignmnet and kept nodes in sorted order. - Covered entire TCSR region. - Added 'firmware-name' property. arch/arm64/boot/dts/qcom/ipq5018.dtsi | 140 ++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 9f13d2dcdfd5..3772d54d89e4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -85,6 +85,18 @@ reg = <0x0 0x4ac00000 0x0 0x200000>; no-map; }; + + q6_region: wcnss@4b000000 { + reg = <0x0 0x4b000000 0x0 0x1700000>; + no-map; + }; + + smem@4ab00000 { + compatible = "qcom,smem"; + reg = <0x0 0x4ab00000 0x0 0x100000>; + hwlocks = <&tcsr_mutex 0>; + no-map; + }; }; soc: soc@0 { @@ -128,6 +140,12 @@ #power-domain-cells = <1>; }; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg = <0x7804000 0x1000>; @@ -181,6 +199,14 @@ }; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq5018-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + #mbox-cells = <1>; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; @@ -238,6 +264,96 @@ status = "disabled"; }; }; + + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq5018-q6-mpd"; + reg = <0x0cd00000 0x4040>; + firmware-name = "IPQ5018/q6_fw.mdt", + "IPQ5018/m3_fw.mdt", + "qcn6122/m3_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + + pd-1 { + compatible = "qcom,ipq5018-wcss-ahb-mpd"; + firmware-name = "IPQ5018/q6_fw.mdt"; + interrupts-extended = <&wcss_smp2p_in 8 0>, + <&wcss_smp2p_in 9 0>, + <&wcss_smp2p_in 12 0>, + <&wcss_smp2p_in 11 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + + pd-2 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + interrupts-extended = <&wcss_smp2p_in 16 0>, + <&wcss_smp2p_in 17 0>, + <&wcss_smp2p_in 20 0>, + <&wcss_smp2p_in 19 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 16>, + <&wcss_smp2p_out 17>, + <&wcss_smp2p_out 18>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "disabled"; + }; + + pd-3 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + interrupts-extended = <&wcss_smp2p_in 24 0>, + <&wcss_smp2p_in 25 0>, + <&wcss_smp2p_in 28 0>, + <&wcss_smp2p_in 27 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 24>, + <&wcss_smp2p_out 25>, + <&wcss_smp2p_out 26>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "disabled"; + }; + }; }; timer { @@ -247,4 +363,28 @@ , ; }; + + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; From patchwork Sun May 21 22:28:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A657C7EE26 for ; Sun, 21 May 2023 22:31:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231502AbjEUWbb (ORCPT ); Sun, 21 May 2023 18:31:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231487AbjEUWb1 (ORCPT ); Sun, 21 May 2023 18:31:27 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D0E719D; 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Sun, 21 May 2023 22:30:45 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMUiuH026839 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:30:44 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:37 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 12/13] arm64: dts: qcom: ipq5018: Add RDP432-c1 board support Date: Mon, 22 May 2023 03:58:51 +0530 Message-ID: <20230521222852.5740-13-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SbYtfswi2Bra9PUdrD-uffKZG38reukA X-Proofpoint-GUID: SbYtfswi2Bra9PUdrD-uffKZG38reukA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 mlxlogscore=999 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210203 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add initial device tree support for the RDP432-C1 board. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - Renamed mp03.5-c1 to RDP432-c1 - Removed boot-args - Resolved dt-binding error's arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts | 49 +++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 259bd57c6064..bb9164de75b0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts new file mode 100644 index 000000000000..7fe28d9859b0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c1.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 RDP432-C1 board device tree source + * + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5018.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C1"; + compatible = "qcom,ipq5018-rdp432-c1", "qcom,ipq5018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&q6v5_wcss { + pd-2 { + firmware-name = "IPQ5018/q6_fw.mdt"; + status = "okay"; + }; + + pd-3 { + firmware-name = "IPQ5018/q6_fw.mdt"; + status = "okay"; + }; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; From patchwork Sun May 21 22:28:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13249641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FF59C7EE23 for ; Sun, 21 May 2023 22:31:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231455AbjEUWbr (ORCPT ); Sun, 21 May 2023 18:31:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231489AbjEUWbg (ORCPT ); Sun, 21 May 2023 18:31:36 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 085351B4; Sun, 21 May 2023 15:31:17 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34LMTsta026563; Sun, 21 May 2023 22:30:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=su4pLfaYpFjRQckjSvgDjsewZEZbx868uHmkpyjso4s=; b=SDVRfjCrACNcg6LJi4tTo65n2Yg4GkY/dVr3flASoMXqmfaGaMAsamyQj8NFyS6GWPB7 sN2PeRdKbUiM453rWFu2k1URqOydZyHyjvc8DzMdimuAuj2mJtzlcfQ5ZGxsPpQI+J0O R6Y6naD7Bc/rMrz1Zae+3sYMlO8E5BOt7ynSDm14fghE+bNKr1eKlb/5ZsB3qvpL6Tcu 26DYdT3ZKvA+IDG3W/Jc7gxrBxYr/VOxmApYCLCjI6S8ZrphZMMMkdyiJFQ1sQVKwEW5 N0tFj1lhcYYi2kkxKOUO+I/03Q68UWhlTYVZQZyAAwBQfEYrMxcv6qkJhslPvxol263h 1w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qppa1a9uy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:30:53 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34LMUp36011891 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 21 May 2023 22:30:52 GMT Received: from mmanikan-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Sun, 21 May 2023 15:30:44 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH V2 13/13] arm64: dtsi: qcom: ipq9574: Add nodes to bring up multipd Date: Mon, 22 May 2023 03:58:52 +0530 Message-ID: <20230521222852.5740-14-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230521222852.5740-1-quic_mmanikan@quicinc.com> References: <20230521222852.5740-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: uYe28ZOXgSwTAqI5FOeRAdDepM7YcXwg X-Proofpoint-ORIG-GUID: uYe28ZOXgSwTAqI5FOeRAdDepM7YcXwg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-21_17,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 priorityscore=1501 spamscore=0 mlxlogscore=760 phishscore=0 impostorscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305210202 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Enable nodes required for multipd remoteproc bring up. Signed-off-by: Manikanta Mylavarapu --- Changes in V2: - Corrected syntax like alignmnet and kept nodes in sorted order. - Added 'firmware-name' property. arch/arm64/boot/dts/qcom/ipq9574.dtsi | 118 ++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 0e04549c69a5..ff0da53ba05f 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -160,6 +160,11 @@ no-map; }; + q6_region: wcnss@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x2b00000>; + no-map; + }; + smem@4aa00000 { compatible = "qcom,smem"; reg = <0x0 0x4aa00000 0x0 0x00100000>; @@ -697,6 +702,95 @@ }; }; + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq9574-q6-mpd"; + reg = <0x0cd00000 0x4040>; + firmware-name = "IPQ9574/q6_fw.mdt", + "IPQ9574/m3_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 0>, + <&wcss_smp2p_in 1 0>, + <&wcss_smp2p_in 2 0>, + <&wcss_smp2p_in 3 0>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + + pd-1 { + compatible = "qcom,ipq9574-wcss-ahb-mpd"; + firmware-name = "IPQ9574/q6_fw.mdt"; + interrupts-extended = <&wcss_smp2p_in 8 0>, + <&wcss_smp2p_in 9 0>, + <&wcss_smp2p_in 12 0>, + <&wcss_smp2p_in 11 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + + pd-2 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + interrupts-extended = <&wcss_smp2p_in 16 0>, + <&wcss_smp2p_in 17 0>, + <&wcss_smp2p_in 20 0>, + <&wcss_smp2p_in 19 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 16>, + <&wcss_smp2p_out 17>, + <&wcss_smp2p_out 18>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "disabled"; + }; + + pd-3 { + compatible = "qcom,ipq5018-wcss-pcie-mpd"; + interrupts-extended = <&wcss_smp2p_in 24 0>, + <&wcss_smp2p_in 25 0>, + <&wcss_smp2p_in 28 0>, + <&wcss_smp2p_in 27 0>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 24>, + <&wcss_smp2p_out 25>, + <&wcss_smp2p_out 26>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + status = "disabled"; + }; + }; + pcie1: pci@10000000 { compatible = "qcom,pcie-ipq9574"; reg = <0x10000000 0xf1d>, @@ -966,4 +1060,28 @@ , ; }; + + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; };