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bh=eA6w2DJkuoLkX3yICHnRN/pQE/wdeda+obKOC24tPDs=; b=WJE2M3UZnZxMFdu1wJ5ezYEwuJaxDAeDX3dZUyK68l38Kq7Z99NwyGr9mCvNTxn0CT R2+n2YMwh1KNtYJr+kt6Kuv6Hq4cMvAaZuSGul1rsJfHbzgwX9m8qtmoKTEPkMPJrTfL H/YMvs5SsFuRBdvgG4W8SFor/EAkPEUWaXxHM7EABgFdpf0zhX8tmyHybnhnzkunFxSV 8SPfKLgVW2Ksp7aSOYDkbYQ+hPPQFtFhlhZ5LAo5iJYJrBU/rGi1ZYCD+k+7i93YJ3DU jvka81hryWL5t3radI0xZBpNIgj4WtFp6a4DaObvke/bqlJZRKKFyOF4Yn4jSfsiQEps CoQQ== X-Gm-Message-State: AJcUukcsK4uvANb9mjRuNmsPJfvHX1wb1qeBvQUzSauPXTBM4mOTp50B ArEEOuxK9POArZOFh6GM/p941efSKM5bGA== X-Google-Smtp-Source: ALg8bN4sMtA5OVzCU8Ei5Qekh8jD8A7JiZQJUSJ46721yFwtfeVmBqhXnoMa/k+dETv3FkJ/hDZ3zQ== X-Received: by 2002:aa7:d1d7:: with SMTP id g23mr37674522edp.217.1549100616177; Sat, 02 Feb 2019 01:43:36 -0800 (PST) Received: from localhost ([2001:67c:1810:f051:fd32:55e2:f60b:183b]) by smtp.gmail.com with ESMTPSA id x6sm20508ejw.40.2019.02.02.01.43.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 02 Feb 2019 01:43:35 -0800 (PST) Date: Sat, 02 Feb 2019 01:43:35 -0800 (PST) X-Google-Original-Date: Sat, 02 Feb 2019 01:42:09 PST (-0800) Subject: [GIT PULL] RISC-V Fixes for 5.0-rc5 From: Palmer Dabbelt To: Linus Torvalds Message-ID: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190202_014339_498428_019A5BD1 X-CRM114-Status: GOOD ( 12.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The following changes since commit 49a57857aeea06ca831043acbb0fa5e0f50602fd: Linux 5.0-rc3 (2019-01-21 13:14:44 +1300) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-5.0-rc5 for you to fetch changes up to ae662eec8a515ab550524e04c793b5ddf1aae3a1: riscv: Adjust mmap base address at a third of task size (2019-01-25 10:50:53 -0800) ---------------------------------------------------------------- RISC-V Fixes for 5.0-rc5 This patch set contains a handful of mostly-independent patches: * A patch that causes our port to respect TIF_NEED_RESCHED, which fixes CONFIG_PREEMPT=y kernels. * A fix to avoid double-put on OF nodes. * Fix a misspelling of target in our Kconfig. * Generic PCIe is enabled in our defconfig. * A fix to our SBI early console to properly handle line endings. * A fix such that max_low_pfn is counted in PFNs. * A change to TASK_UNMAPPED_BASE to match what other arches do. This has passed by standard "boot Fedora" flow. ---------------------------------------------------------------- Alexandre Ghiti (1): riscv: Adjust mmap base address at a third of task size Alistair Francis (1): RISC-V: defconfig: Enable Generic PCIE by default Andreas Schwab (2): RISC-V: fix bad use of of_node_put tty/serial: use uart_console_write in the RISC-V SBL early console Antony Pavlov (2): RISC-V: asm/page.h: fix spelling mistake "CONFIG_64BITS" -> "CONFIG_64BIT" RISC-V: Kconfig: fix spelling mistake "traget" -> "target" Guo Ren (1): riscv: fixup max_low_pfn with PFN_DOWN. Palmer Dabbelt (2): RISC-V: defconfig: Move CONFIG_PCI{,E_XILINX} RISC-V: defconfig: Add CRYPTO_DEV_VIRTIO=y Vincent Chen (1): RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y arch/riscv/Kconfig | 2 +- arch/riscv/configs/defconfig | 8 +++++--- arch/riscv/include/asm/page.h | 2 +- arch/riscv/include/asm/processor.h | 2 +- arch/riscv/kernel/asm-offsets.c | 1 + arch/riscv/kernel/entry.S | 18 +++++++++++++++++- arch/riscv/kernel/setup.c | 2 +- arch/riscv/kernel/smpboot.c | 6 +----- arch/riscv/mm/init.c | 3 ++- drivers/tty/serial/earlycon-riscv-sbi.c | 13 ++++++++----- 10 files changed, 38 insertions(+), 19 deletions(-)