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[94.181.180.60]) by smtp.googlemail.com with ESMTPSA id c18-20020a197612000000b004f378fbb358sm1614049lff.112.2023.05.24.01.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 01:28:08 -0700 (PDT) From: Maxim Kiselev To: linux-iio@vger.kernel.org Cc: Maxim Kiselev , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Andre Przywara , Andy Shevchenko , Cosmin Tanislav , Haibo Chen , ChiYuan Huang , Ramona Bolboaca , Ibrahim Tilki , ChiaEn Wu , William Breathitt Gray , Arnd Bergmann , AngeloGioacchino Del Regno , Caleb Connolly , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC PATCH v1 1/4] iio: adc: Add Allwinner D1/T113s/R329 SoCs GPADC Date: Wed, 24 May 2023 11:27:30 +0300 Message-Id: <20230524082744.3215427-2-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230524082744.3215427-1-bigunclemax@gmail.com> References: <20230524082744.3215427-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org The General Purpose ADC (GPADC) can convert the external signal into a certain proportion of digital value, to realize the measurement of analog signal, which can be applied to power detection and key detection. D1, T113s and R329 contain this GPADC IP. The only difference between this SoCs is the number of available channels: T113 - 1 channel D1 - 2 channels R329 - 4 channels Signed-off-by: Maxim Kiselev --- drivers/iio/adc/Kconfig | 10 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/sun20i-gpadc-iio.c | 275 +++++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) create mode 100644 drivers/iio/adc/sun20i-gpadc-iio.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index eb2b09ef5d5b..988804f46bf6 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1123,6 +1123,16 @@ config SUN4I_GPADC To compile this driver as a module, choose M here: the module will be called sun4i-gpadc-iio. +config SUN20I_GPADC + tristate "Support for the Allwinner SoCs GPADC" + depends on ARCH_SUNXI || COMPILE_TEST + help + Say yes here to build support for Allwinner (D1, T113 and R329) SoCs + GPADC. This ADC provides up to 4 channels. + + To compile this driver as a module, choose M here: the module will be + called sun20i-gpadc-iio. + config TI_ADC081C tristate "Texas Instruments ADC081C/ADC101C/ADC121C family" depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index e07e4a3e6237..fc4ef71d5f8f 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o obj-$(CONFIG_SPEAR_ADC) += spear_adc.o obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o +obj-$(CONFIG_SUN20I_GPADC) += sun20i-gpadc-iio.o obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o obj-$(CONFIG_STM32_DFSDM_CORE) += stm32-dfsdm-core.o diff --git a/drivers/iio/adc/sun20i-gpadc-iio.c b/drivers/iio/adc/sun20i-gpadc-iio.c new file mode 100644 index 000000000000..90f3bb2e41cd --- /dev/null +++ b/drivers/iio/adc/sun20i-gpadc-iio.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GPADC driver for sunxi platforms (D1, T113-S3 and R329) + * Copyright (c) 2023 Maksim Kiselev + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SUN20I_GPADC_SR 0x00 + +#define SUN20I_GPADC_CTRL 0x04 +#define SUN20I_GPADC_CTRL_ADC_FIRST_DLY ((GENMASK(7, 0) & (x)) << 24) +#define SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN BIT(23) +#define SUN20I_GPADC_CTRL_ADC_OP_BIAS ((GENMASK(1, 0) & (x)) << 20) +#define SUN20I_GPADC_CTRL_WORK_MODE_SELECT(x) ((GENMASK(1, 0) & (x)) << 18) +#define SUN20I_GPADC_CTRL_ADC_CALI_EN BIT(17) +#define SUN20I_GPADC_CTRL_ADC_EN BIT(16) + +#define SUN20I_GPADC_CS_EN 0x08 +#define SUN20I_GPADC_CS_EN_ADC_CHAN_CMP_EN(x) ((GENMASK(16, 0) & BIT(x)) << 16) +#define SUN20I_GPADC_CS_EN_ADC_CHAN_SELECT(x) (GENMASK(16, 0) & BIT(x)) + +#define SUN20I_GPADC_DATA_INTC 0x28 +#define SUN20I_GPADC_DATA_INTC_CHAN_DATA_IRQ_EN(x) (GENMASK(16, 0) & BIT(x)) + +#define SUN20I_GPADC_DATA_INTS 0x38 +#define SUN20I_GPADC_DATA_INTS_DATA_PENDING(x) (GENMASK(16, 0) & BIT(x)) +#define SUN20I_GPADC_DATA_INTS_DATA_PENDING_MASK GENMASK(16, 0) + +#define SUN20I_GPADC_CHAN_DATA(x) (0x80 + (x) * 4) + +#define SUN20I_GPADC_TIMEOUT msecs_to_jiffies(100) +#define SUN20I_GPADC_MAX_CHANNELS 16 + +struct sun20i_gpadc_configuration { + const struct iio_chan_spec *channels; + u8 num_channels; +}; + +struct sun20i_gpadc_iio { + struct iio_dev *indio_dev; + struct regmap *regmap; + struct completion completion; + struct mutex lock; +}; + +#define SUN20I_GPADC_ADC_CHANNEL(_channel) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = _channel, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ +} + +static const struct iio_chan_spec sun8i_t113_gpadc_channels[] = { + SUN20I_GPADC_ADC_CHANNEL(0), +}; + +static const struct iio_chan_spec sun20i_d1_gpadc_channels[] = { + SUN20I_GPADC_ADC_CHANNEL(0), + SUN20I_GPADC_ADC_CHANNEL(1), +}; + +static const struct iio_chan_spec sun50i_r329_gpadc_channels[] = { + SUN20I_GPADC_ADC_CHANNEL(0), + SUN20I_GPADC_ADC_CHANNEL(1), + SUN20I_GPADC_ADC_CHANNEL(2), + SUN20I_GPADC_ADC_CHANNEL(3), +}; + +static const struct sun20i_gpadc_configuration sun20i_gpadc_config[] = { + { sun8i_t113_gpadc_channels, ARRAY_SIZE(sun8i_t113_gpadc_channels) }, + { sun20i_d1_gpadc_channels, ARRAY_SIZE(sun20i_d1_gpadc_channels) }, + { sun50i_r329_gpadc_channels, ARRAY_SIZE(sun50i_r329_gpadc_channels) }, +}; + +static const struct regmap_config sun20i_gpadc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static int sun20i_gpadc_adc_read(struct sun20i_gpadc_iio *info, + struct iio_chan_spec const *chan, int *val) +{ + reinit_completion(&info->completion); + + /* enable the analog input channel */ + regmap_write(info->regmap, SUN20I_GPADC_CS_EN, + SUN20I_GPADC_CS_EN_ADC_CHAN_SELECT(chan->channel)); + + /* enable the data irq for input channel */ + regmap_write(info->regmap, SUN20I_GPADC_DATA_INTC, + SUN20I_GPADC_DATA_INTC_CHAN_DATA_IRQ_EN(chan->channel)); + + /* enable the ADC function */ + regmap_update_bits(info->regmap, SUN20I_GPADC_CTRL, + SUN20I_GPADC_CTRL_ADC_EN, SUN20I_GPADC_CTRL_ADC_EN); + + if (!wait_for_completion_timeout(&info->completion, + SUN20I_GPADC_TIMEOUT)) + return -ETIMEDOUT; + + /* read the ADC data */ + regmap_read(info->regmap, SUN20I_GPADC_CHAN_DATA(chan->channel), val); + + return IIO_VAL_INT; +} + +static int sun20i_gpadc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct sun20i_gpadc_iio *info = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + mutex_lock(&info->lock); + ret = sun20i_gpadc_adc_read(info, chan, val); + mutex_unlock(&info->lock); + return ret; + case IIO_CHAN_INFO_SCALE: + /* 1800mV / 4096 * raw */ + *val = 0; + *val2 = 439453125; + return IIO_VAL_INT_PLUS_NANO; + default: + return -EINVAL; + } +} + +static irqreturn_t sun20i_gpadc_irq_handler(int irq, void *data) +{ + struct sun20i_gpadc_iio *info = data; + u32 reg; + + /* clear data interrupt status register */ + regmap_read(info->regmap, SUN20I_GPADC_DATA_INTS, ®); + regmap_write(info->regmap, SUN20I_GPADC_DATA_INTS, reg); + + complete(&info->completion); + + return IRQ_HANDLED; +} + +static const struct iio_info sun20i_gpadc_iio_info = { + .read_raw = sun20i_gpadc_read_raw, +}; + +static int sun20i_gpadc_probe(struct platform_device *pdev) +{ + const struct sun20i_gpadc_configuration *config; + struct iio_dev *indio_dev; + struct sun20i_gpadc_iio *info; + struct reset_control *rst; + void __iomem *base; + struct clk *clk; + int irq; + int ret; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); + if (!indio_dev) + return -ENOMEM; + + info = iio_priv(indio_dev); + platform_set_drvdata(pdev, indio_dev); + + mutex_init(&info->lock); + init_completion(&info->completion); + + info->indio_dev = indio_dev; + indio_dev->info = &sun20i_gpadc_iio_info; + indio_dev->name = dev_name(&pdev->dev); + + config = of_device_get_match_data(&pdev->dev); + if (!config) + return -ENODEV; + + /* Sanity check for possible later IP variants with more channels */ + if (config->num_channels > SUN20I_GPADC_MAX_CHANNELS) + return dev_err_probe(&pdev->dev, -EINVAL, + "max channels exceeded\n"); + + indio_dev->channels = config->channels; + indio_dev->num_channels = config->num_channels; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + info->regmap = devm_regmap_init_mmio(&pdev->dev, base, + &sun20i_gpadc_regmap_config); + if (IS_ERR(info->regmap)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->regmap), + "failed to init regmap\n"); + + clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk), + "failed to enable bus clock\n"); + + rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(rst), + "failed to get reset control\n"); + + ret = reset_control_deassert(rst); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to deassert reset\n"); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return dev_err_probe(&pdev->dev, irq, "failed to get irq\n"); + + ret = devm_request_irq(&pdev->dev, irq, sun20i_gpadc_irq_handler, + 0, dev_name(&pdev->dev), info); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "failed requesting irq %d\n", irq); + + /* set the single conversion mode and enable auto calibration*/ + regmap_write(info->regmap, SUN20I_GPADC_CTRL, + SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN | + SUN20I_GPADC_CTRL_WORK_MODE_SELECT(0)); + + ret = devm_iio_device_register(&pdev->dev, indio_dev); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "could not register the device\n"); + + return 0; +} + +static const struct of_device_id sun20i_gpadc_of_id[] = { + { + .compatible = "allwinner,sun8i-t113-gpadc", + .data = &sun20i_gpadc_config[0], + }, + { + .compatible = "allwinner,sun20i-d1-gpadc", + .data = &sun20i_d1_gpadc_channels[1] + }, + { + .compatible = "allwinner,sun50i-r329-gpadc", + .data = &sun50i_r329_gpadc_channels[2] + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id); + +static struct platform_driver sun20i_gpadc_driver = { + .driver = { + .name = "sun20i-gpadc-iio", + .of_match_table = sun20i_gpadc_of_id, + }, + .probe = sun20i_gpadc_probe, +}; +module_platform_driver(sun20i_gpadc_driver); + +MODULE_DESCRIPTION("ADC driver for sunxi platforms"); +MODULE_AUTHOR("Maksim Kiselev "); +MODULE_LICENSE("GPL"); From patchwork Wed May 24 08:27:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13253449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B293C77B7A for ; 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[94.181.180.60]) by smtp.googlemail.com with ESMTPSA id c18-20020a197612000000b004f378fbb358sm1614049lff.112.2023.05.24.01.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 01:28:21 -0700 (PDT) From: Maxim Kiselev To: linux-iio@vger.kernel.org Cc: Maxim Kiselev , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Andre Przywara , Heiko Stuebner , Andy Shevchenko , Cosmin Tanislav , Miquel Raynal , Alexander Sverdlin , Ramona Bolboaca , William Breathitt Gray , ChiYuan Huang , Ibrahim Tilki , Caleb Connolly , Arnd Bergmann , Mike Looijmans , ChiaEn Wu , Haibo Chen , Hugo Villeneuve , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC PATCH v1 2/4] dt-bindings: iio: adc: Add Allwinner D1/T113s/R329 SoCs GPADC Date: Wed, 24 May 2023 11:27:31 +0300 Message-Id: <20230524082744.3215427-3-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230524082744.3215427-1-bigunclemax@gmail.com> References: <20230524082744.3215427-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Allwinner's D1, T113s and R329 SoCs have a new general purpose ADC. This ADC is the same for all of this SoCs. The only difference is the number of available channels. Signed-off-by: Maxim Kiselev --- .../iio/adc/allwinner,sun20i-d1-gpadc.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml b/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml new file mode 100644 index 000000000000..a79b874750dd --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/allwinner,sun20i-d1-gpadc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1 General Purpose ADC + +properties: + "#io-channel-cells": + const: 0 + + clocks: + maxItems: 1 + + compatible: + enum: + - allwinner,sun20i-d1-gpadc + - allwinner,sun8i-t113-gpadc + - allwinner,sun50i-r329-gpadc + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - "#io-channel-cells" + - clocks + - compatible + - interrupts + - reg + - resets + +additionalProperties: false + +examples: + - | + gpadc: adc@2009000 { + compatible = "allwinner,sun20i-d1-gpadc"; + reg = <0x2009000 0x1000>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + interrupts = ; + #io-channel-cells = <0>; + }; + +... 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[94.181.180.60]) by smtp.googlemail.com with ESMTPSA id c18-20020a197612000000b004f378fbb358sm1614049lff.112.2023.05.24.01.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 01:28:34 -0700 (PDT) From: Maxim Kiselev To: linux-iio@vger.kernel.org Cc: Maxim Kiselev , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Andre Przywara , Andy Shevchenko , Cosmin Tanislav , ChiaEn Wu , Ramona Bolboaca , ChiYuan Huang , Ibrahim Tilki , Caleb Connolly , William Breathitt Gray , Arnd Bergmann , Mike Looijmans , =?utf-8?q?Leonard_G=C3=B6hrs?= , Haibo Chen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC PATCH v1 3/4] ARM: dts: sun8i: t113s: Add GPADC node Date: Wed, 24 May 2023 11:27:32 +0300 Message-Id: <20230524082744.3215427-4-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230524082744.3215427-1-bigunclemax@gmail.com> References: <20230524082744.3215427-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This patch adds declaration of the general purpose ADC with one channel for T113s SoC. Signed-off-by: Maxim Kiselev --- arch/arm/boot/dts/sun8i-t113s.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/sun8i-t113s.dtsi index 804aa197a24f..d269fdde330d 100644 --- a/arch/arm/boot/dts/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/sun8i-t113s.dtsi @@ -42,6 +42,18 @@ gic: interrupt-controller@1c81000 { #interrupt-cells = <3>; }; + soc { + gpadc: adc@2009000 { + compatible = "allwinner,sun8i-t113-gpadc"; + reg = <0x2009000 0x1000>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + interrupts = ; + status = "disabled"; + #io-channel-cells = <0>; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , From patchwork Wed May 24 08:27:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13253451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B13AC77B73 for ; Wed, 24 May 2023 08:29:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239085AbjEXI3G (ORCPT ); Wed, 24 May 2023 04:29:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239027AbjEXI3E (ORCPT ); Wed, 24 May 2023 04:29:04 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7ECF132; Wed, 24 May 2023 01:28:50 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f3b9755961so582113e87.0; Wed, 24 May 2023 01:28:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684916928; x=1687508928; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=odFoqtaACFFyMrXmxlrRHYMZnaIGXqlcjA/Yeo/eMSM=; b=Mvd/veDyjuxX8uDcTR8PI4Xqf4ovhcjx5jyKNU3IYsLv4K4TWPiwQuH7PXLRUsd1lc FyfsPiUqwOq7sGQfZ10bL3H78meCp0oJsj12w7ytR5d0mG3wDlkzIA9amxl0LHWmdIa0 nXTGfbb9SYE29Q/mKKsF9fX2N4Xee3qGLqoiTf3mpGpaRyyJf2VzepfVXB0Fj6tjE84u Wre8p0Iu75GJoNJ32N0Rhj8avsw8FRrCTbcV0NFk4oNtz1jQj3MslC3Ps8lUxtC0cQd/ 6c9GVZxKAzA3NmOekitk+/TRT6AuwtmWI3YkDMpKlpGigNvSnPkbhU9lCm7b0LEp42gX ThBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684916928; x=1687508928; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=odFoqtaACFFyMrXmxlrRHYMZnaIGXqlcjA/Yeo/eMSM=; b=EC5jYU7NWyXxMSRi3jOSknkrmtqpEzRJGFF8nYPx6OOXKZ609kEhSeCWzGDgmJHAlJ LYD4XkPZL5BJGc3H705KVioQwymuP312VAEM08ogOZ2gKifxWzHqiPsPFU6Vli6iSecd fe2/Ux+6BTBjk6U8vUR5hQSt4xehG2mYwdxNzrxSPS7OkbhmF4iWGiN69VH6tzPglg8r 5r2ZOGC5L+qlwKL/8SRdStp0qTaOAVmAIxRdHhvoy1lxOX8n1qVXGp15TmbAPxy+lOfy KJa41/OGFDiN4Dj+Gwgu0DiHYUgMru1hihjFPavW7AH78AIehA1tPkF9X5hc+PyaFNQ+ 8rRQ== X-Gm-Message-State: AC+VfDzas8pptdGBS0JOkFHIXkudCHxX4hU47giKwPu6Ghhb7+aTiqB2 0bHcueyd7jMqkLKbdFap5vfVlJEAOkSvpMUw X-Google-Smtp-Source: ACHHUZ7nTj6ZzaR2KWD9boDc/9z2PyjWBCXVB7avQ4mYjB8ldUrHEw92byKyfbq/IsC5bWV5bsz3dQ== X-Received: by 2002:ac2:596a:0:b0:4f1:3ae6:20bf with SMTP id h10-20020ac2596a000000b004f13ae620bfmr5776396lfp.1.1684916928480; Wed, 24 May 2023 01:28:48 -0700 (PDT) Received: from pc.. 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[94.181.180.60]) by smtp.googlemail.com with ESMTPSA id c18-20020a197612000000b004f378fbb358sm1614049lff.112.2023.05.24.01.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 01:28:48 -0700 (PDT) From: Maxim Kiselev To: linux-iio@vger.kernel.org Cc: Maxim Kiselev , Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Heiko Stuebner , Andre Przywara , Andy Shevchenko , Cosmin Tanislav , Marcus Folkesson , Alexander Sverdlin , Arnd Bergmann , Hugo Villeneuve , Mike Looijmans , ChiYuan Huang , Ramona Bolboaca , Ibrahim Tilki , ChiaEn Wu , William Breathitt Gray , Caleb Connolly , Haibo Chen , =?utf-8?q?Leonard_G=C3=B6hrs?= , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RFC PATCH v1 4/4] riscv: dts: allwinner: d1: Add GPADC node Date: Wed, 24 May 2023 11:27:33 +0300 Message-Id: <20230524082744.3215427-5-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230524082744.3215427-1-bigunclemax@gmail.com> References: <20230524082744.3215427-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org This patch adds declaration of the general purpose ADC with two channel for D1 SoC. Signed-off-by: Maxim Kiselev --- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi index 97e7cbb32597..b21825429cca 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi @@ -6,6 +6,16 @@ / { soc { + gpadc: adc@2009000 { + compatible = "allwinner,sun20i-d1-gpadc"; + reg = <0x2009000 0x1000>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + interrupts = ; + status = "disabled"; + #io-channel-cells = <0>; + }; + lradc: keys@2009800 { compatible = "allwinner,sun20i-d1-lradc", "allwinner,sun50i-r329-lradc";