From patchwork Fri May 26 16:59:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13257193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68958C77B7A for ; Fri, 26 May 2023 17:11:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=l0iMkZKSSoNt+7OvcmXyP6AyANLDi/EPn5+F0EkqRTA=; b=2XL0yP9/To9hNG P0knUG05PZzDTeB2VYVUMWH1akimgxfkGpnH8YX0wWZefvOlz2aynoRhC7eU4TGCkFU3oEt6biCDI NSRLgNKG7ZdQXUGfuqDu0h+n4n9/lCwT6CVPAtfSH67TXN7ZAa/kqGDACd64SMVixqyQzQKLXQQhm MYwCAOuMlXvR/Ah0hzNQJP8W2uqX1/ZVF2Kd5c96nhBpdX+KCQOA8bfEXfUc1PQs97YoLT31QCbMc SBm2Ah19txnhEGftM/EOEIEvl7kNCcQSNyH/HRJLBfmbVETMby6a59p4j/85zqW7XzD8e5sBGETcK t0iv8jgZ2kD/23L7RUBw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayC-003FdG-1t; Fri, 26 May 2023 17:11:16 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q2ay9-003Fbk-2R for linux-riscv@lists.infradead.org; Fri, 26 May 2023 17:11:14 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 56DC3651C0; Fri, 26 May 2023 17:11:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64C85C43446; Fri, 26 May 2023 17:11:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121072; bh=N+SE5apBHJdpc4kl5LVsR83pASoe466MUuKqmk4qCmY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dy9f79qlz416EP/3kBixmbxtEXL1AKGqFraAcnWqIMmty/VaLIObcEn4i3SO2uOV5 QkhwCRgI/Oay6bicOxByimULBFgUFw4j6xneFP+fsk11XbUZMlDS3mNrTjpUoqqqTz DPwGGmjWeRBgtFzQ9ouzXuhtXZ9Y46W8C6ObVWRrOdxmxoX7UOcfV9J0b5bErkxuxC ppNttvMssdEoz7kRbhRyYN6bZlp+UYB42+BkQAbnz1U92W3qY73ZMyiDf8+iCahGwg LLej5KAh21kHUwffCZrId0f8ZlWjsdXRsPwBaepbd0kjN2eSX6TmWWJEi/Am3Jq5P5 BklHbdj0qYrUw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot Date: Sat, 27 May 2023 00:59:53 +0800 Message-Id: <20230526165958.908-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230526_101113_833142_0F19E06D X-CRM114-Status: GOOD ( 10.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The CBOM size and whether the HW is noncoherent is known and determined during booting and won't change after that. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/errata/thead/errata.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index c259dc925ec1..be84b14f0118 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -45,8 +45,11 @@ static bool errata_probe_cmo(unsigned int stage, if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return false; - riscv_cbom_block_size = L1_CACHE_BYTES; - riscv_noncoherent_supported(); + if (stage == RISCV_ALTERNATIVES_BOOT) { + riscv_cbom_block_size = L1_CACHE_BYTES; + riscv_noncoherent_supported(); + } + return true; } From patchwork Fri May 26 16:59:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13257195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16C67C7EE23 for ; Fri, 26 May 2023 17:11:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/l3a+ePya7BhtbfrXboFUVD6rZD9hk/3qeLSq13K1ks=; b=LxOgM2Z6G2DLpf XHYOtXRMFhL9oVOd/pvBY4RM+1+17wRfb4dUI/RbqjHPWc843zKD5JbKGTZd7ky6NU35fYcPFQGvW ibYwEB13j1qrN1z6NVuYAEClFRn5yZYHXKC7wqZ5zKcNvibq6Voc818c1gpFY8ffn63u9enrWh5MK HQG+eZ1x9qpiAospcZmvw8g6XOI+xszqc8yKgxFgwqtp7yhjYcplbnUodVHzey94nnkjRnG3EGELT 31ccD4ru1zZT4vkRbsh/khnEMAWmzvyX7uzOtHXuBf64jnL+h48BPi1S7xkZuyA3n7miz9PtpqAk/ oZyE+Q/aUfS/tzQH76Wg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayG-003Fei-0t; Fri, 26 May 2023 17:11:20 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayB-003Fcf-1r for linux-riscv@lists.infradead.org; Fri, 26 May 2023 17:11:16 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 29AD0651BE; Fri, 26 May 2023 17:11:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 374DBC433D2; Fri, 26 May 2023 17:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121074; bh=xGXWKrOp0g9viGaeP46hlIuMnd4eCZ7qokxGpnJ/fzc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=inb6fwAeTMyK2wSbEr0nuGmmPotGctpAFAas68FOu4FXw2az1r0gk6rZbi+5aV0h5 m4OTi/vkC0xVo5GTCgTkRkG73mXt852HxHcds0NLIr1prkeDvnwR35p44PQEvIl6cy yiSGbH8nOzCslfwRqUU068U0GxfMvlzcryYaJZugLD0oW6QzFdR4E6aOzmTF8JuRDS 2E4BuuxBKV+OGh4lFzfjSK7OfQQmJG6g09pKeZsR9d5KkR2MBKUakQsKttJ8oqYShU j0wk75Exd01x45Uaxs8towiqvb/su72IxbpAqoT33JD5OogB3dtjS4/aCddv+IDty7 ib60VxxrBdFdw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init Date: Sat, 27 May 2023 00:59:54 +0800 Message-Id: <20230526165958.908-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230526_101115_647534_8D1A73BC X-CRM114-Status: UNSURE ( 9.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The two functions cbo_get_block_size() and riscv_init_cbo_blocksizes() are only called during booting, mark them as __init. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/mm/cacheflush.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index fca532ddf3ec..fbc59b3f69f2 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -104,9 +104,9 @@ EXPORT_SYMBOL_GPL(riscv_cbom_block_size); unsigned int riscv_cboz_block_size; EXPORT_SYMBOL_GPL(riscv_cboz_block_size); -static void cbo_get_block_size(struct device_node *node, - const char *name, u32 *block_size, - unsigned long *first_hartid) +static void __init cbo_get_block_size(struct device_node *node, + const char *name, u32 *block_size, + unsigned long *first_hartid) { unsigned long hartid; u32 val; @@ -126,7 +126,7 @@ static void cbo_get_block_size(struct device_node *node, } } -void riscv_init_cbo_blocksizes(void) +void __init riscv_init_cbo_blocksizes(void) { unsigned long cbom_hartid, cboz_hartid; u32 cbom_block_size = 0, cboz_block_size = 0; From patchwork Fri May 26 16:59:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13257196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF83BC77B7A for ; Fri, 26 May 2023 17:11:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=SmTMy4b3qwPhxRPtbwim+ofYCGdZL4mbRz/WW/fgvdg=; b=JlA5SM2Qads9nX 7gVTIP05entGbonVuL5qIDqG5HQln4OdHjXntubGV0+hSTKMCGniChd0j9BkH5oe8xhjXNxYGB4xJ 4c0WkgaUt7MeV49f4M8rLUpV8yWS9cY6Z164i6CKq+EO2Za0lOy3zQotm5CAwV55yEBXNMDtBHb1z AL+wPqwmDo45oTiPWx7sBt5//eyaJC9m6yOYAslurBrD0sonRfN0FQWK9ZKZZ5wEaPcUCG47xRQsf E5BnGiOR+I1/da6b7kwhkI5zeqwQRKz9VPnZBBJTKxZxHXkt2qjDvr5/ArrKJpUudnRGEfjwxf68g OCHt59bma5cADQ4lIgxw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayG-003FfQ-2m; Fri, 26 May 2023 17:11:20 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayD-003Fdh-1H for linux-riscv@lists.infradead.org; Fri, 26 May 2023 17:11:18 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id F0E83651C0; Fri, 26 May 2023 17:11:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09AA0C4339B; Fri, 26 May 2023 17:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121076; bh=EFBwhFd9h5qljpxdSxEUl1LBAOZbrYHCRzIQKTfr4Eo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aqSdc9yjds0qBut4705CgMnspNEGuyhW+e1aoMQmGPboAeGFMDVvjfNAGTjvZCgZv CyuYU9rrIt276VNDMQ4RkYntlG86VMvrqucBi6vr9aM+tc8munbsrRU0TZpnlEXrxc UGbQiDbl21o6r6XyAlFF1w10ARU6M7vWRz3B2aYMqI5DQUtHVw/A/DH9hNaGuGnefq O6dfGs+cFxuthKDzH5KyY70wbvnLgHdK9ilEpFIxbOUNcSZfn3hMsTYojY3Ejmoy6I Y241nSqbxB7/nDNx99+A1sYt/6FtGfU2htL7glI0+OfpQ/GhvsPp02cit4tp7RJgfa 7kyyc8Qnzh61Q== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init Date: Sat, 27 May 2023 00:59:55 +0800 Message-Id: <20230526165958.908-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230526_101117_475498_56372DF4 X-CRM114-Status: GOOD ( 10.72 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The noncoherent_supported indicates whether the HW is coherent or not, it won't change after booting, mark it as __ro_after_init. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/mm/dma-noncoherent.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index d919efab6eba..d51a75864e53 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -10,7 +10,7 @@ #include #include -static bool noncoherent_supported; +static bool noncoherent_supported __ro_after_init; void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir) From patchwork Fri May 26 16:59:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13257197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3CECC77B7A for ; Fri, 26 May 2023 17:11:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PCKIQJNN/jItHQhzrHZ8jpbYmtGmixFZZZ1Qbhl/NQo=; b=sFhc7hQzTMG7Os AzXjnNg0tINaYOF+GyiC6KEeEr/JI2OHDwIP9ep+3PzF88dra6kq1F3rkbUrcl0I7fOmzfEvZENtw tEkEMOYxw8h40vTi2OW0134e/Tf2u8/hFc8wndTWLTPC32xecgVvJaOWDjM6b8vPx+8Oj6uP+lexl jL4VSubcpQ2qUBYTAMqQ9oSc8eX1IZGVHOgGl4mGLEsGaWV4VY4b7Cd5Oa4JgCfyvs5xBPq+hDCJ/ VjwKgWG764Eo4RTjvXmEzH60DueRFtPBLORnyGOGObnHmHRiwdeb3fSs4zcJDZw0izE718dBADMvB fZLBJLoo/SlYRa0VW9fA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayK-003Fhe-1r; Fri, 26 May 2023 17:11:24 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayF-003FeJ-0a for linux-riscv@lists.infradead.org; Fri, 26 May 2023 17:11:20 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C197B650CE; Fri, 26 May 2023 17:11:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D085CC433EF; Fri, 26 May 2023 17:11:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121078; bh=Bs4Qhmx5NZ+yKonQ7Rt09UyM8af1mOtvP1M80X6S4jQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q9Y1UXMhi4qK29CeyQI19Humy4yTmrqCpAopNGt1S+1XcaeUKmnORESujrBqXEfd3 qvyiSgkK20sTmXgyHEJccjGyXnZ17e5PF7iLp92CC0yT0Z/JZf7UIbIvqs2eUcTEaF e//NjVYc1BMFIG/OE0/ik7wg3p8J1EIBIQXxrTR967X4dGzAEc5H2hrn8Sj+3pChl5 eF9S4qczAXnpMMxQYG0TdNBYrdEFdNDfMgLkRoSUisfE2yVc9fVNi6CfoPwMQD8SLi i3ZmM+sElibCVv5j5oilGTXSrslQ3Or1mpAVnl8L7S9vaNgFA513T/J2wz7eAGGBBe tcEgUMrGrAGiA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() Date: Sat, 27 May 2023 00:59:56 +0800 Message-Id: <20230526165958.908-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230526_101119_301504_3EEA6D39 X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We will soon take different actions by checking the HW is noncoherent or not, I.E ZICBOM/ERRATA_THEAD_CMO or not. Signed-off-by: Jisheng Zhang --- arch/riscv/errata/thead/errata.c | 19 +++++++++++-------- arch/riscv/include/asm/cacheflush.h | 4 ++-- arch/riscv/kernel/setup.c | 6 +++++- arch/riscv/mm/dma-noncoherent.c | 10 ++++++---- 4 files changed, 24 insertions(+), 15 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index be84b14f0118..c192b80a5166 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage, static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id, unsigned long impid) { - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO)) - return false; - - if (arch_id != 0 || impid != 0) - return false; + bool cmo; if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return false; + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) && + (arch_id == 0 && impid == 0)) + cmo = true; + else + cmo = false; + if (stage == RISCV_ALTERNATIVES_BOOT) { - riscv_cbom_block_size = L1_CACHE_BYTES; - riscv_noncoherent_supported(); + if (cmo) + riscv_cbom_block_size = L1_CACHE_BYTES; + riscv_noncoherent_supported(cmo); } - return true; + return cmo; } static bool errata_probe_pmu(unsigned int stage, diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8091b8bf4883..9d056c9b625a 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size; void riscv_init_cbo_blocksizes(void); #ifdef CONFIG_RISCV_DMA_NONCOHERENT -void riscv_noncoherent_supported(void); +void riscv_noncoherent_supported(bool cmo); #else -static inline void riscv_noncoherent_supported(void) {} +static inline void riscv_noncoherent_supported(bool cmo) {} #endif /* diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 36b026057503..565f3e20169b 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -264,6 +264,7 @@ static void __init parse_dtb(void) void __init setup_arch(char **cmdline_p) { + bool cmo; parse_dtb(); setup_initial_init_mm(_stext, _etext, _edata, _end); @@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p) apply_boot_alternatives(); if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) - riscv_noncoherent_supported(); + cmo = true; + else + cmo = false; + riscv_noncoherent_supported(cmo); } static int __init topology_init(void) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index d51a75864e53..0e172e2b4751 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, dev->dma_coherent = coherent; } -void riscv_noncoherent_supported(void) +void riscv_noncoherent_supported(bool cmo) { - WARN(!riscv_cbom_block_size, - "Non-coherent DMA support enabled without a block size\n"); - noncoherent_supported = true; + if (cmo) { + WARN(!riscv_cbom_block_size, + "Non-coherent DMA support enabled without a block size\n"); + noncoherent_supported = true; + } } From patchwork Fri May 26 16:59:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13257198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43C01C7EE23 for ; Fri, 26 May 2023 17:11:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gRBH4L5N9Ps3354DUD9DxiyLc3CCupuho1rKnVnx1ZI=; b=Rt/e7G9ofoLL+/ NxusQzawK/4vOZkLsOB2QRvRxmibBMD3INViu3kWtDkjeZH5Rs+mIOOA5mEE/Fm43BkguhfDJExj0 8u+isrC021Ldvp0V3KhFJxUSA11Ra8NnieRZTSxnlzoakS/WgRjgn2QZ/fyjc7cYdkM48f7KYJkol fvcOwM+nKPJgGV1Kmx7XxAf9Kp/FMdLVJakKDixl/fLwq8erJ7NJG5TIA3jUlO0eJgymY1Jfnczo3 FjUVDaZmyXYi3Fz/+lvKN3LHiDBHfjQS92qZT0WAeNwabfElV8Nr1PBs/zpQrvmYuxzk9xbKEg8gQ iArjlK180KUEhUQsyqXA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayL-003Fi9-0Z; Fri, 26 May 2023 17:11:25 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayH-003FfI-0C for linux-riscv@lists.infradead.org; Fri, 26 May 2023 17:11:22 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 96D06651C2; Fri, 26 May 2023 17:11:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A24CEC4339B; Fri, 26 May 2023 17:11:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121080; bh=NqqasUnRMBLReOmJzfWs5pvHZNoT/9CPsg7U+dgQNHM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r/6CXpeHNUGKQyClLnumeEU4WdVQ0v8ClQth1L1b9KGS6C8PaXWnAEiR3wZEqunEe cGvry/QwoEgYKFwdE6S8D1CGMT2AjnhMLomwpNTHxqHqz7PTBH6FIsdHxo2jmlgqf+ qLP5vdpNAIi+DOzIkcmlS2R4bjuP+MRaxFYqNkx1GEzi0zQevkg4NTpWn6DQ45QHT9 3dLnTe/tGy8xVoyoyrza3W+r6aRDTIEkIC6CmBceFxj6vLrBxT18saM1slxX4wBf4/ t0zQj1LjdVjwjm71EnF8EI7PHZpb2r+/UGueBe7pDY561UJ77DVEJs7DT+aGbhRtgx WSD1FXf35HPGQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value Date: Sat, 27 May 2023 00:59:57 +0800 Message-Id: <20230526165958.908-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230526_101121_182655_D112BF4D X-CRM114-Status: GOOD ( 16.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, riscv defines ARCH_DMA_MINALIGN as L1_CACHE_BYTES, I.E 64Bytes, if CONFIG_RISCV_DMA_NONCOHERENT=y. To support unified kernel Image, usually we have to enable CONFIG_RISCV_DMA_NONCOHERENT, thus it brings some bad effects to for coherent platforms: Firstly, it wastes memory, kmalloc-96, kmalloc-32, kmalloc-16 and kmalloc-8 slab caches don't exist any more, they are replaced with either kmalloc-128 or kmalloc-64. Secondly, larger than necessary kmalloc aligned allocations results in unnecessary cache/TLB pressure. This issue also exists on arm64 platforms. From last year, Catalin tried to solve this issue by decoupling ARCH_KMALLOC_MINALIGN from ARCH_DMA_MINALIGN, limiting kmalloc() minimum alignment to dma_get_cache_alignment() and replacing ARCH_KMALLOC_MINALIGN usage in various drivers with ARCH_DMA_MINALIGN etc. One fact we can make use of for riscv: if the CPU doesn't support ZICBOM or T-HEAD CMO, we know the platform is coherent. Based on Catalin's work and above fact, we can easily solve the kmalloc align issue for riscv: we can override dma_get_cache_alignment(), then let it return ARCH_DMA_MINALIGN at the beginning and return 1 once we know the underlying HW neither supports ZICBOM nor supports T-HEAD CMO. So what about if the CPU supports ZICBOM and T-HEAD CMO, but all the devices are dma coherent? Well, we use ARCH_DMA_MINALIGN as the kmalloc minimum alignment, nothing changed in this case. This case can be improved in the future. After this patch, a simple test of booting to a small buildroot rootfs on qemu shows: kmalloc-96 5041 5041 96 ... kmalloc-64 9606 9606 64 ... kmalloc-32 5128 5128 32 ... kmalloc-16 7682 7682 16 ... kmalloc-8 10246 10246 8 ... So we save about 1268KB memory. The saving will be much larger in normal OS env on real HW platforms. [1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/ Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/cache.h | 14 ++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index d3036df23ccb..2174fe7bac9a 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -13,6 +13,7 @@ #ifdef CONFIG_RISCV_DMA_NONCOHERENT #define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#define ARCH_KMALLOC_MINALIGN (8) #endif /* @@ -23,4 +24,17 @@ #define ARCH_SLAB_MINALIGN 16 #endif +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +extern int dma_cache_alignment; +#define dma_get_cache_alignment dma_get_cache_alignment +static inline int dma_get_cache_alignment(void) +{ + return dma_cache_alignment; +} +#endif + +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_RISCV_CACHE_H */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index 0e172e2b4751..21b553c299db 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -11,6 +11,8 @@ #include static bool noncoherent_supported __ro_after_init; +int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN; +EXPORT_SYMBOL(dma_cache_alignment); void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir) @@ -78,5 +80,7 @@ void riscv_noncoherent_supported(bool cmo) WARN(!riscv_cbom_block_size, "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported = true; + } else { + dma_cache_alignment = 1; } } From patchwork Fri May 26 16:59:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13257199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3155C7EE23 for ; Fri, 26 May 2023 17:11:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IXiYu5PBJeMBirgyWl1wfixvFh+0ab7pY2YHeo/QEP0=; b=gJ0OxPNTV2XWmg /xhtdo/ihAaDke2ONBDDn1L90GmEeMxY6/rHpaeU8C/s9oB9WmTWa6CtosBDg6RPiFDcSZDrGt9Fs ZDiWkfUeC/bKU/PKaMtXMAif5q9V0eBtoqioG2y7FdQ75Hw2R78CVrx0L0O4i/c4dvEY4mxAygtPB PvfaMDqtfvyhzaNPybl3q5FP2k0+5o1Is9Zs+ZmdqP33PNYQcRRJ0ip1BX/0CZL64OGRvAU+if/S8 ktkEM59XWgTIsLHc8QjSGxHMTAdIdvLddw1bpOsS9fNj7n2rP7Koj8266X8FhZi1HtZwgf/rWUVju lJQcRvnwbRXWg5f89hxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayP-003Fky-1J; Fri, 26 May 2023 17:11:29 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q2ayJ-003Fgm-0z for linux-riscv@lists.infradead.org; Fri, 26 May 2023 17:11:24 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DCFC6651D3; Fri, 26 May 2023 17:11:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73D6FC433EF; Fri, 26 May 2023 17:11:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121081; bh=Sb+M48Kvrrwe56O2VNb3Wy6c5mOmMps4uXhVYIYGrVA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bNCXjNb4yjDWVmK8nVob+9hyyY8G6hAJF9rkXgE10A1fmr6dPhyHr82KyXokkoJMh vhYiAMlsJ3rYifkJ0MND8EjH8qski6jZNSGf0igixo1rRawZRSqTIMCAjQ2CT9Puva 9XQTDnC0qD1sU1xQtsN9fHq+BwgScWu+AH510ELfxQhyEvuNEH/PfSoKs/CKXEftJD 4Dahcxl81zim9vpr11kdsU6Wcn2yDzsWmbUWvP1nlzU+KniHqHflKWRRPBiOZVdzoc rNsdUj2cRzxWT/HPUhfPbzbFfSIX1tsT0m2qYe6IGpOBWH1FwFTq3cAp99q2kOeYgM CZTuJ2IuA1tSA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 6/6] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent Date: Sat, 27 May 2023 00:59:58 +0800 Message-Id: <20230526165958.908-7-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230526_101123_386153_EE4DD4FE X-CRM114-Status: GOOD ( 11.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org With the DMA bouncing of unaligned kmalloc() buffers now in place, enable it for riscv when RISCV_DMA_NONCOHERENT=y to allow the kmalloc-{8,16,32,96} caches. Since RV32 doesn't enable SWIOTLB yet, and I didn't see any dma noncoherent RV32 platforms in the mainline, so skip RV32 now by only enabling DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB is available. Once we see such requirement on RV32, we can enable it then. NOTE: we didn't force to create the swiotlb buffer even when the end of RAM is within the 32-bit physical address range. That's to say: For RV64 with > 4GB memory, the feature is enabled. For RV64 with <= 4GB memory, the feature isn't enabled by default. We rely on users to pass "swiotlb=mmnn,force" where mmnn is the Number of I/O TLB slabs, see kernel-parameters.txt for details. Tested on Sipeed Lichee Pi 4A with 8GB DDR and Sipeed M1S BL808 Dock board. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b958f67f9a12..14f030cd6357 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -260,6 +260,7 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_DEVICE select DMA_DIRECT_REMAP + select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)