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([2602:ae:1598:4c01:be31:c162:a57e:7431]) by smtp.gmail.com with ESMTPSA id j20-20020a170902759400b001a988a71617sm1258992pll.192.2023.05.27.07.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 May 2023 07:19:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: christoph.muellner@vrull.eu, alex.bennee@linaro.org Subject: [PATCH 1/4] fpu: Add float64_to_int{32,64}_modulo Date: Sat, 27 May 2023 07:19:07 -0700 Message-Id: <20230527141910.1885950-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230527141910.1885950-1-richard.henderson@linaro.org> References: <20230527141910.1885950-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add versions of float64_to_int* which do not saturate the result. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- include/fpu/softfloat.h | 3 ++ fpu/softfloat.c | 31 ++++++++++++++++ fpu/softfloat-parts.c.inc | 78 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 3dcf20e3a2..cd130564d8 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -751,6 +751,9 @@ int16_t float64_to_int16_round_to_zero(float64, float_status *status); int32_t float64_to_int32_round_to_zero(float64, float_status *status); int64_t float64_to_int64_round_to_zero(float64, float_status *status); +int32_t float64_to_int32_modulo(float64, FloatRoundMode, float_status *status); +int64_t float64_to_int64_modulo(float64, FloatRoundMode, float_status *status); + uint16_t float64_to_uint16_scalbn(float64, FloatRoundMode, int, float_status *); uint32_t float64_to_uint32_scalbn(float64, FloatRoundMode, int, float_status *); uint64_t float64_to_uint64_scalbn(float64, FloatRoundMode, int, float_status *); diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 108f9cb224..c05819afcd 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -852,11 +852,24 @@ static uint64_t parts128_float_to_uint(FloatParts128 *p, FloatRoundMode rmode, #define parts_float_to_uint(P, R, Z, M, S) \ PARTS_GENERIC_64_128(float_to_uint, P)(P, R, Z, M, S) +static int64_t parts64_float_to_sint_modulo(FloatParts64 *p, + FloatRoundMode rmode, + int bitsm1, float_status *s); +static int64_t parts128_float_to_sint_modulo(FloatParts128 *p, + FloatRoundMode rmode, + int bitsm1, float_status *s); + +#define parts_float_to_sint_modulo(P, R, M, S) \ + PARTS_GENERIC_64_128(float_to_sint_modulo, P)(P, R, M, S) + static void parts64_sint_to_float(FloatParts64 *p, int64_t a, int scale, float_status *s); static void parts128_sint_to_float(FloatParts128 *p, int64_t a, int scale, float_status *s); +#define parts_float_to_sint(P, R, Z, MN, MX, S) \ + PARTS_GENERIC_64_128(float_to_sint, P)(P, R, Z, MN, MX, S) + #define parts_sint_to_float(P, I, Z, S) \ PARTS_GENERIC_64_128(sint_to_float, P)(P, I, Z, S) @@ -3409,6 +3422,24 @@ int64_t bfloat16_to_int64_round_to_zero(bfloat16 a, float_status *s) return bfloat16_to_int64_scalbn(a, float_round_to_zero, 0, s); } +int32_t float64_to_int32_modulo(float64 a, FloatRoundMode rmode, + float_status *s) +{ + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return parts_float_to_sint_modulo(&p, rmode, 31, s); +} + +int64_t float64_to_int64_modulo(float64 a, FloatRoundMode rmode, + float_status *s) +{ + FloatParts64 p; + + float64_unpack_canonical(&p, a, s); + return parts_float_to_sint_modulo(&p, rmode, 63, s); +} + /* * Floating-point to unsigned integer conversions */ diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 247400031c..527e15e6ab 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1181,6 +1181,84 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, return r; } +/* + * Like partsN(float_to_sint), except do not saturate the result. + * Instead, return the rounded unbounded precision two's compliment result, + * modulo 2**(bitsm1 + 1). + */ +static int64_t partsN(float_to_sint_modulo)(FloatPartsN *p, + FloatRoundMode rmode, + int bitsm1, float_status *s) +{ + int flags = 0; + uint64_t r; + bool overflow = false; + + switch (p->cls) { + case float_class_snan: + flags |= float_flag_invalid_snan; + /* fall through */ + case float_class_qnan: + flags |= float_flag_invalid; + r = 0; + break; + + case float_class_inf: + overflow = true; + r = 0; + break; + + case float_class_zero: + return 0; + + case float_class_normal: + /* TODO: N - 2 is frac_size for rounding; could use input fmt. */ + if (parts_round_to_int_normal(p, rmode, 0, N - 2)) { + flags = float_flag_inexact; + } + + if (p->exp <= DECOMPOSED_BINARY_POINT) { + /* + * Because we rounded to integral, and exp < 64, + * we know frac_low is zero. + */ + r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); + if (p->exp < bitsm1) { + /* Result in range. */ + } else if (p->exp == bitsm1) { + /* The only in-range value is INT_MIN. */ + overflow = !p->sign || p->frac_hi != DECOMPOSED_IMPLICIT_BIT; + } else { + overflow = true; + } + } else { + /* Overflow, but there might still be bits to return. */ + int shl = p->exp - DECOMPOSED_BINARY_POINT; + if (shl < N) { + frac_shl(p, shl); + r = p->frac_hi; + } else { + r = 0; + } + overflow = true; + } + + if (p->sign) { + r = -r; + } + break; + + default: + g_assert_not_reached(); + } + + if (overflow) { + flags = float_flag_invalid | float_flag_invalid_cvti; + } + float_raise(flags, s); + return r; +} + /* * Integer to float conversions * From patchwork Sat May 27 14:19:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13257683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66810C7EE2F for ; Sat, 27 May 2023 14:20:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2ulN-0007op-Cx; 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([2602:ae:1598:4c01:be31:c162:a57e:7431]) by smtp.gmail.com with ESMTPSA id j20-20020a170902759400b001a988a71617sm1258992pll.192.2023.05.27.07.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 May 2023 07:19:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: christoph.muellner@vrull.eu, alex.bennee@linaro.org Subject: [PATCH 2/4] tests/tcg/alpha: Add test for cvttq Date: Sat, 27 May 2023 07:19:08 -0700 Message-Id: <20230527141910.1885950-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230527141910.1885950-1-richard.henderson@linaro.org> References: <20230527141910.1885950-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Test for invalid, integer overflow, and inexact. Test for proper result, modulo 2**64. Signed-off-by: Richard Henderson Acked-by: Alex Bennée Acked-by: Alex Bennée --- tests/tcg/alpha/test-cvttq.c | 78 +++++++++++++++++++++++++++++++++ tests/tcg/alpha/Makefile.target | 2 +- 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/alpha/test-cvttq.c diff --git a/tests/tcg/alpha/test-cvttq.c b/tests/tcg/alpha/test-cvttq.c new file mode 100644 index 0000000000..d1ad995312 --- /dev/null +++ b/tests/tcg/alpha/test-cvttq.c @@ -0,0 +1,78 @@ +#include + +#define FPCR_SUM (1UL << 63) +#define FPCR_INED (1UL << 62) +#define FPCR_UNFD (1UL << 61) +#define FPCR_UNDZ (1UL << 60) +#define FPCR_DYN_SHIFT 58 +#define FPCR_DYN_CHOPPED (0UL << FPCR_DYN_SHIFT) +#define FPCR_DYN_MINUS (1UL << FPCR_DYN_SHIFT) +#define FPCR_DYN_NORMAL (2UL << FPCR_DYN_SHIFT) +#define FPCR_DYN_PLUS (3UL << FPCR_DYN_SHIFT) +#define FPCR_DYN_MASK (3UL << FPCR_DYN_SHIFT) +#define FPCR_IOV (1UL << 57) +#define FPCR_INE (1UL << 56) +#define FPCR_UNF (1UL << 55) +#define FPCR_OVF (1UL << 54) +#define FPCR_DZE (1UL << 53) +#define FPCR_INV (1UL << 52) +#define FPCR_OVFD (1UL << 51) +#define FPCR_DZED (1UL << 50) +#define FPCR_INVD (1UL << 49) +#define FPCR_DNZ (1UL << 48) +#define FPCR_DNOD (1UL << 47) +#define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \ + | FPCR_OVF | FPCR_DZE | FPCR_INV) + +static long test_cvttq(long *ret_e, double d) +{ + unsigned long reset = (FPCR_INED | FPCR_UNFD | FPCR_OVFD | FPCR_DZED | + FPCR_INVD | FPCR_DYN_NORMAL); + long r, e; + + asm("excb\n\t" + "mt_fpcr %3\n\t" + "excb\n\t" + "cvttq/svic %2, %0\n\t" + "excb\n\t" + "mf_fpcr %1\n\t" + "excb\n\t" + : "=f"(r), "=f"(e) + : "f"(d), "f"(reset)); + + *ret_e = e & FPCR_STATUS_MASK; + return r; +} + +int main (void) +{ + static const struct { + double d; + long r; + long e; + } T[] = { + { 1.0, 1, 0 }, + { -1.0, -1, 0 }, + { 1.5, 1, FPCR_INE }, + { 0x1.0p32, 0x0000000100000000ul, 0 }, + { -0x1.0p63, 0x8000000000000000ul, 0 }, + { 0x1.0p63, 0x8000000000000000ul, FPCR_IOV | FPCR_INE }, + { 0x1.0p64, 0x0000000000000000ul, FPCR_IOV | FPCR_INE }, + { 0x1.cccp64, 0xccc0000000000000ul, FPCR_IOV | FPCR_INE }, + { __builtin_inf(), 0, FPCR_INV }, + { __builtin_nan(""), 0, FPCR_INV }, + }; + + int i, err = 0; + + for (i = 0; i < sizeof(T)/sizeof(T[0]); i++) { + long e, r = test_cvttq(&e, T[i].d); + + if (r != T[i].r || e != T[i].e) { + printf("Fail %a: expect (%016lx : %04lx) got (%016lx : %04lx)\n", + T[i].d, T[i].r, T[i].e >> 48, r, e >> 48); + err = 1; + } + } + return err; +} diff --git a/tests/tcg/alpha/Makefile.target b/tests/tcg/alpha/Makefile.target index a585080328..b94500a7d9 100644 --- a/tests/tcg/alpha/Makefile.target +++ b/tests/tcg/alpha/Makefile.target @@ -5,7 +5,7 @@ ALPHA_SRC=$(SRC_PATH)/tests/tcg/alpha VPATH+=$(ALPHA_SRC) -ALPHA_TESTS=hello-alpha test-cond test-cmov test-ovf +ALPHA_TESTS=hello-alpha test-cond test-cmov test-ovf test-cvttq TESTS+=$(ALPHA_TESTS) test-cmov: EXTRA_CFLAGS=-DTEST_CMOV From patchwork Sat May 27 14:19:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13257685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1345EC77B73 for ; Sat, 27 May 2023 14:20:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2ulN-0007p5-L7; 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([2602:ae:1598:4c01:be31:c162:a57e:7431]) by smtp.gmail.com with ESMTPSA id j20-20020a170902759400b001a988a71617sm1258992pll.192.2023.05.27.07.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 May 2023 07:19:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: christoph.muellner@vrull.eu, alex.bennee@linaro.org Subject: [PATCH 3/4] target/alpha: Use float64_to_int64_modulo for CVTTQ Date: Sat, 27 May 2023 07:19:09 -0700 Message-Id: <20230527141910.1885950-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230527141910.1885950-1-richard.henderson@linaro.org> References: <20230527141910.1885950-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For the most part we can use the new generic routine, though exceptions need some post-processing to sort invalid from integer overflow. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/alpha/fpu_helper.c | 85 +++++++++------------------------------ 1 file changed, 18 insertions(+), 67 deletions(-) diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c index 3ff8bb456d..63d9e9ce39 100644 --- a/target/alpha/fpu_helper.c +++ b/target/alpha/fpu_helper.c @@ -453,78 +453,29 @@ uint64_t helper_cvtqs(CPUAlphaState *env, uint64_t a) static uint64_t do_cvttq(CPUAlphaState *env, uint64_t a, int roundmode) { - uint64_t frac, ret = 0; - uint32_t exp, sign, exc = 0; - int shift; + float64 fa; + int64_t ret; + uint32_t exc; - sign = (a >> 63); - exp = (uint32_t)(a >> 52) & 0x7ff; - frac = a & 0xfffffffffffffull; + fa = t_to_float64(a); + ret = float64_to_int64_modulo(fa, roundmode, &FP_STATUS); - if (exp == 0) { - if (unlikely(frac != 0) && !env->fp_status.flush_inputs_to_zero) { - goto do_underflow; - } - } else if (exp == 0x7ff) { - exc = FPCR_INV; - } else { - /* Restore implicit bit. */ - frac |= 0x10000000000000ull; + exc = get_float_exception_flags(&FP_STATUS); + if (unlikely(exc)) { + set_float_exception_flags(0, &FP_STATUS); - shift = exp - 1023 - 52; - if (shift >= 0) { - /* In this case the number is so large that we must shift - the fraction left. There is no rounding to do. */ - if (shift < 64) { - ret = frac << shift; - } - /* Check for overflow. Note the special case of -0x1p63. */ - if (shift >= 11 && a != 0xC3E0000000000000ull) { + /* We need to massage the resulting exceptions. */ + if (exc & float_flag_invalid_cvti) { + /* Overflow, either normal or infinity. */ + if (float64_is_infinity(fa)) { + exc = FPCR_INV; + } else { exc = FPCR_IOV | FPCR_INE; } - } else { - uint64_t round; - - /* In this case the number is smaller than the fraction as - represented by the 52 bit number. Here we must think - about rounding the result. Handle this by shifting the - fractional part of the number into the high bits of ROUND. - This will let us efficiently handle round-to-nearest. */ - shift = -shift; - if (shift < 63) { - ret = frac >> shift; - round = frac << (64 - shift); - } else { - /* The exponent is so small we shift out everything. - Leave a sticky bit for proper rounding below. */ - do_underflow: - round = 1; - } - - if (round) { - exc = FPCR_INE; - switch (roundmode) { - case float_round_nearest_even: - if (round == (1ull << 63)) { - /* Fraction is exactly 0.5; round to even. */ - ret += (ret & 1); - } else if (round > (1ull << 63)) { - ret += 1; - } - break; - case float_round_to_zero: - break; - case float_round_up: - ret += 1 - sign; - break; - case float_round_down: - ret += sign; - break; - } - } - } - if (sign) { - ret = -ret; + } else if (exc & float_flag_invalid) { + exc = FPCR_INV; + } else if (exc & float_flag_inexact) { + exc = FPCR_INE; } } env->error_code = exc; From patchwork Sat May 27 14:19:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13257681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5F1CFC77B7C for ; Sat, 27 May 2023 14:20:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2ulO-0007pC-7L; Sat, 27 May 2023 10:19:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2ulK-0007og-EM for qemu-devel@nongnu.org; Sat, 27 May 2023 10:19:19 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2ulI-0002Gg-Ng for qemu-devel@nongnu.org; Sat, 27 May 2023 10:19:18 -0400 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2564b0921f1so304152a91.3 for ; Sat, 27 May 2023 07:19:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685197155; x=1687789155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4Ci3Rw1Bwfq/vRMH6eDy4QVIqFnQy7Z61D8fU9qGASA=; b=opHnNvlK67U5GEiwnV5AJmHAEhCy0zfcc8EfjaiERh3+sewTukAAu828PJeaJ4fUxw zYV09YDgXxUQ8sQ68bJqoU/ytHJiz7XUD+fNQu4245Xm15T9fEO7UuLFlEBgrtCRc4Ml mHEpKvSAOR+QMW1DxWV69nI7PkFrknE8+0uIflibGmvKZG/zKoowRBA227W6C6kETtbq VU9EbQN6MqMwJV/2XheekZYK/+ktVpay+TANl0mMHsxxskaQwE1etyc6WwjKViAzOUJK GWYJopMdXXeajGBQ+pV+vLfx3go3BSk+l/xqyHGEHnUCIGPuMEQbiGZneB1CW3Ldt/kH NPwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685197155; x=1687789155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4Ci3Rw1Bwfq/vRMH6eDy4QVIqFnQy7Z61D8fU9qGASA=; b=afVjlmsWSHyoVPKL3gYde4XxUvLonOWnIQvhRxuFFE7E/zQOMEeyDRy6M+9YJGA2r/ hfCzCw77mcrfH+ekXukJ2pK7O6NxYOOsqFoex8qfJTPq7yRuVHcj+XMHme7MvtAb5Th+ RyxRnt82y+4hyHMYL2tSliBhrfnAH8MAFR6LEILXjESp/1EdCxkzx7OfPlrSXcq+70AM cUNL6XRRStyoVD2okQnMVGfaBNnaW4Q6lvqoMJHSk7FES7ippCjDAHAn6YIIqiBaNRhg Srqwd6cNuthEPpOXuO10FNaD3S9i+wK4h4acofbUnodx0y0wuDmWrV9xISktJCB3E2Q/ sGmg== X-Gm-Message-State: AC+VfDzi7GS8MxBtPD4TXcdmPHAYbipdJ77TmjZoOeCgqnPqhbUywyY/ Kl8PkeHWs1LawdnpKE90r+9orEOw5YeHBailRaY= X-Google-Smtp-Source: ACHHUZ5uVfZGpOYcdjj130ClUPZFaEU0SyYCoV4YKvtTuk2mB+A+19ET2W3v5GyBE3T10j+8BaKfYA== X-Received: by 2002:a17:902:ea0b:b0:1af:b3b6:4947 with SMTP id s11-20020a170902ea0b00b001afb3b64947mr7767551plg.24.1685197155272; Sat, 27 May 2023 07:19:15 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:be31:c162:a57e:7431]) by smtp.gmail.com with ESMTPSA id j20-20020a170902759400b001a988a71617sm1258992pll.192.2023.05.27.07.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 May 2023 07:19:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: christoph.muellner@vrull.eu, alex.bennee@linaro.org Subject: [PATCH 4/4] target/arm: Use float64_to_int32_modulo for FJCVTZS Date: Sat, 27 May 2023 07:19:10 -0700 Message-Id: <20230527141910.1885950-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230527141910.1885950-1-richard.henderson@linaro.org> References: <20230527141910.1885950-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The standard floating point results are provided by the generic routine. We only need handle the extra Z flag result afterward. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- target/arm/vfp_helper.c | 71 +++++++---------------------------------- 1 file changed, 12 insertions(+), 59 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 36906db8e0..789bba36cc 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -1120,68 +1120,21 @@ const FloatRoundMode arm_rmode_to_sf_map[] = { uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) { float_status *status = vstatus; - uint32_t exp, sign; - uint64_t frac; - uint32_t inexact = 1; /* !Z */ + uint32_t inexact, frac; + uint32_t e_old, e_new; - sign = extract64(value, 63, 1); - exp = extract64(value, 52, 11); - frac = extract64(value, 0, 52); + e_old = get_float_exception_flags(status); + set_float_exception_flags(0, status); + frac = float64_to_int32_modulo(value, float_round_to_zero, status); + e_new = get_float_exception_flags(status); + set_float_exception_flags(e_old | e_new, status); - if (exp == 0) { - /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ - inexact = sign; - if (frac != 0) { - if (status->flush_inputs_to_zero) { - float_raise(float_flag_input_denormal, status); - } else { - float_raise(float_flag_inexact, status); - inexact = 1; - } - } - frac = 0; - } else if (exp == 0x7ff) { - /* This operation raises Invalid for both NaN and overflow (Inf). */ - float_raise(float_flag_invalid, status); - frac = 0; + if (value == float64_chs(float64_zero)) { + /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ + inexact = 1; } else { - int true_exp = exp - 1023; - int shift = true_exp - 52; - - /* Restore implicit bit. */ - frac |= 1ull << 52; - - /* Shift the fraction into place. */ - if (shift >= 0) { - /* The number is so large we must shift the fraction left. */ - if (shift >= 64) { - /* The fraction is shifted out entirely. */ - frac = 0; - } else { - frac <<= shift; - } - } else if (shift > -64) { - /* Normal case -- shift right and notice if bits shift out. */ - inexact = (frac << (64 + shift)) != 0; - frac >>= -shift; - } else { - /* The fraction is shifted out entirely. */ - frac = 0; - } - - /* Notice overflow or inexact exceptions. */ - if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) { - /* Overflow, for which this operation raises invalid. */ - float_raise(float_flag_invalid, status); - inexact = 1; - } else if (inexact) { - float_raise(float_flag_inexact, status); - } - - /* Honor the sign. */ - if (sign) { - frac = -frac; - } + /* Normal inexact or overflow or NaN */ + inexact = e_new & (float_flag_inexact | float_flag_invalid); } /* Pack the result and the env->ZF representation of Z together. */