From patchwork Mon May 29 06:26:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13258192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57EDAC77B7A for ; Mon, 29 May 2023 06:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231747AbjE2G2e (ORCPT ); Mon, 29 May 2023 02:28:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231749AbjE2G2I (ORCPT ); Mon, 29 May 2023 02:28:08 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65DB8E4F; Sun, 28 May 2023 23:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685341658; x=1716877658; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9nT6k4usc1ZdAfXJeFOMGjCgg2EwH9GxhdepY57V2w8=; b=JHpJkQTZ0kcqUm9uh54qS5Qovv+m5vCnyNUYH6yymCKgBXlwLzQe09si daov/5yo28/3YsgvhmkBfag3LXWDPxrIxI3oWw6Qp9rAVkeo/MZnieAYh TkP3bm/z59riQahmjI9k8PiU+ITN9yBwcWjw6okSCeMnDSq9uREq8CE9+ CcYcYZIT3H4eOxcOobzldI0OadN6vFWloRwyOHDRJ81Xyza5BLYyAKJt2 nAXx+X0g4IfAFX2oFAqPoqLLO9VtY8GSyEHUR3CONtA1mOg/8n0YqfIZN 6urombmlvdNcEIYNivX5WKmJaEGFyIeFArLymrmu1JgZ78Nb/eOeh+PNh Q==; X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="215861656" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 May 2023 23:26:29 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sun, 28 May 2023 23:26:27 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sun, 28 May 2023 23:26:22 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH v2 1/4] ARM: dts: at91: sama7g5: keep only microchip,sam9x60-pit64b compatible for pit64b Date: Mon, 29 May 2023 09:26:01 +0300 Message-ID: <20230529062604.1498052-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529062604.1498052-1-claudiu.beznea@microchip.com> References: <20230529062604.1498052-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org SAM9X60 and SAMA7G5 PIT64Bs are 1 to 1 compatible. Thus, there is no need for specific compatible string on SAMA7G5. Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/sama7g5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 886b6209a71e..500b00508621 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -610,7 +610,7 @@ eic: interrupt-controller@e1628000 { }; pit64b0: timer@e1800000 { - compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; + compatible = "microchip,sam9x60-pit64b"; reg = <0xe1800000 0x4000>; interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; @@ -618,7 +618,7 @@ pit64b0: timer@e1800000 { }; pit64b1: timer@e1804000 { - compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; + compatible = "microchip,sam9x60-pit64b"; reg = <0xe1804000 0x4000>; interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; From patchwork Mon May 29 06:26:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13258194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F057C7EE29 for ; Mon, 29 May 2023 06:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231516AbjE2G2w (ORCPT ); Mon, 29 May 2023 02:28:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231735AbjE2G1q (ORCPT ); Mon, 29 May 2023 02:27:46 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B21D120; Sun, 28 May 2023 23:27:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685341637; x=1716877637; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pZDeHAwx+WHaBXQtS6jEEcIeL2CywxswjLJT4bjmOYA=; b=U+3jvR9wdtPqf9oawf4bQvhu3aPokHAkklFH2rB23/FLZjfuYt7Z020A ZuzbFecwEtdkKqoPGjMqvwWS2iceyq4IvNaJI4G8qRG0lOnFHWdoyYhCX 9+Cb0UKVUawqMLot5o7mVihwa7sTbwhxD2GFgeKs+Mmf5ag3KEQby3uKc j+xMVwVZb2gwCqNz9QXYL5vkOCNBmDhUV1UCOWQofgr2YqIHVq5xOWXZ0 ++K5zOXdcfuogpJehVMQBtIyBYuAPbHPRcyZT4jRV//9+mnXzjSFmamL2 w4oMv1InB1Lt2NFNaudW+hYBYajKR9st8ZZT0WKWsN3XHmr9lBU3CgxOP g==; X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="213501744" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 May 2023 23:26:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sun, 28 May 2023 23:26:31 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sun, 28 May 2023 23:26:27 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH v2 2/4] dt-bindings: timer: atmel,at91sam9260-pit: convert to yaml Date: Mon, 29 May 2023 09:26:02 +0300 Message-ID: <20230529062604.1498052-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529062604.1498052-1-claudiu.beznea@microchip.com> References: <20230529062604.1498052-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Convert Microchip AT91 PIT bindings to YAML. Along with it clocks and clock-names bindings were added as the drivers needs it to ensure proper hardware functionality. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 12 --- .../bindings/timer/atmel,at91sam9260-pit.yaml | 96 +++++++++++++++++++ 2 files changed, 96 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 67a66bf74895..54d3f586403e 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -4,18 +4,6 @@ Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" - reg : Should contain registers location and length -PIT Timer required properties: -- compatible: Should be "atmel,at91sam9260-pit" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the PIT which is the IRQ line - shared across all System Controller members. - -PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for PIT64B timer -- clocks: Should contain the available clock sources for PIT64B timer. - System Timer (ST) required properties: - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: Should contain registers location and length diff --git a/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml b/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml new file mode 100644 index 000000000000..1cc7b7494e4b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/atmel,at91sam9260-pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91 Periodic Interval Timer (PIT) + +maintainers: + - Claudiu Beznea + +description: + Microchip AT91 periodic interval timer provides the operating system scheduler + interrupt. It is designed to offer maximum accuracy and efficient management, + even for systems with long response time. + +properties: + compatible: + enum: + - atmel,at91sam9260-pit + - microchip,sam9x60-pit64b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: atmel,at91sam9260-pit + then: + properties: + interrupts: + description: + Contain interrupt for the PIT which is the IRQ line shared across all + System Controller members. + clocks: + maxItems: 1 + + else: + properties: + interrupts: + description: + PIT64B peripheral interrupt identifier. + clocks: + minItems: 2 + clock-names: + items: + - const: pclk + - const: gclk + required: + - clock-names + +unevaluatedProperties: false + +examples: + - | + /* AT91RM9200 */ + #include + #include + + pit: timer@fffffe40 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + - | + /* SAM9X60 */ + #include + #include + + pit64b: timer@f0028000 { + compatible = "microchip,sam9x60-pit64b"; + reg = <0xf0028000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names = "pclk", "gclk"; + }; + +... From patchwork Mon May 29 06:26:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13258191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 878DBC77B7A for ; Mon, 29 May 2023 06:28:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231673AbjE2G1x (ORCPT ); Mon, 29 May 2023 02:27:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231643AbjE2G1r (ORCPT ); Mon, 29 May 2023 02:27:47 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E21D3DE; Sun, 28 May 2023 23:27:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685341637; x=1716877637; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tSQUnslAhMfFgaCfiyHY/+VYMnOWOgn2z8cAN4rX8QA=; b=C+DtTg1FeOyeGlAzVZ+5553XSWubnF+OTBPx9mvtc4rpnp8v9f7qenhI tayGUitpOP3otI4ewlYCy5PZj3CTxxQhYuWxLSVG8s3xPAASejfpkGxJ3 ppATLcMhaIueAhQkNFFg0EgUzEsTT+iDXJRHptVFRmaPUdGrG7wGI9b/w QLe8TAMNooc0jfR1X2xpvENVFO4QpiNKGg282Aep3umSWZouN2lR6zvE7 m1UCvfWcFL2R9g/JhjW0Ct4+gzqSX02RGk3qRJK5BUn6v7qLrqAm+5Bc0 VxApk/1ShHx9pkbJCQJwkA6cvK2j9L1ou73Ajawrnm6mEKqGwHUlxN4xa Q==; X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="227402341" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 May 2023 23:26:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sun, 28 May 2023 23:26:36 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sun, 28 May 2023 23:26:31 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH v2 3/4] dt-bindings: watchdog: atmel,at91rm9200-wdt: convert to yaml Date: Mon, 29 May 2023 09:26:03 +0300 Message-ID: <20230529062604.1498052-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529062604.1498052-1-claudiu.beznea@microchip.com> References: <20230529062604.1498052-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Convert Microchip AT91RM9200 system timer watchdog bindings to YAML. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley --- .../watchdog/atmel,at91rm9200-wdt.yaml | 29 +++++++++++++++++++ .../watchdog/atmel-at91rm9200-wdt.txt | 9 ------ 2 files changed, 29 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/watchdog/atmel,at91rm9200-wdt.yaml delete mode 100644 Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt diff --git a/Documentation/devicetree/bindings/watchdog/atmel,at91rm9200-wdt.yaml b/Documentation/devicetree/bindings/watchdog/atmel,at91rm9200-wdt.yaml new file mode 100644 index 000000000000..592e797df4c2 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/atmel,at91rm9200-wdt.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/atmel,at91rm9200-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91RM9200 System Timer Watchdog + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +properties: + compatible: + const: atmel,at91rm9200-wdt + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + +... diff --git a/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt deleted file mode 100644 index d4d86cf8f9eb..000000000000 --- a/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt +++ /dev/null @@ -1,9 +0,0 @@ -Atmel AT91RM9200 System Timer Watchdog - -Required properties: -- compatible: must be "atmel,at91sam9260-wdt". - -Example: - watchdog@fffffd00 { - compatible = "atmel,at91rm9200-wdt"; - }; From patchwork Mon May 29 06:26:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13258193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC132C7EE23 for ; Mon, 29 May 2023 06:28:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231679AbjE2G2s (ORCPT ); Mon, 29 May 2023 02:28:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231682AbjE2G2i (ORCPT ); Mon, 29 May 2023 02:28:38 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 520911BC; Sun, 28 May 2023 23:28:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685341689; x=1716877689; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dh0EL4hNH/yV6+3G0mpHZLbVKP4ILEfFeFyXC+i3GrQ=; b=2NmnZp6HaVGmrA1AEITvTv7CHjLplUFnxV2vJ07Uz/CNJZt6bKSPZNMc QrBxFPndnvvnwko9++CuagztkyIwGIrcPdg67aozo5Ue2VPxSaTzxEwwb 6BJERPcCJsvZZEFW3gu7FoK7DNfb1OOGWoQajTTgpb5glPJaH9iORJ6s0 hfohjILa/pyL62kUlML4ENDpuFG/IeUHktcPtY1m59lx4AtXAMij/668H v2lg7H/l6kgvcZTG/1NSOqLsEjA0Y9iYsIdxG9W4BmBT16tRVYg+Rakw5 EdHg/sNLwr2O4JM0m+JvUqUGw2siqaOLgu+hjC8iVGAQnEU4PUMf+FZKy Q==; X-IronPort-AV: E=Sophos;i="6.00,200,1681196400"; d="scan'208";a="215861693" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 28 May 2023 23:26:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sun, 28 May 2023 23:26:42 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sun, 28 May 2023 23:26:37 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH v2 4/4] dt-bindings: timer: atmel,at91rm9200-st: convert to yaml Date: Mon, 29 May 2023 09:26:04 +0300 Message-ID: <20230529062604.1498052-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529062604.1498052-1-claudiu.beznea@microchip.com> References: <20230529062604.1498052-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Convert Microchip AT91 system timer to YAML. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley --- .../devicetree/bindings/arm/atmel-sysregs.txt | 9 --- .../bindings/timer/atmel,at91rm9200-st.yaml | 65 +++++++++++++++++++ 2 files changed, 65 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 54d3f586403e..68c0eacb01ac 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -4,15 +4,6 @@ Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" - reg : Should contain registers location and length -System Timer (ST) required properties: -- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the ST which is the IRQ line - shared across all System Controller members. -- clocks: phandle to input clock. -Its subnodes can be: -- watchdog: compatible should be "atmel,at91rm9200-wdt" - RAMC SDRAM/DDR Controller required properties: - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", diff --git a/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml b/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml new file mode 100644 index 000000000000..a75644e1a2fe --- /dev/null +++ b/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/atmel,at91rm9200-st.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91 System Timer (ST) + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: + Microchip AT91 system timer integrates a period interval timer, a watchdog + timer and a real-time timer. + +properties: + compatible: + items: + - const: atmel,at91rm9200-st + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + description: + Contain interrupt for the ST which is the IRQ line shared across all + system controller members. + maxItems: 1 + + clocks: + maxItems: 1 + + watchdog: + $ref: ../watchdog/atmel,at91rm9200-wdt.yaml + description: + Child node describing watchdog. + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + + st: timer@fffffd00 { + compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; + reg = <0xfffffd00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + }; + +...