From patchwork Mon May 29 09:43:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13258353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54620C7EE2C for ; Mon, 29 May 2023 09:45:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230348AbjE2JpD (ORCPT ); Mon, 29 May 2023 05:45:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229521AbjE2JpC (ORCPT ); Mon, 29 May 2023 05:45:02 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F042D8E; Mon, 29 May 2023 02:45:00 -0700 (PDT) Received: from [192.168.122.1] (217-149-172-244.nat.highway.telekom.at [217.149.172.244]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 76460CFC23; Mon, 29 May 2023 09:44:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685353499; bh=fKHguGMctFNCESACSZJ0OkdRQtMgSdg2Fb+SHug/OJY=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=bYRgCX1Ct/yYkMnlN9yCglsXXuZ1BQk3uiLrHhLsUtetfldu11etU/2uFd0IPxM8D A3ir4xouCPzZVRQXHVZ1j7RrHFoXmirxFrSCvoB4i5LkQS+ewEWFjUgOk+biEZ/7MA Zh0sxnYZqoS/IhwlJxL4oOq9a556IjcAyuFz9C4I= From: Luca Weiss Date: Mon, 29 May 2023 11:43:58 +0200 Subject: [PATCH 1/7] dt-bindings: msm: dsi-phy-28nm: Document msm8226 compatible MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v1-1-679f335d3d5b@z3ntu.xyz> References: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1472; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=fKHguGMctFNCESACSZJ0OkdRQtMgSdg2Fb+SHug/OJY=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkdHQT9jqIw6A1vUzspKqvEWAMqlztD1SJhxJ7V eBnFLL0nG6JAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHR0EwAKCRBy2EO4nU3X VplIEADTELAz3DmTbckP/EXs0s8kIO2qRB8KJ/Gxh8KNnF7/ZIAfmfut/0ZvL90EA4Zg0DFlz1W XAg27cSf2RdPkngXT8HlHZOJTNbVmBk/I9r+er/qQHAV9Ab6yMEWs9qNk4KX1aKaHTS7E283kf+ 9X+Gwx9qwvsNoivbYSUryR17/67wARPVIO7Hwl+WWgmf3dtwbNNNp8N9Zm6sN/KMU2+wJyCVFlD I+wSPWUEs1nLX4uaPJdks84IlKzAzcAobwWe49l1kXVF5mQbOwsfIFTQREPNRsTFRmtf0Aqrw2q k8oJChDdnQ2ZJfaAF6lK92Y7Uywc7NDVLkQmg21VwKHGY9ZFLPmAivgf5y+acIluAnt0m9a9HgY Gx2FxW03P0FM0JRxHIHMFyDFM8kpB+UX9X0r3DxRMB2stX2hlhryH6HXjRv3AhyTqczUhQZ/gUZ L4mQr0epIMJrYt6aivv+6PeC6yowY97Jh/NqBypIGquta1VVUZhxI/eHkuSonJO9+wWcIqo9WTo 2zlKxFWQVHOz1JhZgKaQoH6zgXXyZT8nyPLteelSEvG/1duBPmhJLNND+d4Ww5ATyOpCaT+xSBn fWUu+u7h1h7ObzKox0Vo9XaLr9mDYaU2a8XnoTs/3x1xs54VbAHMyiGH825y+GEsNVdS2ExWFm+ WXDMKfb5l4dd9Xg== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The MSM8226 SoC uses a slightly different 28nm dsi phy. Add a new compatible for it. Signed-off-by: Luca Weiss Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 1 + Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml index cf4a338c4661..bd70c3873ca9 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -18,6 +18,7 @@ properties: - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp + - qcom,dsi-phy-28nm-8226 - qcom,dsi-phy-28nm-8960 reg: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index b0100105e428..db9f07c6142d 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -125,6 +125,7 @@ patternProperties: - qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-8953 - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-8226 - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-lp - qcom,hdmi-phy-8084 From patchwork Mon May 29 09:43:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13258359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08E02C7EE29 for ; Mon, 29 May 2023 09:46:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231785AbjE2JqB (ORCPT ); Mon, 29 May 2023 05:46:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231531AbjE2Jp5 (ORCPT ); Mon, 29 May 2023 05:45:57 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 569F7188; Mon, 29 May 2023 02:45:31 -0700 (PDT) Received: from [192.168.122.1] (217-149-172-244.nat.highway.telekom.at [217.149.172.244]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 36AE0CFC26; Mon, 29 May 2023 09:44:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685353499; bh=WzMfGipgNDWNsOYbbUolxDAl9asoBs643I4DWeuO5wg=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=xsCTIVZ2XydPj4aTPBhFmEov3jF00sHQPwOFpcUWAa5xQWH6V7MK6Cmlz98kWAGzT BR/acMHLVbBqf6dKPAv+E8BJh7+Gb9F1kBxNoWZ+mHhJT45Wqp+mZQH+WY0y1CIv+6 MQdEbSoiwk6Vr70nPzTOxQUxsB5YVDEGWXE207hc= From: Luca Weiss Date: Mon, 29 May 2023 11:43:59 +0200 Subject: [PATCH 2/7] dt-bindings: display/msm: dsi-controller-main: Add msm8226 compatible MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v1-2-679f335d3d5b@z3ntu.xyz> References: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1059; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=WzMfGipgNDWNsOYbbUolxDAl9asoBs643I4DWeuO5wg=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkdHQUzO1mR9BwKnPmS8ocLKymVBUj1cJ4J6vHR 9Fmkuw+9CqJAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHR0FAAKCRBy2EO4nU3X VrvmEACG9nQBxjvX7hJykfZ4TC2iWDL/e/P3QD0g54i/5noyQc+SwwPSH2XedmFuQ0Iu9iCebPM VBp9IE0U+oNbZSx1A1dhVNm56mAmVEJizEfs5fhtBfnXC92oUYZbN4lM3P7PIb+boRm1qCcuHAz /errQCUMKcOytKA16SBFJHXJZCVPNUgVcr/0C29dMEa7AKB6GMk1AOzjBTnIYL3r+MH9bQ22VWS IJVSKrpPKoEysaLUMiO9MFSm7PizXMZeEBQHCOaAfKFRGhPqMIubSFcmPVsEc7Qr+u0EjhZITeq XTyC7JJvtqNHz/Bd77Lly8a13zg/yCsE1opWxT0dBHHfoCAC5moRElTimNXnpZX5vas9eU2TRD2 aDW/j8h1AqxuHtWQGV+F4eDpth1t/CtHqy9d+aR4gctlsxP/KYcMYvs4lJxt75GcuEIliAe2MgQ I3LZ73lAWVYeRx+8D5hdyixsk96X8OyKAsonK2izV3qCzWVHhoQ3kkRLKFLHduOnE5pUMqyvDWh 10dBmKSKel2dW8ZcQ10uJsHGXGPACOPriiScJ9AMkahPuIzqcFTa1ACPAkXIqjpU1yGhWQVq+pz /4IyBlF1e3pFD6A6o77XNY1uV91E0iRbhADdiAJTzSZA5foJoJlL7h7iLkN7HavLd/psanLxZA2 qwXHLt+GKHLj82g== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible for the DSI found on MSM8226. Signed-off-by: Luca Weiss Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 130e16d025bc..660e0f496826 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - qcom,apq8064-dsi-ctrl + - qcom,msm8226-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl @@ -256,6 +257,7 @@ allOf: compatible: contains: enum: + - qcom,msm8226-dsi-ctrl - qcom,msm8974-dsi-ctrl then: properties: From patchwork Mon May 29 09:44:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13258358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30909C7EE32 for ; Mon, 29 May 2023 09:46:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231761AbjE2JqD (ORCPT ); Mon, 29 May 2023 05:46:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231627AbjE2Jp5 (ORCPT ); Mon, 29 May 2023 05:45:57 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 278B3189; Mon, 29 May 2023 02:45:32 -0700 (PDT) Received: from [192.168.122.1] (217-149-172-244.nat.highway.telekom.at [217.149.172.244]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 0A12FCFC27; Mon, 29 May 2023 09:45:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685353500; bh=8sIn/Qz0l9jKCvWDS6LR4GIaadAQo/SQgllobL2+TqU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=gLvd+//fU8fm71mZT5VbhoBp3gOGZMq8gCEHZPqSbkZyTQ+xtFH29AR8vbs0rMxHr rQ9A8SM6a//+jRMIuyQBIlBABLEW5nvI90d8PCp7ioySfAvyvlxzXurLAtljYvJGRo dm99TjAQcRQEBpcZvsQcLMVcuNuaXj2kJCoFNjyo= From: Luca Weiss Date: Mon, 29 May 2023 11:44:00 +0200 Subject: [PATCH 3/7] dt-bindings: display/msm: qcom,mdp5: Add msm8226 compatible MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v1-3-679f335d3d5b@z3ntu.xyz> References: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=784; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=8sIn/Qz0l9jKCvWDS6LR4GIaadAQo/SQgllobL2+TqU=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkdHQVmzfdSUiOjj0rA8qZ4KUbvyyfYVN2HPCxI 1qYANeRNJ+JAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHR0FQAKCRBy2EO4nU3X VqhmD/9SaQzg08+ttAZ4k0pCFP0Jq/ngScWc1jWT1NLy6R3BuZB59NpszqGWm1dUssVUYgq1Jev RHjBxmrc6X6I4jFGZb9i3XyQw8I5SKyD4XhDrhukDf5mBfKa0Dsfn7Kmx8z7ElyDAmvdZXi77te iTdwBq/Gyf5LGPGgWW8PdBmFW3ROwkZ8MyEMS39Plvjuy5KLI2frOMsfC763SIrAsmmyNXSvTXH bZpXZp+86mxERPf9BI/9c6g8EVF+ecY1UX3BPfeBqOafi+cSy7YXw3GsCG/Ck5kob6fhD2DH+/b qJ8IGe0D5L/He1wTF0TDJgk7xazyprwr2aRUFn7n+yP0wpvZN8lxZAvN8R/G1JdohexGeM6xz9m lvyiL473bvXUKqXlGfa9CiZ6GtUTcoR1LisW+UBQHCYh+gV0HMvp1aVHNUShXCkIDX689owKqsD tXLKnwhhMqsV1TimiYjrFt3xf4pjeREez+RQgzXBCVU8n//J29LPK8088CRRFf2NM8x0s5VgAZp bBZgOJdWKPqhvLjeCPNtS1mIE9gX/ePb/HB8krNqRjH4QnoBhYn3+H09B+0SPI2IDTtex9df9WL w6/T05Lp0Whk0XozrKyqqz9IpiTIjIoe1T3PWVcGXPi052Sq6NK78INkGLh3kzo5SjrQNwf4gcS 5OlagslCJ67p+Yg== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible for the MDP5 found on MSM8226. Signed-off-by: Luca Weiss Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index a763cf8da122..2fe032d0e8f8 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -22,6 +22,7 @@ properties: - items: - enum: - qcom,apq8084-mdp5 + - qcom,msm8226-mdp5 - qcom,msm8916-mdp5 - qcom,msm8917-mdp5 - qcom,msm8953-mdp5 From patchwork Mon May 29 09:44:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13258354 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78DABC7EE32 for ; Mon, 29 May 2023 09:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231728AbjE2JpF (ORCPT ); Mon, 29 May 2023 05:45:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231719AbjE2JpE (ORCPT ); Mon, 29 May 2023 05:45:04 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 000DB90; Mon, 29 May 2023 02:45:02 -0700 (PDT) Received: from [192.168.122.1] (217-149-172-244.nat.highway.telekom.at [217.149.172.244]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id BFAECCFC28; Mon, 29 May 2023 09:45:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685353501; bh=Pvj7kBCbsncRN/r2Hw0hNp6SoznPdByBlaY/zEcd12o=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=VXAtWFzmQx4kMmbXVxJ0/jmTihf4UrGIeQkLpL+R6GblDaVyskNs80P6za/28yJ/K Clt1xm12l7JsJylg1YLvWtSXrDpFxy8Us53pSPaIWWSO+ZWSgLNt8/JQK4wDMQLmhI muG4CFJ6lfLHoeEsTL3sEimH4xzOAyvBJLVc75Sg= From: Luca Weiss Date: Mon, 29 May 2023 11:44:01 +0200 Subject: [PATCH 4/7] drm/msm/mdp5: Add MDP5 configuration for MSM8226 MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v1-4-679f335d3d5b@z3ntu.xyz> References: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2673; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=Pvj7kBCbsncRN/r2Hw0hNp6SoznPdByBlaY/zEcd12o=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkdHQWyEjmV/3z2MU1XlxJRVfIBRMSNKm7z5lbm 12NOYLf2emJAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHR0FgAKCRBy2EO4nU3X VoKvD/0WXNNBwPvWw6sReo8s/QeM2zmgoi9Y5n3wNabBguRjFnoTmZ7sxp4cXMmMvc5XIAesKJb +QitMyQy9JcfnXzc5Kp0XPSSmKfNYQMzvqmBsnCZswlk84PnRKz0NUz8+zaUfUyG7aN/3G98JDy k5F3S9Zd6Ho5A3322YWKeoLuPxqjLPE3WVMatZWmYnvY6jfYzmL8M2AbVsMnY1ClnaEU/ClWtk8 dI7PzSJ2vpZYSfzZO+Xvya+30SU6AmHUzqsRC/UepLLAxd1q4SPuPVxNezhy969xoxr5vCQbNWm oSVTPKdbL997vj1hwFTPLqEzNA7SgVdbyToPb03M7/KZZ3MPVBVMhS6Yka/LFSgzXfocuX6EgQZ mroGU7i0frgwEtYMi/Jq52M7H0MDKaFXzFSeuKed6yzfG0zpUW6i6liG1oGRICCZp/tWVwdiKAN ruzeOhP1bWMuNfOy4Pfpulijt3iOxuKtrMVwlaVQ6NCj7U61J640D6FrnX2z7b5xxDvR+0+1OUw hCD8UtVTP5S3URKTmVYHu71Mz9l7952HYiChQaQqgHGiZvBiQopvOjaC+1ow7rrsRnq3jEqWfib /kMPOLGIuOsADktLQx73Z8j0EvyjGH+3NvHZwioJvBjA82QLIcmVcn05b0OTHYVIj5ZZA4RjJt6 u9s8OyTA39pA6qA== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the required config for the v1.1 MDP5 found on MSM8226. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82 ++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 2eec2d78f32a..694d54341337 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -103,6 +103,87 @@ static const struct mdp5_cfg_hw msm8x74v1_config = { .max_clk = 200000000, }; +static const struct mdp5_cfg_hw msm8x26_config = { + .name = "msm8x26", + .mdp = { + .count = 1, + .caps = MDP_CAP_SMP | + 0, + }, + .smp = { + .mmb_count = 7, + .mmb_size = 4096, + .clients = { + [SSPP_VIG0] = 1, + [SSPP_DMA0] = 4, + [SSPP_RGB0] = 7, + }, + }, + .ctl = { + .count = 2, + .base = { 0x00500, 0x00600 }, + .flush_hw_mask = 0x0003ffff, + }, + .pipe_vig = { + .count = 1, + .base = { 0x01100 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | + MDP_PIPE_CAP_CSC | + 0, + }, + .pipe_rgb = { + .count = 1, + .base = { 0x01d00 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | + 0, + }, + .pipe_dma = { + .count = 1, + .base = { 0x02900 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + 0, + }, + .lm = { + .count = 2, + .base = { 0x03100, 0x03d00 }, + .instances = { + { .id = 0, .pp = 0, .dspp = 0, + .caps = MDP_LM_CAP_DISPLAY, }, + { .id = 1, .pp = -1, .dspp = -1, + .caps = MDP_LM_CAP_WB }, + }, + .nb_stages = 2, + .max_width = 2048, + .max_height = 0xFFFF, + }, + .dspp = { + .count = 1, + .base = { 0x04500 }, + }, + .pp = { + .count = 1, + .base = { 0x21a00 }, + }, + .intf = { + .base = { 0x00000, 0x21200 }, + .connect = { + [0] = INTF_DISABLED, + [1] = INTF_DSI, + }, + }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 125 + }, + .max_clk = 200000000, +}; + static const struct mdp5_cfg_hw msm8x74v2_config = { .name = "msm8x74", .mdp = { @@ -1236,6 +1317,7 @@ static const struct mdp5_cfg_hw sdm660_config = { static const struct mdp5_cfg_handler cfg_handlers_v1[] = { { .revision = 0, .config = { .hw = &msm8x74v1_config } }, + { .revision = 1, .config = { .hw = &msm8x26_config } }, { .revision = 2, .config = { .hw = &msm8x74v2_config } }, { .revision = 3, .config = { .hw = &apq8084_config } }, { .revision = 6, .config = { .hw = &msm8x16_config } }, From patchwork Mon May 29 09:44:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13258360 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCC51C7EE33 for ; Mon, 29 May 2023 09:46:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231789AbjE2JqE (ORCPT ); Mon, 29 May 2023 05:46:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231771AbjE2JqB (ORCPT ); Mon, 29 May 2023 05:46:01 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0857D133; Mon, 29 May 2023 02:45:34 -0700 (PDT) Received: from [192.168.122.1] (217-149-172-244.nat.highway.telekom.at [217.149.172.244]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 83F58CFC29; Mon, 29 May 2023 09:45:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685353502; bh=Pw/tZJzdE92dqB5g65+01DVbNHwSCp+HTkrhVc7vhDQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=xaTDwxwxipXWTzZ8oghu7wOEUErbqayRlrch8IEtgWPWG19IHihBvIB9MMlVpQlob 9OXzQF3L7WXCBslmKDtil2z94gZVfmzHdhz85GrDIUeKurmjhCErW1axLi4Z4J2/1j C/TBelcvKr+SDMTmSyIJweRul2RwB8o9IuDsikoI= From: Luca Weiss Date: Mon, 29 May 2023 11:44:02 +0200 Subject: [PATCH 5/7] drm/msm/dsi: Add configuration for MSM8226 MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v1-5-679f335d3d5b@z3ntu.xyz> References: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the config for the v1.0.2 DSI found on MSM8226. We can reuse existing bits from other revisions that are identical for v1.0.2. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 29ccd755cc2e..8a5fb6df7210 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -245,6 +245,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &apq8064_dsi_cfg, &msm_dsi_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0, &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0_2, + &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1, &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 91bdaf50bb1a..43f0dd74edb6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -11,6 +11,7 @@ #define MSM_DSI_VER_MAJOR_V2 0x02 #define MSM_DSI_VER_MAJOR_6G 0x03 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000 +#define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000 From patchwork Mon May 29 09:44:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13258355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66796C7EE29 for ; Mon, 29 May 2023 09:45:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231744AbjE2JpH (ORCPT ); Mon, 29 May 2023 05:45:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229521AbjE2JpG (ORCPT ); Mon, 29 May 2023 05:45:06 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D2838E; Mon, 29 May 2023 02:45:04 -0700 (PDT) Received: from [192.168.122.1] (217-149-172-244.nat.highway.telekom.at [217.149.172.244]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 4A6A3CFC2A; Mon, 29 May 2023 09:45:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685353503; bh=XT7iHcNZUhdhe+xkApreVmOVd5PsnMSUPY7AfB+cD1I=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=FG7SLk3shkRM6P4cY5S7Idb4rXYJsY59uXj+4MzH2InblW1pU3wuOw46Z92n9k70X UKShtL7fl4Sgzi/jotJDMCKwYB6DDBoIyb3ptQLHI9ebpHm0VdCvCuMBQuTpbkr97w 3kuMKl0zpQ0dCFE3sUklGj+iK/RQA8I6fT7pmFPI= From: Luca Weiss Date: Mon, 29 May 2023 11:44:03 +0200 Subject: [PATCH 6/7] drm/msm/dsi: Add phy configuration for MSM8226 MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v1-6-679f335d3d5b@z3ntu.xyz> References: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel. Worth noting that the msm-3.10 downstream kernel also will try other sequences in case this one doesn't work, but during testing it has shown that the _m sequence succeeds first time also: .pll_enable_seqs[0] = dsi_pll_enable_seq_m, .pll_enable_seqs[1] = dsi_pll_enable_seq_m, .pll_enable_seqs[2] = dsi_pll_enable_seq_d, .pll_enable_seqs[3] = dsi_pll_enable_seq_d, .pll_enable_seqs[4] = dsi_pll_enable_seq_f1, .pll_enable_seqs[5] = dsi_pll_enable_seq_c, .pll_enable_seqs[6] = dsi_pll_enable_seq_e, We may need to expand this in the future. Signed-off-by: Luca Weiss --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 97 ++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index bb09cbe8ff86..9d5795c58a98 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -541,6 +541,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_28nm_hpm_famb_cfgs }, { .compatible = "qcom,dsi-phy-28nm-lp", .data = &dsi_phy_28nm_lp_cfgs }, + { .compatible = "qcom,dsi-phy-28nm-8226", + .data = &dsi_phy_28nm_8226_cfgs }, #endif #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY { .compatible = "qcom,dsi-phy-20nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 7137a17ae523..8b640d174785 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -46,8 +46,9 @@ struct msm_dsi_phy_cfg { extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; -extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 4c1bf55c5f38..f71308387566 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -37,6 +37,7 @@ /* v2.0.0 28nm LP implementation */ #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) +#define DSI_PHY_28NM_QUIRK_PHY_8226 BIT(1) #define LPFR_LUT_SIZE 10 struct lpfr_cfg { @@ -377,6 +378,74 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) return ret; } +static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); + struct device *dev = &pll_28nm->phy->pdev->dev; + void __iomem *base = pll_28nm->phy->pll_base; + u32 max_reads = 5, timeout_us = 100; + bool locked; + u32 val; + int i; + + DBG("id=%d", pll_28nm->phy->id); + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; // 1 + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; // 4 + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; // 2 + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; // 8 + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + + for (i = 0; i < 7; i++) { + /* DSI Uniphy lock detect setting */ + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, + 0x0c, 100); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + + /* poll for PLL ready status */ + locked = pll_28nm_poll_for_ready(pll_28nm, + max_reads, timeout_us); + if (locked) + break; + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00, 50); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; // 1 + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; // 4 + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 100); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; // 2 + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; // 8 + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + } + + if (unlikely(!locked)) + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL Lock success"); + + return locked ? 0 : -EINVAL; +} + static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); @@ -471,6 +540,15 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { .is_enabled = dsi_pll_28nm_clk_is_enabled, }; +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = { + .round_rate = dsi_pll_28nm_clk_round_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = dsi_pll_28nm_vco_prepare_8226, + .unprepare = dsi_pll_28nm_vco_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + /* * PLL Callbacks */ @@ -536,6 +614,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; + else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226) + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_8226; else vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; @@ -820,3 +900,20 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, }; +const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = { + .has_phy_regulator = true, + .regulator_data = dsi_phy_28nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_init, + .save_pll_state = dsi_28nm_pll_save_state, + .restore_pll_state = dsi_28nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0xfd922b00 }, + .num_dsi_phy = 1, + .quirks = DSI_PHY_28NM_QUIRK_PHY_8226, +}; From patchwork Mon May 29 09:44:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13258356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 171DEC77B7E for ; Mon, 29 May 2023 09:45:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231753AbjE2JpI (ORCPT ); Mon, 29 May 2023 05:45:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231733AbjE2JpG (ORCPT ); Mon, 29 May 2023 05:45:06 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73C2D90; Mon, 29 May 2023 02:45:05 -0700 (PDT) Received: from [192.168.122.1] (217-149-172-244.nat.highway.telekom.at [217.149.172.244]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 1A7BCCFC2B; Mon, 29 May 2023 09:45:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685353503; bh=olIjx6WNF0x2y6WeKZc+6Pza/04SgAz6C7jo5EcOTi4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=p6UE9fXxzSn/W3LEX2Wav5xgnUoKZaGYthvYO9z5QQAHAM04kMSpmn6jT21acHtY6 48clhABsraBmdF4kyjO6tid9TD0ollHJoBVMTYPwSnChKof/e07BlaFCUhnEOxAcGr GimB6IpKAPvvkT1fdRDrpaPoFv5uxzmgT+tvtaUU= From: Luca Weiss Date: Mon, 29 May 2023 11:44:04 +0200 Subject: [PATCH 7/7] ARM: dts: qcom: msm8226: Add mdss nodes MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v1-7-679f335d3d5b@z3ntu.xyz> References: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v1-0-679f335d3d5b@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3341; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=olIjx6WNF0x2y6WeKZc+6Pza/04SgAz6C7jo5EcOTi4=; b=owEBbAKT/ZANAwAIAXLYQ7idTddWAcsmYgBkdHQY5R80arv9k0ADpEw1M/ChWf45zauAT8Z2m fs+d+RpiMaJAjIEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHR0GAAKCRBy2EO4nU3X VkYQD/iP2kg+TmrA9D35SoXw/U3mupRc57sfecIUJokolunxh4MPPfeL5D0/3JT0Q5nNw4W0aSJ hA+sjtfobYWpluNHDMuDsJ0/DWoSfLqfWmudtS4133dC5B/RcyEXbubj+j4eSk0rJ8I2NQoUVy9 Kme0Hha0vWs1U/GhFeGtTrwMilhFUpCgQGBvMqw/QTpL/7LOQ2Q+RNTr1giM51ne9Fcqsb8uRv/ /H1QOyvRLBYXLK7DnPlcg3IGFhTV1k8EhUpHupw8aZkg+BosxMrsm5WPYgpay/4vEKc89NZvSMY ObZ2S+SqhNZf/tYkstu+U9lV4aUwG4gNj8Q784jvSww4+wfTmikSKV8FTJ1i86AP6bIfcrOnVU5 8zOcuMm5YXNZdROr89hUCyJPq0nBxrEK/MAMoShvK8jHXVywrhotHNz1YgK1zj3CFbc4IwkGV4a SMTdfFLF1Rt9HAYfsvCz/CQ+9jotUu7PBqrVMwTFdHSB0Q8N3nvK/ax8ICUaJD72ha4YjaX92gm Yz6Lp1x8YpVEL9tUmBLVZbobPNy9NbUMhB/ax/LRP9m0P2Taz1JeVUEx8cNML7kpFj8sYh6Arf6 qPKs2MVsCpEBlCA7oEwCNfQhlfdE6f9pGSMBK8UwpjxEhFWzUaJEzTbEhbF4mc2RUUZJzTxxdI3 GeZAr3jjdUNyJ X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the nodes that describe the mdss so that display can work on MSM8226. Signed-off-by: Luca Weiss --- arch/arm/boot/dts/qcom-msm8226.dtsi | 118 ++++++++++++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 42acb9ddb8cc..182d6405032f 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -636,6 +636,124 @@ smd-edge { label = "lpass"; }; }; + + mdss: display-subsystem@fd900000 { + compatible = "qcom,mdss"; + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "vsync"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: display-controller@fd900000 { + compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; + reg = <0xfd900100 0x22000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: dsi@fd922800 { + compatible = "qcom,msm8226-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0xfd922800 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy0 0>, <&dsi_phy0 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&dsi_phy0>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi_phy0: phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-8226"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x280>, + <0xfd922d80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; + }; }; timer {