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Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=56264; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=cHhqOiBeb+YJ+YQIhFZNfZFWT5WvWpRnLnTzlg1R1Zo=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafdwf6BZ5LIs0Az5k2XIzPk189oao/E2T+7RYUX r9+McCiJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn3QAKCRB33NvayMhJ0R5pD/ 94rfrjGgo0FjVUcvzgJwIRYdvTywr7tn9aTma31SzzgypKRjOGInX+4bubEhj8C4evpIS/EuQ58bGq 4HKpGeQzyQVn9SpZ30f785T+G3RfFefrAuOkejWf0wF+6jWtZyCc/oVkZy8QvOz5rCc01cbaSWt/SB Pr9OP+4qsaSrBoQgGTwrb8KRcAGmz4Nh/vPJtA1bXA8UELm9F5YR9+UxPyJiRdbwnyIivwYXVALFU3 8EHzNB2B3EJ8XTKzgIF+heV/lJDJ7fQLrPxWUBLgAvV1lglcE/c0HZw3v72bRlRPhwSi328uqYXG6D srLCYr/JbfGua5XqIHBHe0MPDaLibpDbmTPG14riD2QbB88hZOgQmpk/i6zZIFBYim+KLbtQUenQ0z oWJ+oBHduro/o8yMRN7JNNGsSiVMIbg7BzDMRoJfrh9d37A8GuVuXjSoTGm9yQGeeNO/8f6UXoF0yu gC4To6GWfqktPtR3rL9LGjrut/fFWfjW8IolkYMtRq8UExKT78EbM8LC1ZPDmY+z/8FubGgtTkjr2R aMO0UVcYnb+fkLbnv59N9kVJwassFExcm7K8ywYSAc8n7IKnn+2bDENBhh2QMEfqOmRMMpOJ2QDdfX WUX87hT3zd958pqT4decszP3qEG6WXZG079SvngKV4F1iTwIoJc9Jj2ovZZw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_003818_362784_CCAD4AEA X-CRM114-Status: GOOD ( 10.42 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Exposing should not be done in a single commit anymore due to dt-bindings enforced rules. Prepend PRIV to the private CLK IDs so we can add new clock to the bindings header and in a separate commit remove such private define and switch to the public CLK IDs identifier. This refers to a discussion at [1] with Arnd and Krzysztof. [1] https://lore.kernel.org/all/2fabe721-7434-43e7-bae5-088a42ba128d@app.fastmail.com/ Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 628 +++++++++++++++++++++++------------------------ drivers/clk/meson/g12a.h | 260 ++++++++++---------- 2 files changed, 444 insertions(+), 444 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 310accf94830..d2e481ae2429 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4255,8 +4255,8 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, + [CLKID_PRIV_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, + [CLKID_PRIV_MPEG_DIV] = &g12a_mpeg_clk_div.hw, [CLKID_CLK81] = &g12a_clk81.hw, [CLKID_MPLL0] = &g12a_mpll0.hw, [CLKID_MPLL1] = &g12a_mpll1.hw, @@ -4307,25 +4307,25 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_UART2] = &g12a_uart2.hw, [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, [CLKID_GIC] = &g12a_gic.hw, - [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, - [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, - [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, - [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, - [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, - [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, - [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, - [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, + [CLKID_PRIV_MPLL0_DIV] = &g12a_mpll0_div.hw, + [CLKID_PRIV_MPLL1_DIV] = &g12a_mpll1_div.hw, + [CLKID_PRIV_MPLL2_DIV] = &g12a_mpll2_div.hw, + [CLKID_PRIV_MPLL3_DIV] = &g12a_mpll3_div.hw, + [CLKID_PRIV_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, + [CLKID_PRIV_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, + [CLKID_PRIV_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, + [CLKID_PRIV_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, + [CLKID_PRIV_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, + [CLKID_PRIV_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, @@ -4346,56 +4346,56 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, - [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, - [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, - [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, - [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, + [CLKID_PRIV_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, + [CLKID_PRIV_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, + [CLKID_PRIV_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, + [CLKID_PRIV_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, [CLKID_DMA] = &g12a_dma.hw, [CLKID_EFUSE] = &g12a_efuse.hw, [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, [CLKID_RESET_SEC] = &g12a_reset_sec.hw, [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, - [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, + [CLKID_PRIV_MPLL_PREDIV] = &g12a_mpll_prediv.hw, [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, + [CLKID_PRIV_VPU_0_DIV] = &g12a_vpu_0_div.hw, [CLKID_VPU_0] = &g12a_vpu_0.hw, [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, + [CLKID_PRIV_VPU_1_DIV] = &g12a_vpu_1_div.hw, [CLKID_VPU_1] = &g12a_vpu_1.hw, [CLKID_VPU] = &g12a_vpu.hw, [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, - [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, + [CLKID_PRIV_VAPB_0_DIV] = &g12a_vapb_0_div.hw, [CLKID_VAPB_0] = &g12a_vapb_0.hw, [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, - [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, + [CLKID_PRIV_VAPB_1_DIV] = &g12a_vapb_1_div.hw, [CLKID_VAPB_1] = &g12a_vapb_1.hw, [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, [CLKID_VAPB] = &g12a_vapb.hw, - [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, - [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, - [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, + [CLKID_PRIV_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, + [CLKID_PRIV_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, + [CLKID_PRIV_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, - [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, - [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, - [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, - [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, - [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, - [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, - [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, - [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, + [CLKID_PRIV_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, + [CLKID_PRIV_VID_PLL_DIV] = &g12a_vid_pll.hw, + [CLKID_PRIV_VCLK_SEL] = &g12a_vclk_sel.hw, + [CLKID_PRIV_VCLK2_SEL] = &g12a_vclk2_sel.hw, + [CLKID_PRIV_VCLK_INPUT] = &g12a_vclk_input.hw, + [CLKID_PRIV_VCLK2_INPUT] = &g12a_vclk2_input.hw, + [CLKID_PRIV_VCLK_DIV] = &g12a_vclk_div.hw, + [CLKID_PRIV_VCLK2_DIV] = &g12a_vclk2_div.hw, [CLKID_VCLK] = &g12a_vclk.hw, [CLKID_VCLK2] = &g12a_vclk2.hw, [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, - [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, - [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, - [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, - [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, + [CLKID_PRIV_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, + [CLKID_PRIV_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, + [CLKID_PRIV_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, + [CLKID_PRIV_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, - [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, + [CLKID_PRIV_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, + [CLKID_PRIV_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, + [CLKID_PRIV_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, + [CLKID_PRIV_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, @@ -4404,69 +4404,69 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, - [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, - [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, - [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, - [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, + [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, + [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, + [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, - [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, - [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, + [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, + [CLKID_PRIV_HDMI_DIV] = &g12a_hdmi_div.hw, [CLKID_HDMI] = &g12a_hdmi.hw, [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, - [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, + [CLKID_PRIV_MALI_0_DIV] = &g12a_mali_0_div.hw, [CLKID_MALI_0] = &g12a_mali_0.hw, [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, - [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, + [CLKID_PRIV_MALI_1_DIV] = &g12a_mali_1_div.hw, [CLKID_MALI_1] = &g12a_mali_1.hw, [CLKID_MALI] = &g12a_mali.hw, - [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, + [CLKID_PRIV_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, - [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, - [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, - [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, + [CLKID_PRIV_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, + [CLKID_PRIV_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, + [CLKID_PRIV_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, + [CLKID_PRIV_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, + [CLKID_PRIV_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, + [CLKID_PRIV_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, + [CLKID_PRIV_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, + [CLKID_PRIV_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, + [CLKID_PRIV_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, - [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, - [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, - [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, - [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, - [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, - [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, - [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, - [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, - [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, - [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, - [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, - [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, - [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, + [CLKID_PRIV_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, + [CLKID_PRIV_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, + [CLKID_PRIV_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, + [CLKID_PRIV_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, + [CLKID_PRIV_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, + [CLKID_PRIV_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, + [CLKID_PRIV_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, + [CLKID_PRIV_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, + [CLKID_PRIV_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, + [CLKID_PRIV_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, + [CLKID_PRIV_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, + [CLKID_PRIV_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, + [CLKID_PRIV_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, - [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, - [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, + [CLKID_PRIV_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, + [CLKID_PRIV_VDEC_1_DIV] = &g12a_vdec_1_div.hw, [CLKID_VDEC_1] = &g12a_vdec_1.hw, - [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, + [CLKID_PRIV_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, + [CLKID_PRIV_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, - [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, - [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, + [CLKID_PRIV_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, + [CLKID_PRIV_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, - [CLKID_TS_DIV] = &g12a_ts_div.hw, + [CLKID_PRIV_TS_DIV] = &g12a_ts_div.hw, [CLKID_TS] = &g12a_ts.hw, - [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, - [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_PRIV_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_PRIV_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, - [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, - [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_PRIV_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_PRIV_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, - [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, + [CLKID_PRIV_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, [NR_CLKS] = NULL, }, @@ -4484,8 +4484,8 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, + [CLKID_PRIV_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, + [CLKID_PRIV_MPEG_DIV] = &g12a_mpeg_clk_div.hw, [CLKID_CLK81] = &g12a_clk81.hw, [CLKID_MPLL0] = &g12a_mpll0.hw, [CLKID_MPLL1] = &g12a_mpll1.hw, @@ -4536,25 +4536,25 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_UART2] = &g12a_uart2.hw, [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, [CLKID_GIC] = &g12a_gic.hw, - [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, - [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, - [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, - [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, - [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, - [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, - [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, - [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, + [CLKID_PRIV_MPLL0_DIV] = &g12a_mpll0_div.hw, + [CLKID_PRIV_MPLL1_DIV] = &g12a_mpll1_div.hw, + [CLKID_PRIV_MPLL2_DIV] = &g12a_mpll2_div.hw, + [CLKID_PRIV_MPLL3_DIV] = &g12a_mpll3_div.hw, + [CLKID_PRIV_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, + [CLKID_PRIV_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, + [CLKID_PRIV_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, + [CLKID_PRIV_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, + [CLKID_PRIV_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, + [CLKID_PRIV_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, @@ -4575,56 +4575,56 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, - [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, - [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, - [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, - [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, + [CLKID_PRIV_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, + [CLKID_PRIV_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, + [CLKID_PRIV_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, + [CLKID_PRIV_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, [CLKID_DMA] = &g12a_dma.hw, [CLKID_EFUSE] = &g12a_efuse.hw, [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, [CLKID_RESET_SEC] = &g12a_reset_sec.hw, [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, - [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, + [CLKID_PRIV_MPLL_PREDIV] = &g12a_mpll_prediv.hw, [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, + [CLKID_PRIV_VPU_0_DIV] = &g12a_vpu_0_div.hw, [CLKID_VPU_0] = &g12a_vpu_0.hw, [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, + [CLKID_PRIV_VPU_1_DIV] = &g12a_vpu_1_div.hw, [CLKID_VPU_1] = &g12a_vpu_1.hw, [CLKID_VPU] = &g12a_vpu.hw, [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, - [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, + [CLKID_PRIV_VAPB_0_DIV] = &g12a_vapb_0_div.hw, [CLKID_VAPB_0] = &g12a_vapb_0.hw, [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, - [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, + [CLKID_PRIV_VAPB_1_DIV] = &g12a_vapb_1_div.hw, [CLKID_VAPB_1] = &g12a_vapb_1.hw, [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, [CLKID_VAPB] = &g12a_vapb.hw, - [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, - [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, - [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, + [CLKID_PRIV_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, + [CLKID_PRIV_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, + [CLKID_PRIV_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, - [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, - [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, - [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, - [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, - [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, - [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, - [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, - [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, + [CLKID_PRIV_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, + [CLKID_PRIV_VID_PLL_DIV] = &g12a_vid_pll.hw, + [CLKID_PRIV_VCLK_SEL] = &g12a_vclk_sel.hw, + [CLKID_PRIV_VCLK2_SEL] = &g12a_vclk2_sel.hw, + [CLKID_PRIV_VCLK_INPUT] = &g12a_vclk_input.hw, + [CLKID_PRIV_VCLK2_INPUT] = &g12a_vclk2_input.hw, + [CLKID_PRIV_VCLK_DIV] = &g12a_vclk_div.hw, + [CLKID_PRIV_VCLK2_DIV] = &g12a_vclk2_div.hw, [CLKID_VCLK] = &g12a_vclk.hw, [CLKID_VCLK2] = &g12a_vclk2.hw, [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, - [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, - [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, - [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, - [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, + [CLKID_PRIV_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, + [CLKID_PRIV_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, + [CLKID_PRIV_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, + [CLKID_PRIV_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, - [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, + [CLKID_PRIV_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, + [CLKID_PRIV_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, + [CLKID_PRIV_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, + [CLKID_PRIV_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, @@ -4633,104 +4633,104 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, - [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, - [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, - [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, - [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, + [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, + [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, + [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, - [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, - [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, + [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, + [CLKID_PRIV_HDMI_DIV] = &g12a_hdmi_div.hw, [CLKID_HDMI] = &g12a_hdmi.hw, [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, - [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, + [CLKID_PRIV_MALI_0_DIV] = &g12a_mali_0_div.hw, [CLKID_MALI_0] = &g12a_mali_0.hw, [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, - [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, + [CLKID_PRIV_MALI_1_DIV] = &g12a_mali_1_div.hw, [CLKID_MALI_1] = &g12a_mali_1.hw, [CLKID_MALI] = &g12a_mali.hw, - [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, + [CLKID_PRIV_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, - [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, - [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, - [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, + [CLKID_PRIV_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, + [CLKID_PRIV_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, + [CLKID_PRIV_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, + [CLKID_PRIV_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, + [CLKID_PRIV_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, + [CLKID_PRIV_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, + [CLKID_PRIV_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, + [CLKID_PRIV_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, + [CLKID_PRIV_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, [CLKID_CPU_CLK] = &g12b_cpu_clk.hw, - [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, - [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, - [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, - [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, - [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, - [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, - [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, - [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, - [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, - [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, - [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, - [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, - [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, + [CLKID_PRIV_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, + [CLKID_PRIV_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, + [CLKID_PRIV_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, + [CLKID_PRIV_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, + [CLKID_PRIV_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, + [CLKID_PRIV_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, + [CLKID_PRIV_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, + [CLKID_PRIV_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, + [CLKID_PRIV_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, + [CLKID_PRIV_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, + [CLKID_PRIV_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, + [CLKID_PRIV_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, + [CLKID_PRIV_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, - [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, - [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, + [CLKID_PRIV_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, + [CLKID_PRIV_VDEC_1_DIV] = &g12a_vdec_1_div.hw, [CLKID_VDEC_1] = &g12a_vdec_1.hw, - [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, + [CLKID_PRIV_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, + [CLKID_PRIV_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, - [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, - [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, + [CLKID_PRIV_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, + [CLKID_PRIV_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, - [CLKID_TS_DIV] = &g12a_ts_div.hw, + [CLKID_PRIV_TS_DIV] = &g12a_ts_div.hw, [CLKID_TS] = &g12a_ts.hw, - [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw, - [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw, - [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw, - [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw, - [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw, - [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw, - [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw, - [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw, - [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw, - [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw, - [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw, + [CLKID_PRIV_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw, + [CLKID_PRIV_SYS1_PLL] = &g12b_sys1_pll.hw, + [CLKID_PRIV_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw, + [CLKID_PRIV_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw, + [CLKID_PRIV_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw, + [CLKID_PRIV_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw, + [CLKID_PRIV_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw, + [CLKID_PRIV_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw, + [CLKID_PRIV_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw, + [CLKID_PRIV_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw, + [CLKID_PRIV_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw, [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw, - [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw, - [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw, - [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw, - [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw, - [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw, - [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw, - [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw, - [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw, - [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw, - [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw, - [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw, - [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw, - [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw, - [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw, - [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw, - [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw, - [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw, - [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, - [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_PRIV_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw, + [CLKID_PRIV_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw, + [CLKID_PRIV_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw, + [CLKID_PRIV_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw, + [CLKID_PRIV_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw, + [CLKID_PRIV_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw, + [CLKID_PRIV_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw, + [CLKID_PRIV_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw, + [CLKID_PRIV_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw, + [CLKID_PRIV_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw, + [CLKID_PRIV_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw, + [CLKID_PRIV_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw, + [CLKID_PRIV_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw, + [CLKID_PRIV_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw, + [CLKID_PRIV_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw, + [CLKID_PRIV_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw, + [CLKID_PRIV_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw, + [CLKID_PRIV_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_PRIV_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, - [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, - [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_PRIV_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_PRIV_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, - [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, - [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, + [CLKID_PRIV_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, + [CLKID_PRIV_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw, - [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, - [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, + [CLKID_PRIV_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, + [CLKID_PRIV_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw, [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, - [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, + [CLKID_PRIV_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, [NR_CLKS] = NULL, }, @@ -4748,8 +4748,8 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, - [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, - [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, + [CLKID_PRIV_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, + [CLKID_PRIV_MPEG_DIV] = &g12a_mpeg_clk_div.hw, [CLKID_CLK81] = &g12a_clk81.hw, [CLKID_MPLL0] = &g12a_mpll0.hw, [CLKID_MPLL1] = &g12a_mpll1.hw, @@ -4800,25 +4800,25 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_UART2] = &g12a_uart2.hw, [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, [CLKID_GIC] = &g12a_gic.hw, - [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, - [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, - [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, - [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, - [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, - [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, + [CLKID_PRIV_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, + [CLKID_PRIV_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, - [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, - [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, - [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, - [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, - [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, - [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, - [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, - [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, - [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, - [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, + [CLKID_PRIV_MPLL0_DIV] = &g12a_mpll0_div.hw, + [CLKID_PRIV_MPLL1_DIV] = &g12a_mpll1_div.hw, + [CLKID_PRIV_MPLL2_DIV] = &g12a_mpll2_div.hw, + [CLKID_PRIV_MPLL3_DIV] = &g12a_mpll3_div.hw, + [CLKID_PRIV_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, + [CLKID_PRIV_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, + [CLKID_PRIV_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, + [CLKID_PRIV_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, + [CLKID_PRIV_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, + [CLKID_PRIV_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, @@ -4839,56 +4839,56 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, - [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, - [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, - [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, - [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, + [CLKID_PRIV_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, + [CLKID_PRIV_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, + [CLKID_PRIV_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, + [CLKID_PRIV_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, [CLKID_DMA] = &g12a_dma.hw, [CLKID_EFUSE] = &g12a_efuse.hw, [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, [CLKID_RESET_SEC] = &g12a_reset_sec.hw, [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, - [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, + [CLKID_PRIV_MPLL_PREDIV] = &g12a_mpll_prediv.hw, [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, - [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, + [CLKID_PRIV_VPU_0_DIV] = &g12a_vpu_0_div.hw, [CLKID_VPU_0] = &g12a_vpu_0.hw, [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, - [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, + [CLKID_PRIV_VPU_1_DIV] = &g12a_vpu_1_div.hw, [CLKID_VPU_1] = &g12a_vpu_1.hw, [CLKID_VPU] = &g12a_vpu.hw, [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, - [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, + [CLKID_PRIV_VAPB_0_DIV] = &g12a_vapb_0_div.hw, [CLKID_VAPB_0] = &g12a_vapb_0.hw, [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, - [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, + [CLKID_PRIV_VAPB_1_DIV] = &g12a_vapb_1_div.hw, [CLKID_VAPB_1] = &g12a_vapb_1.hw, [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, [CLKID_VAPB] = &g12a_vapb.hw, - [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, - [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, - [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, + [CLKID_PRIV_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, + [CLKID_PRIV_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, + [CLKID_PRIV_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, - [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, - [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, - [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, - [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, - [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, - [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, - [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, - [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, + [CLKID_PRIV_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, + [CLKID_PRIV_VID_PLL_DIV] = &g12a_vid_pll.hw, + [CLKID_PRIV_VCLK_SEL] = &g12a_vclk_sel.hw, + [CLKID_PRIV_VCLK2_SEL] = &g12a_vclk2_sel.hw, + [CLKID_PRIV_VCLK_INPUT] = &g12a_vclk_input.hw, + [CLKID_PRIV_VCLK2_INPUT] = &g12a_vclk2_input.hw, + [CLKID_PRIV_VCLK_DIV] = &g12a_vclk_div.hw, + [CLKID_PRIV_VCLK2_DIV] = &g12a_vclk2_div.hw, [CLKID_VCLK] = &g12a_vclk.hw, [CLKID_VCLK2] = &g12a_vclk2.hw, [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, - [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, - [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, - [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, - [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, + [CLKID_PRIV_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, + [CLKID_PRIV_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, + [CLKID_PRIV_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, + [CLKID_PRIV_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, - [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, - [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, - [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, - [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, + [CLKID_PRIV_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, + [CLKID_PRIV_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, + [CLKID_PRIV_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, + [CLKID_PRIV_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, @@ -4897,89 +4897,89 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, - [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, - [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, - [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, - [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, + [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, + [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, + [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, - [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, - [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, + [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, + [CLKID_PRIV_HDMI_DIV] = &g12a_hdmi_div.hw, [CLKID_HDMI] = &g12a_hdmi.hw, [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, - [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, + [CLKID_PRIV_MALI_0_DIV] = &g12a_mali_0_div.hw, [CLKID_MALI_0] = &g12a_mali_0.hw, [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, - [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, + [CLKID_PRIV_MALI_1_DIV] = &g12a_mali_1_div.hw, [CLKID_MALI_1] = &g12a_mali_1.hw, [CLKID_MALI] = &g12a_mali.hw, - [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, + [CLKID_PRIV_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw, [CLKID_MPLL_50M] = &g12a_mpll_50m.hw, - [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, - [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, - [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, - [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, - [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, - [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, - [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, - [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, - [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, + [CLKID_PRIV_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw, + [CLKID_PRIV_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw, + [CLKID_PRIV_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw, + [CLKID_PRIV_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw, + [CLKID_PRIV_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw, + [CLKID_PRIV_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw, + [CLKID_PRIV_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw, + [CLKID_PRIV_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw, + [CLKID_PRIV_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw, [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, - [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, - [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, - [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, - [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, - [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, - [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, - [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, - [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, - [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, - [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, - [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, - [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, - [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, + [CLKID_PRIV_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw, + [CLKID_PRIV_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw, + [CLKID_PRIV_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw, + [CLKID_PRIV_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw, + [CLKID_PRIV_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw, + [CLKID_PRIV_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw, + [CLKID_PRIV_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw, + [CLKID_PRIV_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw, + [CLKID_PRIV_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw, + [CLKID_PRIV_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw, + [CLKID_PRIV_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw, + [CLKID_PRIV_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw, + [CLKID_PRIV_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw, [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, - [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, - [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw, + [CLKID_PRIV_VDEC_1_SEL] = &g12a_vdec_1_sel.hw, + [CLKID_PRIV_VDEC_1_DIV] = &g12a_vdec_1_div.hw, [CLKID_VDEC_1] = &g12a_vdec_1.hw, - [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, - [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, + [CLKID_PRIV_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw, + [CLKID_PRIV_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw, [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw, - [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, - [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, + [CLKID_PRIV_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw, + [CLKID_PRIV_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw, [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw, - [CLKID_TS_DIV] = &g12a_ts_div.hw, + [CLKID_PRIV_TS_DIV] = &g12a_ts_div.hw, [CLKID_TS] = &g12a_ts.hw, - [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw, + [CLKID_PRIV_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw, [CLKID_GP1_PLL] = &sm1_gp1_pll.hw, - [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw, - [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw, - [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw, - [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw, - [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw, - [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw, - [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw, - [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw, + [CLKID_PRIV_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw, + [CLKID_PRIV_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw, + [CLKID_PRIV_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw, + [CLKID_PRIV_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw, + [CLKID_PRIV_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw, + [CLKID_PRIV_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw, + [CLKID_PRIV_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw, + [CLKID_PRIV_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw, [CLKID_DSU_CLK] = &sm1_dsu_clk.hw, [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw, [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw, [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw, - [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, - [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, + [CLKID_PRIV_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw, + [CLKID_PRIV_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw, [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw, - [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, - [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, + [CLKID_PRIV_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw, + [CLKID_PRIV_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw, [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw, - [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, - [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, + [CLKID_PRIV_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw, + [CLKID_PRIV_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw, [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw, - [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, - [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, + [CLKID_PRIV_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw, + [CLKID_PRIV_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw, [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw, [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw, - [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, + [CLKID_PRIV_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw, [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw, [NR_CLKS] = NULL, }, @@ -5246,7 +5246,7 @@ static int meson_g12a_dvfs_setup_common(struct device *dev, struct clk_hw *xtal; int ret; - xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0); + xtal = clk_hw_get_parent_by_index(hws[CLKID_PRIV_CPU_CLK_DYN1_SEL], 0); /* Setup clock notifier for cpu_clk_postmux0 */ g12a_cpu_clk_postmux0_nb_data.xtal = xtal; @@ -5284,7 +5284,7 @@ static int meson_g12b_dvfs_setup(struct platform_device *pdev) if (ret) return ret; - xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0); + xtal = clk_hw_get_parent_by_index(hws[CLKID_PRIV_CPU_CLK_DYN1_SEL], 0); /* Setup clock notifier for cpu_clk mux */ notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw, diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index a97613df38b3..a57f4a9717db 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -135,136 +135,136 @@ * to expose, such as the internal muxes and dividers of composite clocks, * will remain defined here. */ -#define CLKID_MPEG_SEL 8 -#define CLKID_MPEG_DIV 9 -#define CLKID_SD_EMMC_A_CLK0_SEL 63 -#define CLKID_SD_EMMC_A_CLK0_DIV 64 -#define CLKID_SD_EMMC_B_CLK0_SEL 65 -#define CLKID_SD_EMMC_B_CLK0_DIV 66 -#define CLKID_SD_EMMC_C_CLK0_SEL 67 -#define CLKID_SD_EMMC_C_CLK0_DIV 68 -#define CLKID_MPLL0_DIV 69 -#define CLKID_MPLL1_DIV 70 -#define CLKID_MPLL2_DIV 71 -#define CLKID_MPLL3_DIV 72 -#define CLKID_MPLL_PREDIV 73 -#define CLKID_FCLK_DIV2_DIV 75 -#define CLKID_FCLK_DIV3_DIV 76 -#define CLKID_FCLK_DIV4_DIV 77 -#define CLKID_FCLK_DIV5_DIV 78 -#define CLKID_FCLK_DIV7_DIV 79 -#define CLKID_FCLK_DIV2P5_DIV 100 -#define CLKID_FIXED_PLL_DCO 101 -#define CLKID_SYS_PLL_DCO 102 -#define CLKID_GP0_PLL_DCO 103 -#define CLKID_HIFI_PLL_DCO 104 -#define CLKID_VPU_0_DIV 111 -#define CLKID_VPU_1_DIV 114 -#define CLKID_VAPB_0_DIV 118 -#define CLKID_VAPB_1_DIV 121 -#define CLKID_HDMI_PLL_DCO 125 -#define CLKID_HDMI_PLL_OD 126 -#define CLKID_HDMI_PLL_OD2 127 -#define CLKID_VID_PLL_SEL 130 -#define CLKID_VID_PLL_DIV 131 -#define CLKID_VCLK_SEL 132 -#define CLKID_VCLK2_SEL 133 -#define CLKID_VCLK_INPUT 134 -#define CLKID_VCLK2_INPUT 135 -#define CLKID_VCLK_DIV 136 -#define CLKID_VCLK2_DIV 137 -#define CLKID_VCLK_DIV2_EN 140 -#define CLKID_VCLK_DIV4_EN 141 -#define CLKID_VCLK_DIV6_EN 142 -#define CLKID_VCLK_DIV12_EN 143 -#define CLKID_VCLK2_DIV2_EN 144 -#define CLKID_VCLK2_DIV4_EN 145 -#define CLKID_VCLK2_DIV6_EN 146 -#define CLKID_VCLK2_DIV12_EN 147 -#define CLKID_CTS_ENCI_SEL 158 -#define CLKID_CTS_ENCP_SEL 159 -#define CLKID_CTS_VDAC_SEL 160 -#define CLKID_HDMI_TX_SEL 161 -#define CLKID_HDMI_SEL 166 -#define CLKID_HDMI_DIV 167 -#define CLKID_MALI_0_DIV 170 -#define CLKID_MALI_1_DIV 173 -#define CLKID_MPLL_50M_DIV 176 -#define CLKID_SYS_PLL_DIV16_EN 178 -#define CLKID_SYS_PLL_DIV16 179 -#define CLKID_CPU_CLK_DYN0_SEL 180 -#define CLKID_CPU_CLK_DYN0_DIV 181 -#define CLKID_CPU_CLK_DYN0 182 -#define CLKID_CPU_CLK_DYN1_SEL 183 -#define CLKID_CPU_CLK_DYN1_DIV 184 -#define CLKID_CPU_CLK_DYN1 185 -#define CLKID_CPU_CLK_DYN 186 -#define CLKID_CPU_CLK_DIV16_EN 188 -#define CLKID_CPU_CLK_DIV16 189 -#define CLKID_CPU_CLK_APB_DIV 190 -#define CLKID_CPU_CLK_APB 191 -#define CLKID_CPU_CLK_ATB_DIV 192 -#define CLKID_CPU_CLK_ATB 193 -#define CLKID_CPU_CLK_AXI_DIV 194 -#define CLKID_CPU_CLK_AXI 195 -#define CLKID_CPU_CLK_TRACE_DIV 196 -#define CLKID_CPU_CLK_TRACE 197 -#define CLKID_PCIE_PLL_DCO 198 -#define CLKID_PCIE_PLL_DCO_DIV2 199 -#define CLKID_PCIE_PLL_OD 200 -#define CLKID_VDEC_1_SEL 202 -#define CLKID_VDEC_1_DIV 203 -#define CLKID_VDEC_HEVC_SEL 205 -#define CLKID_VDEC_HEVC_DIV 206 -#define CLKID_VDEC_HEVCF_SEL 208 -#define CLKID_VDEC_HEVCF_DIV 209 -#define CLKID_TS_DIV 211 -#define CLKID_SYS1_PLL_DCO 213 -#define CLKID_SYS1_PLL 214 -#define CLKID_SYS1_PLL_DIV16_EN 215 -#define CLKID_SYS1_PLL_DIV16 216 -#define CLKID_CPUB_CLK_DYN0_SEL 217 -#define CLKID_CPUB_CLK_DYN0_DIV 218 -#define CLKID_CPUB_CLK_DYN0 219 -#define CLKID_CPUB_CLK_DYN1_SEL 220 -#define CLKID_CPUB_CLK_DYN1_DIV 221 -#define CLKID_CPUB_CLK_DYN1 222 -#define CLKID_CPUB_CLK_DYN 223 -#define CLKID_CPUB_CLK_DIV16_EN 225 -#define CLKID_CPUB_CLK_DIV16 226 -#define CLKID_CPUB_CLK_DIV2 227 -#define CLKID_CPUB_CLK_DIV3 228 -#define CLKID_CPUB_CLK_DIV4 229 -#define CLKID_CPUB_CLK_DIV5 230 -#define CLKID_CPUB_CLK_DIV6 231 -#define CLKID_CPUB_CLK_DIV7 232 -#define CLKID_CPUB_CLK_DIV8 233 -#define CLKID_CPUB_CLK_APB_SEL 234 -#define CLKID_CPUB_CLK_APB 235 -#define CLKID_CPUB_CLK_ATB_SEL 236 -#define CLKID_CPUB_CLK_ATB 237 -#define CLKID_CPUB_CLK_AXI_SEL 238 -#define CLKID_CPUB_CLK_AXI 239 -#define CLKID_CPUB_CLK_TRACE_SEL 240 -#define CLKID_CPUB_CLK_TRACE 241 -#define CLKID_GP1_PLL_DCO 242 -#define CLKID_DSU_CLK_DYN0_SEL 244 -#define CLKID_DSU_CLK_DYN0_DIV 245 -#define CLKID_DSU_CLK_DYN0 246 -#define CLKID_DSU_CLK_DYN1_SEL 247 -#define CLKID_DSU_CLK_DYN1_DIV 248 -#define CLKID_DSU_CLK_DYN1 249 -#define CLKID_DSU_CLK_DYN 250 -#define CLKID_DSU_CLK_FINAL 251 -#define CLKID_SPICC0_SCLK_SEL 256 -#define CLKID_SPICC0_SCLK_DIV 257 -#define CLKID_SPICC1_SCLK_SEL 259 -#define CLKID_SPICC1_SCLK_DIV 260 -#define CLKID_NNA_AXI_CLK_SEL 262 -#define CLKID_NNA_AXI_CLK_DIV 263 -#define CLKID_NNA_CORE_CLK_SEL 265 -#define CLKID_NNA_CORE_CLK_DIV 266 -#define CLKID_MIPI_DSI_PXCLK_DIV 268 +#define CLKID_PRIV_MPEG_SEL 8 +#define CLKID_PRIV_MPEG_DIV 9 +#define CLKID_PRIV_SD_EMMC_A_CLK0_SEL 63 +#define CLKID_PRIV_SD_EMMC_A_CLK0_DIV 64 +#define CLKID_PRIV_SD_EMMC_B_CLK0_SEL 65 +#define CLKID_PRIV_SD_EMMC_B_CLK0_DIV 66 +#define CLKID_PRIV_SD_EMMC_C_CLK0_SEL 67 +#define CLKID_PRIV_SD_EMMC_C_CLK0_DIV 68 +#define CLKID_PRIV_MPLL0_DIV 69 +#define CLKID_PRIV_MPLL1_DIV 70 +#define CLKID_PRIV_MPLL2_DIV 71 +#define CLKID_PRIV_MPLL3_DIV 72 +#define CLKID_PRIV_MPLL_PREDIV 73 +#define CLKID_PRIV_FCLK_DIV2_DIV 75 +#define CLKID_PRIV_FCLK_DIV3_DIV 76 +#define CLKID_PRIV_FCLK_DIV4_DIV 77 +#define CLKID_PRIV_FCLK_DIV5_DIV 78 +#define CLKID_PRIV_FCLK_DIV7_DIV 79 +#define CLKID_PRIV_FCLK_DIV2P5_DIV 100 +#define CLKID_PRIV_FIXED_PLL_DCO 101 +#define CLKID_PRIV_SYS_PLL_DCO 102 +#define CLKID_PRIV_GP0_PLL_DCO 103 +#define CLKID_PRIV_HIFI_PLL_DCO 104 +#define CLKID_PRIV_VPU_0_DIV 111 +#define CLKID_PRIV_VPU_1_DIV 114 +#define CLKID_PRIV_VAPB_0_DIV 118 +#define CLKID_PRIV_VAPB_1_DIV 121 +#define CLKID_PRIV_HDMI_PLL_DCO 125 +#define CLKID_PRIV_HDMI_PLL_OD 126 +#define CLKID_PRIV_HDMI_PLL_OD2 127 +#define CLKID_PRIV_VID_PLL_SEL 130 +#define CLKID_PRIV_VID_PLL_DIV 131 +#define CLKID_PRIV_VCLK_SEL 132 +#define CLKID_PRIV_VCLK2_SEL 133 +#define CLKID_PRIV_VCLK_INPUT 134 +#define CLKID_PRIV_VCLK2_INPUT 135 +#define CLKID_PRIV_VCLK_DIV 136 +#define CLKID_PRIV_VCLK2_DIV 137 +#define CLKID_PRIV_VCLK_DIV2_EN 140 +#define CLKID_PRIV_VCLK_DIV4_EN 141 +#define CLKID_PRIV_VCLK_DIV6_EN 142 +#define CLKID_PRIV_VCLK_DIV12_EN 143 +#define CLKID_PRIV_VCLK2_DIV2_EN 144 +#define CLKID_PRIV_VCLK2_DIV4_EN 145 +#define CLKID_PRIV_VCLK2_DIV6_EN 146 +#define CLKID_PRIV_VCLK2_DIV12_EN 147 +#define CLKID_PRIV_CTS_ENCI_SEL 158 +#define CLKID_PRIV_CTS_ENCP_SEL 159 +#define CLKID_PRIV_CTS_VDAC_SEL 160 +#define CLKID_PRIV_HDMI_TX_SEL 161 +#define CLKID_PRIV_HDMI_SEL 166 +#define CLKID_PRIV_HDMI_DIV 167 +#define CLKID_PRIV_MALI_0_DIV 170 +#define CLKID_PRIV_MALI_1_DIV 173 +#define CLKID_PRIV_MPLL_50M_DIV 176 +#define CLKID_PRIV_SYS_PLL_DIV16_EN 178 +#define CLKID_PRIV_SYS_PLL_DIV16 179 +#define CLKID_PRIV_CPU_CLK_DYN0_SEL 180 +#define CLKID_PRIV_CPU_CLK_DYN0_DIV 181 +#define CLKID_PRIV_CPU_CLK_DYN0 182 +#define CLKID_PRIV_CPU_CLK_DYN1_SEL 183 +#define CLKID_PRIV_CPU_CLK_DYN1_DIV 184 +#define CLKID_PRIV_CPU_CLK_DYN1 185 +#define CLKID_PRIV_CPU_CLK_DYN 186 +#define CLKID_PRIV_CPU_CLK_DIV16_EN 188 +#define CLKID_PRIV_CPU_CLK_DIV16 189 +#define CLKID_PRIV_CPU_CLK_APB_DIV 190 +#define CLKID_PRIV_CPU_CLK_APB 191 +#define CLKID_PRIV_CPU_CLK_ATB_DIV 192 +#define CLKID_PRIV_CPU_CLK_ATB 193 +#define CLKID_PRIV_CPU_CLK_AXI_DIV 194 +#define CLKID_PRIV_CPU_CLK_AXI 195 +#define CLKID_PRIV_CPU_CLK_TRACE_DIV 196 +#define CLKID_PRIV_CPU_CLK_TRACE 197 +#define CLKID_PRIV_PCIE_PLL_DCO 198 +#define CLKID_PRIV_PCIE_PLL_DCO_DIV2 199 +#define CLKID_PRIV_PCIE_PLL_OD 200 +#define CLKID_PRIV_VDEC_1_SEL 202 +#define CLKID_PRIV_VDEC_1_DIV 203 +#define CLKID_PRIV_VDEC_HEVC_SEL 205 +#define CLKID_PRIV_VDEC_HEVC_DIV 206 +#define CLKID_PRIV_VDEC_HEVCF_SEL 208 +#define CLKID_PRIV_VDEC_HEVCF_DIV 209 +#define CLKID_PRIV_TS_DIV 211 +#define CLKID_PRIV_SYS1_PLL_DCO 213 +#define CLKID_PRIV_SYS1_PLL 214 +#define CLKID_PRIV_SYS1_PLL_DIV16_EN 215 +#define CLKID_PRIV_SYS1_PLL_DIV16 216 +#define CLKID_PRIV_CPUB_CLK_DYN0_SEL 217 +#define CLKID_PRIV_CPUB_CLK_DYN0_DIV 218 +#define CLKID_PRIV_CPUB_CLK_DYN0 219 +#define CLKID_PRIV_CPUB_CLK_DYN1_SEL 220 +#define CLKID_PRIV_CPUB_CLK_DYN1_DIV 221 +#define CLKID_PRIV_CPUB_CLK_DYN1 222 +#define CLKID_PRIV_CPUB_CLK_DYN 223 +#define CLKID_PRIV_CPUB_CLK_DIV16_EN 225 +#define CLKID_PRIV_CPUB_CLK_DIV16 226 +#define CLKID_PRIV_CPUB_CLK_DIV2 227 +#define CLKID_PRIV_CPUB_CLK_DIV3 228 +#define CLKID_PRIV_CPUB_CLK_DIV4 229 +#define CLKID_PRIV_CPUB_CLK_DIV5 230 +#define CLKID_PRIV_CPUB_CLK_DIV6 231 +#define CLKID_PRIV_CPUB_CLK_DIV7 232 +#define CLKID_PRIV_CPUB_CLK_DIV8 233 +#define CLKID_PRIV_CPUB_CLK_APB_SEL 234 +#define CLKID_PRIV_CPUB_CLK_APB 235 +#define CLKID_PRIV_CPUB_CLK_ATB_SEL 236 +#define CLKID_PRIV_CPUB_CLK_ATB 237 +#define CLKID_PRIV_CPUB_CLK_AXI_SEL 238 +#define CLKID_PRIV_CPUB_CLK_AXI 239 +#define CLKID_PRIV_CPUB_CLK_TRACE_SEL 240 +#define CLKID_PRIV_CPUB_CLK_TRACE 241 +#define CLKID_PRIV_GP1_PLL_DCO 242 +#define CLKID_PRIV_DSU_CLK_DYN0_SEL 244 +#define CLKID_PRIV_DSU_CLK_DYN0_DIV 245 +#define CLKID_PRIV_DSU_CLK_DYN0 246 +#define CLKID_PRIV_DSU_CLK_DYN1_SEL 247 +#define CLKID_PRIV_DSU_CLK_DYN1_DIV 248 +#define CLKID_PRIV_DSU_CLK_DYN1 249 +#define CLKID_PRIV_DSU_CLK_DYN 250 +#define CLKID_PRIV_DSU_CLK_FINAL 251 +#define CLKID_PRIV_SPICC0_SCLK_SEL 256 +#define CLKID_PRIV_SPICC0_SCLK_DIV 257 +#define CLKID_PRIV_SPICC1_SCLK_SEL 259 +#define CLKID_PRIV_SPICC1_SCLK_DIV 260 +#define CLKID_PRIV_NNA_AXI_CLK_SEL 262 +#define CLKID_PRIV_NNA_AXI_CLK_DIV 263 +#define CLKID_PRIV_NNA_CORE_CLK_SEL 265 +#define CLKID_PRIV_NNA_CORE_CLK_DIV 266 +#define CLKID_PRIV_MIPI_DSI_PXCLK_DIV 268 #define NR_CLKS 271 From patchwork Tue May 30 07:38:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong 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Subject: [PATCH v5 02/17] clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-2-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4770; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=YshimAv78sTusx5XlbLyLaKmvGYFuT/Nlues9OXV98A=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafdZGnB9zL+CgnVBMve1Z9B0LfgNI/N9xYPM8bx JoupRWiJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn3QAKCRB33NvayMhJ0Rl7EA CJucqpVwIaz1WC0N5elAKMHy0ZF1CnPdHViDAjTl5eMgn20LIrKiWHzVEJCQYdpHUDvPsdsUjLbPol hIXuZOUC4KyTS/dVAwlapVMxSOTolFQQwFBSnc7u98i18ElJu9ONLburHqKdNdtdkvFMi7Q41+Uqu0 wkMxecsNgWxUJlN12Zgd0EoynpJEwy8Useyf8fSc5/XqIF96HpITRB4uPQIMVB7ONHwaLhY8vJD+Oe RsASCAup7UujZWZQor7gksEW4VRWO/EUNGzTIadFkHr6CfutBp0InSQtKXe52FIzLHaKXObS2LnvIM nWvRMq4HhG6zqQdY4sfxGJHJ31dkZUgSVxMW2yMejHhGENvttn/7pdaiiqvubrFyStRJK3+OEcFpMV stKm6BJpLUMogz21ysc7PNwmeqdFTiE0mI6ojBV5Gq8b/1rsFvD9L9T9qfNgCNDKtoWa5adCt5YTHe /3Pmva1VUIDOjHRRh4kfZi5bZPjcv3FZrG/AuogP0jux1bLPfg8FLnw2KVfEtZrMb+SjJYa3y/oYba kbqrXFMLJeiazu7xfDNoCkEc58zpXyWZXT2l2UB5ilAjGF+zMWQoo4Px5oZVxCsSo3w4ccC9A8LtB+ 0V9N6+2VgBCBU2zUhmOk9XGJomDJsx3sE2uErEJ0p5MhZZYOrP8Nz3r8QlHw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_003818_341392_4BF754BE X-CRM114-Status: GOOD ( 12.90 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible SoCs, they are used to feed the VPU LCD Pixel encoder used for DSI display purposes. Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 40 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 4 +++- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index d2e481ae2429..a132aad2aac9 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3547,6 +3547,22 @@ static struct clk_regmap g12a_cts_encp_sel = { }, }; +static struct clk_regmap g12a_cts_encl_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VIID_CLK_DIV, + .mask = 0xf, + .shift = 12, + .table = mux_table_cts_sel, + }, + .hw.init = &(struct clk_init_data){ + .name = "cts_encl_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = g12a_cts_parent_hws, + .num_parents = ARRAY_SIZE(g12a_cts_parent_hws), + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + }, +}; + static struct clk_regmap g12a_cts_vdac_sel = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_VIID_CLK_DIV, @@ -3626,6 +3642,22 @@ static struct clk_regmap g12a_cts_encp = { }, }; +static struct clk_regmap g12a_cts_encl = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VID_CLK_CNTL2, + .bit_idx = 3, + }, + .hw.init = &(struct clk_init_data) { + .name = "cts_encl", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_cts_encl_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, +}; + static struct clk_regmap g12a_cts_vdac = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VID_CLK_CNTL2, @@ -4406,10 +4438,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, + [CLKID_PRIV_CTS_ENCL] = &g12a_cts_encl.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, @@ -4635,10 +4669,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, + [CLKID_PRIV_CTS_ENCL] = &g12a_cts_encl.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, @@ -4899,10 +4935,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, + [CLKID_PRIV_CTS_ENCL] = &g12a_cts_encl.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, @@ -5133,10 +5171,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { &g12a_vclk2_div12_en, &g12a_cts_enci_sel, &g12a_cts_encp_sel, + &g12a_cts_encl_sel, &g12a_cts_vdac_sel, &g12a_hdmi_tx_sel, &g12a_cts_enci, &g12a_cts_encp, + &g12a_cts_encl, &g12a_cts_vdac, &g12a_hdmi_tx, &g12a_hdmi_sel, diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index a57f4a9717db..9a3091fcaa41 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -265,8 +265,10 @@ #define CLKID_PRIV_NNA_CORE_CLK_SEL 265 #define CLKID_PRIV_NNA_CORE_CLK_DIV 266 #define CLKID_PRIV_MIPI_DSI_PXCLK_DIV 268 +#define CLKID_PRIV_CTS_ENCL 271 +#define CLKID_PRIV_CTS_ENCL_SEL 272 -#define NR_CLKS 271 +#define NR_CLKS 273 /* include the CLKIDs that have been made part of the DT binding */ #include From patchwork Tue May 30 07:38:04 2023 Content-Type: text/plain; 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Tue, 30 May 2023 00:38:17 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id m4-20020a5d4a04000000b003079c402762sm2312013wrq.19.2023.05.30.00.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 00:38:16 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:04 +0200 Subject: [PATCH v5 03/17] dt-bindings: clk: g12a-clkc: add VCLK2_SEL and CTS_ENCL clock ids MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-3-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. 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X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add new CLK ids for the VCLK2_SEL, CTS_ENCL and CTS_ENCL_SEL clocks on G12A compatible SoCs. Signed-off-by: Neil Armstrong Acked-by: Conor Dooley --- include/dt-bindings/clock/g12a-clkc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index a93b58c5e18e..80421d7982dd 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -108,6 +108,7 @@ #define CLKID_VAPB 124 #define CLKID_HDMI_PLL 128 #define CLKID_VID_PLL 129 +#define CLKID_VCLK2_SEL 133 #define CLKID_VCLK 138 #define CLKID_VCLK2 139 #define CLKID_VCLK_DIV1 148 @@ -149,5 +150,7 @@ #define CLKID_NNA_CORE_CLK 267 #define CLKID_MIPI_DSI_PXCLK_SEL 269 #define CLKID_MIPI_DSI_PXCLK 270 +#define CLKID_CTS_ENCL 271 +#define CLKID_CTS_ENCL_SEL 272 #endif /* __G12A_CLKC_H */ From patchwork Tue May 30 07:38:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13259467 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73D09C7EE23 for ; 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Tue, 30 May 2023 00:38:17 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:05 +0200 Subject: [PATCH v5 04/17] clk: meson: g12: use VCLK2_SEL, CTS_ENCL & CTS_ENCL_SEL public CLK IDs MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-4-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4965; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=ykSwF0V0lUS+Xeggc75UkrBZ6e3mEPjzepbC0GhniEs=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafeS+RBYJ5gBUnorLdUmAymfM1ZVs6kR7L/wisf VI37kfGJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn3gAKCRB33NvayMhJ0T+CEA DGHyBfRCXIDqYZbNurPI1sb/Ze3ilqYZTVrrQuJjM90Tdl5a0o8b0qbWQ4kDxqEAAU/IEY99JNJfed fN2ZePLSSArZ3dWZ27Uz9sHdan8oAH6ato+VnQaXwv0Gr2sVJd0pkIOhITtBi9S/R4LLjuwi4t3n/d j5HDJAkYcOJdI7Dchkjdz48fItlAadx8zAsSwHVL/kKBE9wAQOGjeK1ew+fIyDCkNvQOTadJCi6NxA aV+cql+M0q6BDWHu4yicOdD2mFyMSpVKCToEI/FLBTD+ygyZvxe3eQuKD9SGVqnMC599JfvAAI0N1W oo9R9a2rBKGTakLKlQkvN2mZ2m+8Irmb+TzSa6KuKz7KdvfOt+yr5DKoI8P8xh0PxcafZupyoPe96J zYufDbbAKJ1HvsSWuPk5qiU1wcEmDl8aPbkq48H0J7VDdNgCUIKvpkj3OjW9Q00lhqlubi20bMLBHd DawwHZqV4+uT/DnKHLjjAJXDw3M0lbx8Q7bmDywDggDW9DVEo2WdK2PEFe4Dn4h+ffxePtd3kPt3NU NugxodI/LFlkkgSxrZ0PRvdcAa8mVl34uRbcF+ObjLhe/HiKKIBhKZax7QZsWqxLYX/KjGc940s/fL jLXmJXY5pD4LmSVneMDFo94J6M24fGigo/zZALq+zEpiX1hoqd4Pmbwr0KDQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_083821_509646_9C4ED13E X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Now those CLK IDs were added to the public bindings header, switch to use those defines and drop the PRIV defines. Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 18 +++++++++--------- drivers/clk/meson/g12a.h | 3 --- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index a132aad2aac9..461ebd79497c 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4411,7 +4411,7 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_PRIV_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, [CLKID_PRIV_VID_PLL_DIV] = &g12a_vid_pll.hw, [CLKID_PRIV_VCLK_SEL] = &g12a_vclk_sel.hw, - [CLKID_PRIV_VCLK2_SEL] = &g12a_vclk2_sel.hw, + [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, [CLKID_PRIV_VCLK_INPUT] = &g12a_vclk_input.hw, [CLKID_PRIV_VCLK2_INPUT] = &g12a_vclk2_input.hw, [CLKID_PRIV_VCLK_DIV] = &g12a_vclk_div.hw, @@ -4438,12 +4438,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, - [CLKID_PRIV_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, + [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, - [CLKID_PRIV_CTS_ENCL] = &g12a_cts_encl.hw, + [CLKID_CTS_ENCL] = &g12a_cts_encl.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, @@ -4642,7 +4642,7 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_PRIV_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, [CLKID_PRIV_VID_PLL_DIV] = &g12a_vid_pll.hw, [CLKID_PRIV_VCLK_SEL] = &g12a_vclk_sel.hw, - [CLKID_PRIV_VCLK2_SEL] = &g12a_vclk2_sel.hw, + [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, [CLKID_PRIV_VCLK_INPUT] = &g12a_vclk_input.hw, [CLKID_PRIV_VCLK2_INPUT] = &g12a_vclk2_input.hw, [CLKID_PRIV_VCLK_DIV] = &g12a_vclk_div.hw, @@ -4669,12 +4669,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, - [CLKID_PRIV_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, + [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, - [CLKID_PRIV_CTS_ENCL] = &g12a_cts_encl.hw, + [CLKID_CTS_ENCL] = &g12a_cts_encl.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, @@ -4908,7 +4908,7 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_PRIV_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, [CLKID_PRIV_VID_PLL_DIV] = &g12a_vid_pll.hw, [CLKID_PRIV_VCLK_SEL] = &g12a_vclk_sel.hw, - [CLKID_PRIV_VCLK2_SEL] = &g12a_vclk2_sel.hw, + [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, [CLKID_PRIV_VCLK_INPUT] = &g12a_vclk_input.hw, [CLKID_PRIV_VCLK2_INPUT] = &g12a_vclk2_input.hw, [CLKID_PRIV_VCLK_DIV] = &g12a_vclk_div.hw, @@ -4935,12 +4935,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, - [CLKID_PRIV_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, + [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, - [CLKID_PRIV_CTS_ENCL] = &g12a_cts_encl.hw, + [CLKID_CTS_ENCL] = &g12a_cts_encl.hw, [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] = &g12a_hdmi_sel.hw, diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 9a3091fcaa41..8275413f2beb 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -168,7 +168,6 @@ #define CLKID_PRIV_VID_PLL_SEL 130 #define CLKID_PRIV_VID_PLL_DIV 131 #define CLKID_PRIV_VCLK_SEL 132 -#define CLKID_PRIV_VCLK2_SEL 133 #define CLKID_PRIV_VCLK_INPUT 134 #define CLKID_PRIV_VCLK2_INPUT 135 #define CLKID_PRIV_VCLK_DIV 136 @@ -265,8 +264,6 @@ #define CLKID_PRIV_NNA_CORE_CLK_SEL 265 #define CLKID_PRIV_NNA_CORE_CLK_DIV 266 #define CLKID_PRIV_MIPI_DSI_PXCLK_DIV 268 -#define CLKID_PRIV_CTS_ENCL 271 -#define CLKID_PRIV_CTS_ENCL_SEL 272 #define NR_CLKS 273 From patchwork Tue May 30 07:38:06 2023 Content-Type: text/plain; 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Tue, 30 May 2023 00:38:19 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id m4-20020a5d4a04000000b003079c402762sm2312013wrq.19.2023.05.30.00.38.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 00:38:19 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:06 +0200 Subject: [PATCH v5 05/17] clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-5-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. 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The nocache option is removed from following clocks: - vclk2_sel - vclk2_input - vclk2_div - vclk2 - vclk_div1 - vclk2_div2_en - vclk2_div4_en - vclk2_div6_en - vclk2_div12_en - vclk2_div2 - vclk2_div4 - vclk2_div6 - vclk2_div12 - cts_encl_sel The missing vclk2 reset sequence is handled via new clkc notifiers in order to reset the vclk2 after each rate change as done by Amlogic in the vendor implementation. In order to set a rate on cts_encl via the vclk2 clock path, the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order to keep CCF from selection a parent. The parents of cts_encl_sel & vclk2_sel are expected to be defined in DT. The following clock scheme is to be used for DSI: xtal \_ gp0_pll_dco \_ gp0_pll |- vclk2_sel | \_ vclk2_input | \_ vclk2_div | \_ vclk2 | \_ vclk2_div1 | \_ cts_encl_sel | \_ cts_encl -> to VPU LCD Encoder |- mipi_dsi_pxclk_sel \_ mipi_dsi_pxclk_div \_ mipi_dsi_pxclk -> to DSI controller The mipi_dsi_pxclk_div is set as RO in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input. Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 131 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 120 insertions(+), 11 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 461ebd79497c..e4053f4957d5 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3163,7 +3163,7 @@ static struct clk_regmap g12a_vclk2_sel = { .ops = &clk_regmap_mux_ops, .parent_hws = g12a_vclk_parent_hws, .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws), - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + .flags = CLK_SET_RATE_NO_REPARENT, }, }; @@ -3191,7 +3191,6 @@ static struct clk_regmap g12a_vclk2_input = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, }, }; @@ -3212,6 +3211,40 @@ static struct clk_regmap g12a_vclk_div = { }, }; +struct g12a_vclk_div_notifier { + struct clk_regmap *clk; + unsigned int offset; + u8 en_bit_idx; + u8 reset_bit_idx; + struct notifier_block nb; +}; + +static int g12a_vclk_div_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct g12a_vclk_div_notifier *nb_data = + container_of(nb, struct g12a_vclk_div_notifier, nb); + + switch (event) { + case PRE_RATE_CHANGE: + /* disable and reset vclk2 divider */ + regmap_update_bits(nb_data->clk->map, nb_data->offset, + BIT(nb_data->en_bit_idx) | + BIT(nb_data->reset_bit_idx), + BIT(nb_data->reset_bit_idx)); + return NOTIFY_OK; + case POST_RATE_CHANGE: + /* enabled and release reset */ + regmap_update_bits(nb_data->clk->map, nb_data->offset, + BIT(nb_data->en_bit_idx) | + BIT(nb_data->reset_bit_idx), + BIT(nb_data->en_bit_idx)); + return NOTIFY_OK; + default: + return NOTIFY_DONE; + }; +}; + static struct clk_regmap g12a_vclk2_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_VIID_CLK_DIV, @@ -3225,10 +3258,18 @@ static struct clk_regmap g12a_vclk2_div = { &g12a_vclk2_input.hw }, .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, + .flags = CLK_DIVIDER_ROUND_CLOSEST, }, }; +static struct g12a_vclk_div_notifier g12a_vclk2_div_data = { + .clk = &g12a_vclk2_div, + .offset = HHI_VIID_CLK_DIV, + .en_bit_idx = 16, + .reset_bit_idx = 17, + .nb.notifier_call = g12a_vclk_div_notifier_cb, +}; + static struct clk_regmap g12a_vclk = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VID_CLK_CNTL, @@ -3243,6 +3284,33 @@ static struct clk_regmap g12a_vclk = { }, }; +struct g12a_vclk_reset_notifier { + struct clk_regmap *clk; + unsigned int offset; + u8 bit_idx; + struct notifier_block nb; +}; + +static int g12a_vclk_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct g12a_vclk_reset_notifier *nb_data = + container_of(nb, struct g12a_vclk_reset_notifier, nb); + + switch (event) { + case POST_RATE_CHANGE: + /* reset vclk2 */ + regmap_update_bits(nb_data->clk->map, nb_data->offset, + BIT(nb_data->bit_idx), BIT(nb_data->bit_idx)); + regmap_update_bits(nb_data->clk->map, nb_data->offset, + BIT(nb_data->bit_idx), 0); + + return NOTIFY_OK; + default: + return NOTIFY_DONE; + }; +} + static struct clk_regmap g12a_vclk2 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VIID_CLK_CNTL, @@ -3253,10 +3321,17 @@ static struct clk_regmap g12a_vclk2 = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT, }, }; +static struct g12a_vclk_reset_notifier g12a_vclk2_data = { + .clk = &g12a_vclk2, + .offset = HHI_VIID_CLK_CNTL, + .bit_idx = 15, + .nb.notifier_call = g12a_vclk_notifier_cb, +}; + static struct clk_regmap g12a_vclk_div1 = { .data = &(struct clk_regmap_gate_data){ .offset = HHI_VID_CLK_CNTL, @@ -3337,7 +3412,7 @@ static struct clk_regmap g12a_vclk2_div1 = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3351,7 +3426,7 @@ static struct clk_regmap g12a_vclk2_div2_en = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3365,7 +3440,7 @@ static struct clk_regmap g12a_vclk2_div4_en = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3379,7 +3454,7 @@ static struct clk_regmap g12a_vclk2_div6_en = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3393,7 +3468,7 @@ static struct clk_regmap g12a_vclk2_div12_en = { .ops = &clk_regmap_gate_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3459,6 +3534,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 = { &g12a_vclk2_div2_en.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3472,6 +3548,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 = { &g12a_vclk2_div4_en.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3485,6 +3562,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 = { &g12a_vclk2_div6_en.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3498,6 +3576,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 = { &g12a_vclk2_div12_en.hw }, .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3559,7 +3638,7 @@ static struct clk_regmap g12a_cts_encl_sel = { .ops = &clk_regmap_mux_ops, .parent_hws = g12a_cts_parent_hws, .num_parents = ARRAY_SIZE(g12a_cts_parent_hws), - .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + .flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, }, }; @@ -3727,7 +3806,7 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_div = { }, .hw.init = &(struct clk_init_data){ .name = "mipi_dsi_pxclk_div", - .ops = &clk_regmap_divider_ops, + .ops = &clk_regmap_divider_ro_ops, .parent_hws = (const struct clk_hw *[]) { &g12a_mipi_dsi_pxclk_sel.hw }, @@ -5421,6 +5500,32 @@ static int meson_g12a_dvfs_setup(struct platform_device *pdev) return 0; } +static int meson_g12a_vclk_setup(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk *notifier_clk; + int ret; + + /* Setup clock notifier for vclk2 */ + notifier_clk = devm_clk_hw_get_clk(dev, &g12a_vclk2.hw, DVFS_CON_ID); + ret = devm_clk_notifier_register(dev, notifier_clk, &g12a_vclk2_data.nb); + if (ret) { + dev_err(dev, "failed to register the vlkc2 notifier\n"); + return ret; + } + + /* Setup clock notifier for vclk2_div */ + notifier_clk = devm_clk_hw_get_clk(dev, &g12a_vclk2_div.hw, DVFS_CON_ID); + ret = devm_clk_notifier_register(dev, notifier_clk, + &g12a_vclk2_div_data.nb); + if (ret) { + dev_err(dev, "failed to register the vclk2_div notifier\n"); + return ret; + } + + return 0; +} + struct meson_g12a_data { const struct meson_eeclkc_data eeclkc_data; int (*dvfs_setup)(struct platform_device *pdev); @@ -5443,6 +5548,10 @@ static int meson_g12a_probe(struct platform_device *pdev) g12a_data = container_of(eeclkc_data, struct meson_g12a_data, eeclkc_data); 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Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3536; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=DcR1nE4ZMJpkpX2oEe3RQlDvB5okZPNaS9Js/yOJnic=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdaffq+G+cxVoOQbtSrl/SEHGE6MG1300kjLhFz94 et6gskiJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn3wAKCRB33NvayMhJ0d9GEA CkuB537HbJHqDkt4SUmKi6+cTkKmuRCZVQl4HXF66H6GNlELIUpDxzLFYKRZ57RzQ7eisjoen0kd67 oIKnVvJZRpmJHPRlvzo+Zq8POWmuEjskvDVNwF5LOcYu1O2U6EN6Dk/VhSKJMPkRmy5m8z4H0REPdb 6BSj6AgKzG0CQIiGnQs2NcSY0lUwbfMntYbpe3CKDvmMVPjY2CTI+4Vydg9lo+/x0AFH22pP1s5fTp 6yq4XEPsF6l7Zy1ooGJt0LGuvPA1WN+dNBmzXYixyNI1ykkQQ2nxmtyngiHRUdauQe/KSN7FRJ6mWR aO7CLt6djQM0Fy5eOwefV9ES0Fl5W6xv/htXVF7UCTqxs5Yl6n2abXMeA2bEAleR2016wMgbKEpdK0 8GrtW4fL2lrXZR6dPvTtaYsLRIhwwLccVan5v64qXCiQdeq2WhQRhiyrhwAY832KRIF/NkJooskNfy IVAF+/HV3P7TrFFHCo2FzIilgfPfEfQNhL7wBeoZMH8MYV5JGi/xRVBUMs+C8rfYPAuWXUlz4U7n3B 5mK9qt2JiOR31nFMGW65MlRQDyZm4F9Cu346AzoDHWQ2mndld0G6q4NmfoU0nva/+8P1sasel2Eu3M PpDTuHBNwKCwTgqyQ1s3vC6hBIM20FKFUAIubZt5cde3q0ZVgNRAZvXUkyTw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_083828_717237_40A386BB X-CRM114-Status: GOOD ( 12.93 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a) with a custom glue managing the IP resets, clock and data inputs similar to the DW-HDMI Glue on the same Amlogic SoC families. Signed-off-by: Neil Armstrong Signed-off-by: Neil Armstrong Reviewed-by: Conor Dooley --- .../display/amlogic,meson-g12a-dw-mipi-dsi.yaml | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml new file mode 100644 index 000000000000..a3428f012005 --- /dev/null +++ b/Documentation/devicetree/bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 BayLibre, SAS +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller + +maintainers: + - Neil Armstrong + +description: | + The Amlogic Meson Synopsys Designware Integration is composed of + - A Synopsys DesignWare MIPI DSI Host Controller IP + - A TOP control block controlling the Clocks & Resets of the IP + +allOf: + - $ref: dsi-controller.yaml# + +properties: + compatible: + enum: + - amlogic,meson-g12a-dw-mipi-dsi + + reg: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 4 + + clock-names: + minItems: 3 + items: + - const: pclk + - const: bit + - const: px + - const: meas + + resets: + maxItems: 1 + + reset-names: + items: + - const: top + + phys: + maxItems: 1 + + phy-names: + items: + - const: dphy + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input node to receive pixel data. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DSI output node to panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - phys + - phy-names + - ports + +unevaluatedProperties: false + +examples: + - | + dsi@6000 { + compatible = "amlogic,meson-g12a-dw-mipi-dsi"; + reg = <0x6000 0x400>; + resets = <&reset_top>; + reset-names = "top"; + clocks = <&clk_pclk>, <&bit_clk>, <&clk_px>; + clock-names = "pclk", "bit", "px"; + phys = <&mipi_dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VPU VENC Input */ + mipi_dsi_venc_port: port@0 { + reg = <0>; + + mipi_dsi_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + /* DSI Output */ + mipi_dsi_panel_port: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + }; From patchwork Tue May 30 07:38:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13259463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 418E4C7EE23 for ; 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Tue, 30 May 2023 00:38:21 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:08 +0200 Subject: [PATCH v5 07/17] dt-bindings: display: meson-vpu: add third DPI output port MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-7-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong , Rob Herring , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1111; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=ngaRaj/ff6scDRZWhYNPrhhh/3jRLEZndlPLfgP8m5M=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafgrQ+d6kVlnqgthYceWHgXDRj4X3G8yCwWhqxC zPMd+56JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn4AAKCRB33NvayMhJ0eT3EA CaIP+cIiapaagNPLfNF2mzXan492id42Vf+UOmKe5aW23Bk7xsIVga2C3eORTyR87dGU0msoFj0M0o PspPAeNAg7DXsMG3N0tpN3pQU9joVnYJobwujt7fMlBo9h2LqkjTlvD1BrWSnOtkn92Amoj9lROpbd 296eS7FzQBOybBtYOICBCbI5Me8Epuh84+WZy9pqHaj44YiDeH9U4UsdteRPYutqED/1oGKZ0z6Eet Y6VNtS14EwxYbcB/hIoF07ReQFwqaSkuJOZFVVCVmABEfKsP7Civ8Kr5jWI70sI6eq9Uqn+aOEqUDT z2nnSHtmrzR6pIp1cWb9YbDB6YXQ1HUTx/PyXxp+M4Lj9Gw3laPdn0qRQ785bQSUSqFZgTXge26B0q xZVu4MnknfHXLTdZ1v2tPtErmaTrvGa9G0vadKqvqHbD0oqrSGHIlsg6zkw3c0GC8lzaFKdO6ZQ68D fm3GGGGjDrUvhgOdaMo4clJxq0mhDdRadCdwdWAJm1KikDaVwKShkRU87r5uu/kXur/uyQD/B5JLtU JGE2aZD4cvNjIywneK6eobQpnxStvcZs6mI3WOUwjNtYFqXnNKefvE9oP4lxjqMak0Mux0gf8vXtRL xJgFplqz2XADbImv2izEtL/ZAHgG1BZhNGjXQCZT1aImRaz9rH3OUOnzwSrg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_083827_747178_EBE4D5FC X-CRM114-Status: UNSURE ( 8.73 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Add third port corresponding to the ENCL DPI encoder used to connect to DSI or LVDS transceivers. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml index 0c72120acc4f..cb0a90f02321 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml @@ -96,6 +96,11 @@ properties: description: A port node pointing to the HDMI-TX port node. + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + A port node pointing to the DPI port node (e.g. DSI or LVDS transceiver). + "#address-cells": const: 1 From patchwork Tue May 30 07:38:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13259462 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2C9FC77B73 for ; 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Tue, 30 May 2023 00:38:22 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:09 +0200 Subject: [PATCH v5 08/17] drm/meson: fix unbind path if HDMI fails to bind MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-8-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2139; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=8CpWFO/23ohWXtlw9VlUvRSsoZjkvEPG4DEcAI5MYHo=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafgS67it5Xd/IPSiDYVRkKBdEU3k4dSZcRJg6IY IKzsY56JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn4AAKCRB33NvayMhJ0VUhEA DBaG9ujzD1I8t4CF/PcaEnEZkX3oRDTeUQ2mqXuf8uqKMsWiwUq4ejxXcT3M9558+/alirvGZSMGJR je5yXs+uY81A+lDAN/Kfki1r5nLbnqchdCedEoVmGvFwsnzV/kgppLF9dnxOflfOb2BS3BccuktlSL I6v0HTTCGbUJaDDms7NEHyl55fK0+CB7BCXNf68MpylOUs548WCOy8fl2QcPeR05x1BRjOIDHQT66Q XY0Kh1vJYWOe7xhxE1oCFrJqYdv0s+w9WIIF5QjNd54oUF1/jCVL26uYwy6QniOrq+quZU4vav2B8A 9x3xioYs6uEAbKQo8WCDtg/7xMRg+6436OB/XKOSITB/1bCelI1aAYCOhaJ2uf4uGhESocQtsgfS+y 1Sz6eUxltr2DVz6vtzP5PIjalX4CvEzPEbBZdRdnLWpoxVCbI5PJIUtLDNSTEwxsNMm2I4jM5VcjmD gdhMqkdV2yk/e7tSqEafcitTrOsrcQoFgbWgwDLYvTTUCIsmpat11MkLYGrODn/SjzfM0m2yYz9dc4 PyUwkUPBoyGcjqdSadGHYXLggtZQ/8WOTu9EUQPxzU3Tv8nQdfdkbWp4JsglxXP+A2HOxZYYFzib8i Kp0vzZvGcm36bLWM3Btf2WRSkwVaM/nsMwg2nO/4Uq5h5NhDaL067x7/sKOQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_083829_790616_35733CFC X-CRM114-Status: GOOD ( 11.64 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org If the case the HDMI controller fails to bind, we try to unbind all components before calling drm_dev_put() which makes drm_bridge_detach() crash because unbinding the HDMI controller frees the bridge memory. The solution is the unbind all components at the end like in the remove path. Signed-off-by: Neil Armstrong Reviewed-by: Nicolas Belin Tested-by: Nicolas Belin --- drivers/gpu/drm/meson/meson_drv.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index ca6d1e59e5d9..e060279dc80a 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -316,32 +316,34 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) goto exit_afbcd; if (has_components) { - ret = component_bind_all(drm->dev, drm); + ret = component_bind_all(dev, drm); if (ret) { dev_err(drm->dev, "Couldn't bind all components\n"); + /* Do not try to unbind */ + has_components = false; goto exit_afbcd; } } ret = meson_encoder_hdmi_init(priv); if (ret) - goto unbind_all; + goto exit_afbcd; ret = meson_plane_create(priv); if (ret) - goto unbind_all; + goto exit_afbcd; ret = meson_overlay_create(priv); if (ret) - goto unbind_all; + goto exit_afbcd; ret = meson_crtc_create(priv); if (ret) - goto unbind_all; + goto exit_afbcd; ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm); if (ret) - goto unbind_all; + goto exit_afbcd; drm_mode_config_reset(drm); @@ -359,15 +361,18 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) uninstall_irq: free_irq(priv->vsync_irq, drm); -unbind_all: - if (has_components) - component_unbind_all(drm->dev, drm); exit_afbcd: if (priv->afbcd.ops) priv->afbcd.ops->exit(priv); free_drm: drm_dev_put(drm); + meson_encoder_hdmi_remove(priv); + meson_encoder_cvbs_remove(priv); + + if (has_components) + component_unbind_all(dev, drm); + return ret; } From patchwork Tue May 30 07:38:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13259466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC7C2C7EE23 for ; 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Tue, 30 May 2023 00:38:23 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:10 +0200 Subject: [PATCH v5 09/17] drm/meson: only use components with dw-hdmi MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-9-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2777; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=nVXfezvQbKE5gC4JrB0CVduxieCr6UkdveYDXaG+sjI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafgB8ChwHhm0E9pEZfTkphqOUzLZTgFYnPzxmOG /S4wCUKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn4AAKCRB33NvayMhJ0UkyD/ 4nse+EzB7hATP8CQAMK3zfVTtmlq8CoWG5Fcwju9bfQsCYBVPvp9Zysjg6wxBX+W13gkaO96AOb2J7 foQf4doFXgEZJzBRjoX21BePaAK5dtyqI27XYUWL8zvYWQfZ/kDfhezwKt6FBKyalaeNCMgTwsvnbe 60ycoHMPi4z56Gc08oDa4f5DcqQ6eWkAXe+SVypHwmoti6uEyl3icc6ca0D8APd+s/Jg4sHopL/Xr3 JiiGulF3tQXV6hF88aWtgMKQyLpKhbBu2Qcm1mhi+G5rnkdFFxB9spFkTYLuMsn6O/+EZjdC+qhCAI rP6BhyvoAYUB+MHEvTbjIja5e9v7x874k5tXcxQ+CpCmIdrJxTAuNQgur1E0DZOMMisqTmeap/vHyZ AH09CltXd1ZrSl5qlliTw0vrwplJb6cDK8L/nQka5f868acWitvPVcpUKeA32xF8X6WA7iQWBHBRO4 EMpnhPZH0+2/2rZZcOqqBgRWs4jL6/D4rXpZzkQZ+Q0l7k5VbNt8tjVG3v3giWr369aRlQNZs9SePj vM68t+3W47ka0W7g5jJ3cFXafmjJme1FwBjc9PXiSEeYAjSaDVCE6iNfyQmLtruHqFev5ITlubRTBm yIquMb+6j1mJXzhswTrD205PsdVr1BDSFRBvv4WUcoKNU8XCUv7Pfe1GWIUA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_083839_544131_5C256B9F X-CRM114-Status: GOOD ( 13.44 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Only DW-HDMI currently needs components since it reuses the drm-meson driver context to access HHI registers (sic). Once this is solved, we can get rid on components. Until now, limit the components matching to the dw-hdmi compatibles we know to require this hack, for other bridges simply use probe defer instead and get over this components sitation. The back story is that we simply cannot attach DSI adapters bridges if we use components, only DSI panels, this is because we bind/unbind the DSI controller at each drm-meson driver master bind tentative. With this the I2C DSI bridge is unable to find the DSI controller host and everything fails to probe. This will simplify a lot adding new or older HDMI bridges. Cc: Martin Blumenstingl Signed-off-by: Neil Armstrong Reviewed-by: Nicolas Belin Tested-by: Nicolas Belin # on Khadas VIM3 + TS050 Panel --- drivers/gpu/drm/meson/meson_drv.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index e060279dc80a..e935c0286a20 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -451,10 +451,17 @@ static void meson_drv_shutdown(struct platform_device *pdev) drm_atomic_helper_shutdown(priv->drm); } -/* Possible connectors nodes to ignore */ -static const struct of_device_id connectors_match[] = { - { .compatible = "composite-video-connector" }, - { .compatible = "svideo-connector" }, +/* + * Only devices to use as components + * TOFIX: get rid of components when we can finally + * get meson_dx_hdmi to stop using the meson_drm + * private structure for HHI registers. + */ +static const struct of_device_id components_dev_match[] = { + { .compatible = "amlogic,meson-gxbb-dw-hdmi" }, + { .compatible = "amlogic,meson-gxl-dw-hdmi" }, + { .compatible = "amlogic,meson-gxm-dw-hdmi" }, + { .compatible = "amlogic,meson-g12a-dw-hdmi" }, {} }; @@ -472,17 +479,12 @@ static int meson_drv_probe(struct platform_device *pdev) continue; } - /* If an analog connector is detected, count it as an output */ - if (of_match_node(connectors_match, remote)) { - ++count; - of_node_put(remote); - continue; - } - - dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n", - np, remote, dev_name(&pdev->dev)); + if (of_match_node(components_dev_match, remote)) { + component_match_add(&pdev->dev, &match, component_compare_of, remote); - component_match_add(&pdev->dev, &match, component_compare_of, remote); + dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n", + np, remote, dev_name(&pdev->dev)); + } of_node_put(remote); From patchwork Tue May 30 07:38:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13259383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23584C7EE23 for ; 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Tue, 30 May 2023 00:38:24 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:11 +0200 Subject: [PATCH v5 10/17] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-10-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15394; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=PLav+7Gd57z4CzaoRTYbs8F3lsWO01D4ELXIlOs+1aE=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafhYlIyfhrjnMjMpZGXz3V2LZQnR2nSCRorITPd AuxwZA6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn4QAKCRB33NvayMhJ0T0zEA CPEYFd0yzsl8U3HWRKcyhZ0gfjdAzW0Ql/S0oyzNAvHJXEKLhw4IYJsdekOmGbQ7nrGRfoFblqs3WB 5fVibgnFKDs4c8KdDhNXlqr/Wz52kDVzMim95D7uYhYiHlfLM3QpjAsXUKl9w4q5aRACSwQF9EzH7V qJRFz1E7d/eyLAWlexMAKy9NAMTnXfVNZwAMzhQSnJsFKrMQygmIQo+n9gUoxtwgJVbIiFl/hTG7lR UvOBbJbhSTvc0Nl7FSImuge7nWGJk++cPnoUbn7cH5pVgUz1ZgfJpeQ8PCmaHemTOfyOkUfAL9cS3d XYq202YtwB3oHqyX1LOeJ9F3ts8Hg0bd99V4y/S0PqtSuzqqAct3gCgIGEFGSgjYw2lVSQsH7TkZ8Z 72BOTifejZg/ne/KWtXrGw7VCjw2UCrx6UQ7jZHhZxNKN7NEYGs8KOLnYOWupmbIu1Zm+PrW3FhVVr g7BF3V3SgmfIGbUqOiiQIGJDKn9YOHU3IxEGagejbLSkfYOl6n0J9XWcfEjWp3k/Bnw0HozuQwj8dW mG79erm1b0FBKm64I6ZmOACeKv2vvS/H2E6ANgEoplk7DU87armEFN90r1U1dJa7xZoFKkX0G5hiCP PAPYvcueKytxS1ZwO03s21248MU5atm7TzJzhG9WwzQQlIPBiQaQUnM1dbsg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_083827_929429_59DE2E43 X-CRM114-Status: GOOD ( 15.67 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This adds supports for the ENCL encoder connected to a MIPI-DSI transceiver on the Amlogic AXG, G12A, G12B & SM1 SoCs. Signed-off-by: Neil Armstrong Signed-off-by: Neil Armstrong Reviewed-by: Nicolas Belin Tested-by: Nicolas Belin # on Khadas VIM3 + TS050 Panel --- drivers/gpu/drm/meson/meson_registers.h | 25 ++++ drivers/gpu/drm/meson/meson_venc.c | 211 +++++++++++++++++++++++++++++++- drivers/gpu/drm/meson/meson_venc.h | 6 + drivers/gpu/drm/meson/meson_vpp.h | 2 + 4 files changed, 242 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h index 0f3cafab8860..3d73d00a1f4c 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -812,6 +812,7 @@ #define VENC_STATA 0x1b6d #define VENC_INTCTRL 0x1b6e #define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1) +#define VENC_INTCTRL_ENCP_LNRST_INT_EN BIT(9) #define VENC_INTFLAG 0x1b6f #define VENC_VIDEO_TST_EN 0x1b70 #define VENC_VIDEO_TST_MDSEL 0x1b71 @@ -1192,7 +1193,11 @@ #define ENCL_VIDEO_PB_OFFST 0x1ca5 #define ENCL_VIDEO_PR_OFFST 0x1ca6 #define ENCL_VIDEO_MODE 0x1ca7 +#define ENCL_PX_LN_CNT_SHADOW_EN BIT(15) #define ENCL_VIDEO_MODE_ADV 0x1ca8 +#define ENCL_VIDEO_MODE_ADV_VFIFO_EN BIT(3) +#define ENCL_VIDEO_MODE_ADV_GAIN_HDTV BIT(4) +#define ENCL_SEL_GAMMA_RGB_IN BIT(10) #define ENCL_DBG_PX_RST 0x1ca9 #define ENCL_DBG_LN_RST 0x1caa #define ENCL_DBG_PX_INT 0x1cab @@ -1219,11 +1224,14 @@ #define ENCL_VIDEO_VOFFST 0x1cc0 #define ENCL_VIDEO_RGB_CTRL 0x1cc1 #define ENCL_VIDEO_FILT_CTRL 0x1cc2 +#define ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER BIT(12) #define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 #define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 #define ENCL_VIDEO_MATRIX_CB 0x1cc5 #define ENCL_VIDEO_MATRIX_CR 0x1cc6 #define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 +#define ENCL_VIDEO_RGBIN_RGB BIT(0) +#define ENCL_VIDEO_RGBIN_ZBLK BIT(1) #define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 #define ENCL_DACSEL_0 0x1cc9 #define ENCL_DACSEL_1 0x1cca @@ -1300,13 +1308,28 @@ #define RDMA_STATUS2 0x1116 #define RDMA_STATUS3 0x1117 #define L_GAMMA_CNTL_PORT 0x1400 +#define L_GAMMA_CNTL_PORT_VCOM_POL BIT(7) /* RW */ +#define L_GAMMA_CNTL_PORT_RVS_OUT BIT(6) /* RW */ +#define L_GAMMA_CNTL_PORT_ADR_RDY BIT(5) /* Read Only */ +#define L_GAMMA_CNTL_PORT_WR_RDY BIT(4) /* Read Only */ +#define L_GAMMA_CNTL_PORT_RD_RDY BIT(3) /* Read Only */ +#define L_GAMMA_CNTL_PORT_TR BIT(2) /* RW */ +#define L_GAMMA_CNTL_PORT_SET BIT(1) /* RW */ +#define L_GAMMA_CNTL_PORT_EN BIT(0) /* RW */ #define L_GAMMA_DATA_PORT 0x1401 #define L_GAMMA_ADDR_PORT 0x1402 +#define L_GAMMA_ADDR_PORT_RD BIT(12) +#define L_GAMMA_ADDR_PORT_AUTO_INC BIT(11) +#define L_GAMMA_ADDR_PORT_SEL_R BIT(10) +#define L_GAMMA_ADDR_PORT_SEL_G BIT(9) +#define L_GAMMA_ADDR_PORT_SEL_B BIT(8) +#define L_GAMMA_ADDR_PORT_ADDR GENMASK(7, 0) #define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 #define L_RGB_BASE_ADDR 0x1405 #define L_RGB_COEFF_ADDR 0x1406 #define L_POL_CNTL_ADDR 0x1407 #define L_DITH_CNTL_ADDR 0x1408 +#define L_DITH_CNTL_DITH10_EN BIT(10) #define L_GAMMA_PROBE_CTRL 0x1409 #define L_GAMMA_PROBE_COLOR_L 0x140a #define L_GAMMA_PROBE_COLOR_H 0x140b @@ -1363,6 +1386,8 @@ #define L_LCD_PWM1_HI_ADDR 0x143f #define L_INV_CNT_ADDR 0x1440 #define L_TCON_MISC_SEL_ADDR 0x1441 +#define L_TCON_MISC_SEL_STV1 BIT(4) +#define L_TCON_MISC_SEL_STV2 BIT(5) #define L_DUAL_PORT_CNTL_ADDR 0x1442 #define MLVDS_CLK_CTL1_HI 0x1443 #define MLVDS_CLK_CTL1_LO 0x1444 diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c index 27ef9f88e4ff..2bdc2855e249 100644 --- a/drivers/gpu/drm/meson/meson_venc.c +++ b/drivers/gpu/drm/meson/meson_venc.c @@ -6,6 +6,7 @@ */ #include +#include #include @@ -1557,6 +1558,205 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, } EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set); +static unsigned short meson_encl_gamma_table[256] = { + 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, + 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, + 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, + 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, + 256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316, + 320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380, + 384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, 444, + 448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504, 508, + 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572, + 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636, + 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700, + 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764, + 768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824, 828, + 832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888, 892, + 896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952, 956, + 960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020, +}; + +static void meson_encl_set_gamma_table(struct meson_drm *priv, u16 *data, + u32 rgb_mask) +{ + int i, ret; + u32 reg; + + writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, 0, + priv->io_base + _REG(L_GAMMA_CNTL_PORT)); + + ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT), + reg, reg & L_GAMMA_CNTL_PORT_ADR_RDY, 10, 10000); + if (ret) + pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__); + + writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask | + FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0), + priv->io_base + _REG(L_GAMMA_ADDR_PORT)); + + for (i = 0; i < 256; i++) { + ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT), + reg, reg & L_GAMMA_CNTL_PORT_WR_RDY, + 10, 10000); + if (ret) + pr_warn_once("%s: GAMMA WR_RDY timeout\n", __func__); + + writel_relaxed(data[i], priv->io_base + _REG(L_GAMMA_DATA_PORT)); + } + + ret = readl_relaxed_poll_timeout(priv->io_base + _REG(L_GAMMA_CNTL_PORT), + reg, reg & L_GAMMA_CNTL_PORT_ADR_RDY, 10, 10000); + if (ret) + pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__); + + writel_relaxed(L_GAMMA_ADDR_PORT_AUTO_INC | rgb_mask | + FIELD_PREP(L_GAMMA_ADDR_PORT_ADDR, 0x23), + priv->io_base + _REG(L_GAMMA_ADDR_PORT)); +} + +void meson_encl_load_gamma(struct meson_drm *priv) +{ + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_R); + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_G); + meson_encl_set_gamma_table(priv, meson_encl_gamma_table, L_GAMMA_ADDR_PORT_SEL_B); + + writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, L_GAMMA_CNTL_PORT_EN, + priv->io_base + _REG(L_GAMMA_CNTL_PORT)); +} + +void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, + const struct drm_display_mode *mode) +{ + unsigned int max_pxcnt; + unsigned int max_lncnt; + unsigned int havon_begin; + unsigned int havon_end; + unsigned int vavon_bline; + unsigned int vavon_eline; + unsigned int hso_begin; + unsigned int hso_end; + unsigned int vso_begin; + unsigned int vso_end; + unsigned int vso_bline; + unsigned int vso_eline; + + max_pxcnt = mode->htotal - 1; + max_lncnt = mode->vtotal - 1; + havon_begin = mode->htotal - mode->hsync_start; + havon_end = havon_begin + mode->hdisplay - 1; + vavon_bline = mode->vtotal - mode->vsync_start; + vavon_eline = vavon_bline + mode->vdisplay - 1; + hso_begin = 0; + hso_end = mode->hsync_end - mode->hsync_start; + vso_begin = 0; + vso_end = 0; + vso_bline = 0; + vso_eline = mode->vsync_end - mode->vsync_start; + + meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCL); + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_relaxed(ENCL_PX_LN_CNT_SHADOW_EN, priv->io_base + _REG(ENCL_VIDEO_MODE)); + writel_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN | + ENCL_VIDEO_MODE_ADV_GAIN_HDTV | + ENCL_SEL_GAMMA_RGB_IN, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + + writel_relaxed(ENCL_VIDEO_FILT_CTRL_BYPASS_FILTER, + priv->io_base + _REG(ENCL_VIDEO_FILT_CTRL)); + writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT)); + writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT)); + writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN)); + writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END)); + writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE)); + writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE)); + + writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN)); + writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END)); + writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN)); + writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END)); + writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE)); + writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE)); + writel_relaxed(ENCL_VIDEO_RGBIN_RGB | ENCL_VIDEO_RGBIN_ZBLK, + priv->io_base + _REG(ENCL_VIDEO_RGBIN_CTRL)); + + /* default black pattern */ + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR)); + writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN)); + writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, 0, + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR)); + writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR)); /* Magic value */ + + writel_relaxed(L_DITH_CNTL_DITH10_EN, priv->io_base + _REG(L_DITH_CNTL_ADDR)); + + /* DE signal for TTL */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR)); + + /* DE signal for TTL */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR)); + + /* Hsync signal for TTL */ + if (mode->flags & DRM_MODE_FLAG_PHSYNC) { + writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR)); + writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR)); + } else { + writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR)); + writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR)); + } + writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR)); + writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR)); + + /* Vsync signal for TTL */ + writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR)); + writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR)); + if (mode->flags & DRM_MODE_FLAG_PVSYNC) { + writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR)); + writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR)); + } else { + writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR)); + writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR)); + } + + /* DE signal */ + writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR)); + writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR)); + writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR)); + writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR)); + + /* Hsync signal */ + writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR)); + writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR)); + writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR)); + writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR)); + + /* Vsync signal */ + writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR)); + writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR)); + writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR)); + writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR)); + + writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR)); + writel_relaxed(L_TCON_MISC_SEL_STV1 | L_TCON_MISC_SEL_STV2, + priv->io_base + _REG(L_TCON_MISC_SEL_ADDR)); + + priv->venc.current_mode = MESON_VENC_MODE_MIPI_DSI; +} +EXPORT_SYMBOL_GPL(meson_venc_mipi_dsi_mode_set); + void meson_venci_cvbs_mode_set(struct meson_drm *priv, struct meson_cvbs_enci_mode *mode) { @@ -1747,8 +1947,15 @@ unsigned int meson_venci_get_field(struct meson_drm *priv) void meson_venc_enable_vsync(struct meson_drm *priv) { - writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, - priv->io_base + _REG(VENC_INTCTRL)); + switch (priv->venc.current_mode) { + case MESON_VENC_MODE_MIPI_DSI: + writel_relaxed(VENC_INTCTRL_ENCP_LNRST_INT_EN, + priv->io_base + _REG(VENC_INTCTRL)); + break; + default: + writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, + priv->io_base + _REG(VENC_INTCTRL)); + } regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); } diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h index 9138255ffc9e..0f59adb1c6db 100644 --- a/drivers/gpu/drm/meson/meson_venc.h +++ b/drivers/gpu/drm/meson/meson_venc.h @@ -21,6 +21,7 @@ enum { MESON_VENC_MODE_CVBS_PAL, MESON_VENC_MODE_CVBS_NTSC, MESON_VENC_MODE_HDMI, + MESON_VENC_MODE_MIPI_DSI, }; struct meson_cvbs_enci_mode { @@ -47,6 +48,9 @@ struct meson_cvbs_enci_mode { unsigned int analog_sync_adj; }; +/* LCD Encoder gamma setup */ +void meson_encl_load_gamma(struct meson_drm *priv); + /* HDMI Clock parameters */ enum drm_mode_status meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode); @@ -63,6 +67,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, unsigned int ycrcb_map, bool yuv420_mode, const struct drm_display_mode *mode); +void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv, + const struct drm_display_mode *mode); unsigned int meson_venci_get_field(struct meson_drm *priv); void meson_venc_enable_vsync(struct meson_drm *priv); diff --git a/drivers/gpu/drm/meson/meson_vpp.h b/drivers/gpu/drm/meson/meson_vpp.h index afc9553ed8d3..b790042a1650 100644 --- a/drivers/gpu/drm/meson/meson_vpp.h +++ b/drivers/gpu/drm/meson/meson_vpp.h @@ -12,6 +12,8 @@ struct drm_rect; struct meson_drm; +/* Mux VIU/VPP to ENCL */ +#define MESON_VIU_VPP_MUX_ENCL 0x0 /* Mux VIU/VPP to ENCI */ #define MESON_VIU_VPP_MUX_ENCI 0x5 /* Mux VIU/VPP to ENCP */ From patchwork Tue May 30 07:38:12 2023 Content-Type: text/plain; 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Tue, 30 May 2023 00:38:26 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id m4-20020a5d4a04000000b003079c402762sm2312013wrq.19.2023.05.30.00.38.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 00:38:26 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:12 +0200 Subject: [PATCH v5 11/17] drm/meson: add DSI encoder MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-11-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong , Jagan Teki , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9381; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=CRG+a62gljx1JJalXPQmGyJpYRgdP01x+Wart/fUwko=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafhlxYYfr8IFFJUzCs+6LdwBR/WBt6YLg2sWYwT KUjgDMqJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn4QAKCRB33NvayMhJ0YfFD/ 0fdaBJI+6lBQGtNeDmSSDC8j5iBqsvkRmNYxSKOUwy7OTpNPCWLVQyy1/jXchX87k9j+NvSUoO8fpX DZAOzKBr1xenUtfwXeakF4q8IzNSji4LhhKM79jNzxgFsHDs+NIYh1P9md/PpU7VStjcER7wk311pM 7hNa8VGkSkzlaR9Jmq81CHaubH9xQ4VVF6sKVLUwBQDJWLhq006r08GtuiA56Dqc8Tp5gM4jjWfFWv cLSOySKc7UVS27IGh61jb24kzIYOrl5XM3uhXJHyUiqMxxqva0tuxaZqQB2qVUjRHkUVi9fvX8EG1X RED0AjrcFoknRq6NDWeBNUDtTKbsY4am0IwKv+df31mOj0wGFaCqA1BmbGLebS42hUSfJicYkKG41L m+AWSUuntLe0OsAcr6WmyJZGp3HN4HjBJAWff2vdzVKmFx3svTiywry8/zTWg79b8ZkZR3VpXHPvT4 sO05QcZvWY4nGUjYPZHi93gGE7ouS9Hwca5uYuQdvd9Nl/v88K8HiVkcxAyQxX0i/phXNk3Da8GJvo KIyU6OIzzhC0rkP27EX/j1SdhNHd+fBQmB7bsLMSQQW6iRZYPKvhKTtoVMLMFslNJaAbllJ/phPIlf BJXy+kvsF0NY4Bz96m6eyuCP/Ki22RdBNxZCgCIeOddIL22PA1L22mifaUVQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_083844_536525_64A875F1 X-CRM114-Status: GOOD ( 21.59 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org This adds an encoder bridge designed to drive a MIPI-DSI display by using the ENCL encoder through the internal MIPI DSI transceiver connected to the output of the ENCL pixel encoder. Signed-off-by: Neil Armstrong Reviewed-by: Jagan Teki Signed-off-by: Neil Armstrong Reviewed-by: Nicolas Belin Tested-by: Nicolas Belin # on Khadas VIM3 + TS050 Panel --- drivers/gpu/drm/meson/Makefile | 2 +- drivers/gpu/drm/meson/meson_drv.c | 9 ++ drivers/gpu/drm/meson/meson_drv.h | 1 + drivers/gpu/drm/meson/meson_encoder_dsi.c | 174 ++++++++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_encoder_dsi.h | 13 +++ 5 files changed, 198 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index 3afa31bdc950..833e18c20603 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -2,7 +2,7 @@ meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_encoder_cvbs.o meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_overlay.o meson-drm-y += meson_rdma.o meson_osd_afbcd.o -meson-drm-y += meson_encoder_hdmi.o +meson-drm-y += meson_encoder_hdmi.o meson_encoder_dsi.o obj-$(CONFIG_DRM_MESON) += meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index e935c0286a20..747b639ea0c4 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -34,6 +34,7 @@ #include "meson_registers.h" #include "meson_encoder_cvbs.h" #include "meson_encoder_hdmi.h" +#include "meson_encoder_dsi.h" #include "meson_viu.h" #include "meson_vpp.h" #include "meson_rdma.h" @@ -329,6 +330,12 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) if (ret) goto exit_afbcd; + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + ret = meson_encoder_dsi_init(priv); + if (ret) + goto exit_afbcd; + } + ret = meson_plane_create(priv); if (ret) goto exit_afbcd; @@ -367,6 +374,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) free_drm: drm_dev_put(drm); + meson_encoder_dsi_remove(priv); meson_encoder_hdmi_remove(priv); meson_encoder_cvbs_remove(priv); @@ -399,6 +407,7 @@ static void meson_drv_unbind(struct device *dev) free_irq(priv->vsync_irq, drm); drm_dev_put(drm); + meson_encoder_dsi_remove(priv); meson_encoder_hdmi_remove(priv); meson_encoder_cvbs_remove(priv); diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h index c62ee358456f..b23009a3380f 100644 --- a/drivers/gpu/drm/meson/meson_drv.h +++ b/drivers/gpu/drm/meson/meson_drv.h @@ -28,6 +28,7 @@ enum vpu_compatible { enum { MESON_ENC_CVBS = 0, MESON_ENC_HDMI, + MESON_ENC_DSI, MESON_ENC_LAST, }; diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.c b/drivers/gpu/drm/meson/meson_encoder_dsi.c new file mode 100644 index 000000000000..812e172dec63 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "meson_drv.h" +#include "meson_encoder_dsi.h" +#include "meson_registers.h" +#include "meson_venc.h" +#include "meson_vclk.h" + +struct meson_encoder_dsi { + struct drm_encoder encoder; + struct drm_bridge bridge; + struct drm_bridge *next_bridge; + struct meson_drm *priv; +}; + +#define bridge_to_meson_encoder_dsi(x) \ + container_of(x, struct meson_encoder_dsi, bridge) + +static int meson_encoder_dsi_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct meson_encoder_dsi *encoder_dsi = bridge_to_meson_encoder_dsi(bridge); + + return drm_bridge_attach(bridge->encoder, encoder_dsi->next_bridge, + &encoder_dsi->bridge, flags); +} + +static void meson_encoder_dsi_atomic_enable(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state) +{ + struct meson_encoder_dsi *encoder_dsi = bridge_to_meson_encoder_dsi(bridge); + struct drm_atomic_state *state = bridge_state->base.state; + struct meson_drm *priv = encoder_dsi->priv; + struct drm_connector_state *conn_state; + struct drm_crtc_state *crtc_state; + struct drm_connector *connector; + + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); + if (WARN_ON(!connector)) + return; + + conn_state = drm_atomic_get_new_connector_state(state, connector); + if (WARN_ON(!conn_state)) + return; + + crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); + if (WARN_ON(!crtc_state)) + return; + + /* ENCL clock setup is handled by CCF */ + + meson_venc_mipi_dsi_mode_set(priv, &crtc_state->adjusted_mode); + meson_encl_load_gamma(priv); + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, ENCL_VIDEO_MODE_ADV_VFIFO_EN, + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV)); + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN)); + + writel_bits_relaxed(BIT(0), 0, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); + + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN)); +} + +static void meson_encoder_dsi_atomic_disable(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state) +{ + struct meson_encoder_dsi *meson_encoder_dsi = + bridge_to_meson_encoder_dsi(bridge); + struct meson_drm *priv = meson_encoder_dsi->priv; + + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN)); + + writel_bits_relaxed(BIT(0), BIT(0), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); +} + +static const struct drm_bridge_funcs meson_encoder_dsi_bridge_funcs = { + .attach = meson_encoder_dsi_attach, + .atomic_enable = meson_encoder_dsi_atomic_enable, + .atomic_disable = meson_encoder_dsi_atomic_disable, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, +}; + +int meson_encoder_dsi_init(struct meson_drm *priv) +{ + struct meson_encoder_dsi *meson_encoder_dsi; + struct device_node *remote; + int ret; + + meson_encoder_dsi = devm_kzalloc(priv->dev, sizeof(*meson_encoder_dsi), GFP_KERNEL); + if (!meson_encoder_dsi) + return -ENOMEM; + + /* DSI Transceiver Bridge */ + remote = of_graph_get_remote_node(priv->dev->of_node, 2, 0); + if (!remote) { + dev_err(priv->dev, "DSI transceiver device is disabled"); + return 0; + } + + meson_encoder_dsi->next_bridge = of_drm_find_bridge(remote); + if (!meson_encoder_dsi->next_bridge) { + dev_dbg(priv->dev, "Failed to find DSI transceiver bridge\n"); + return -EPROBE_DEFER; + } + + /* DSI Encoder Bridge */ + meson_encoder_dsi->bridge.funcs = &meson_encoder_dsi_bridge_funcs; + meson_encoder_dsi->bridge.of_node = priv->dev->of_node; + meson_encoder_dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; + + drm_bridge_add(&meson_encoder_dsi->bridge); + + meson_encoder_dsi->priv = priv; + + /* Encoder */ + ret = drm_simple_encoder_init(priv->drm, &meson_encoder_dsi->encoder, + DRM_MODE_ENCODER_DSI); + if (ret) { + dev_err(priv->dev, "Failed to init DSI encoder: %d\n", ret); + return ret; + } + + meson_encoder_dsi->encoder.possible_crtcs = BIT(0); + + /* Attach DSI Encoder Bridge to Encoder */ + ret = drm_bridge_attach(&meson_encoder_dsi->encoder, &meson_encoder_dsi->bridge, NULL, 0); + if (ret) { + dev_err(priv->dev, "Failed to attach bridge: %d\n", ret); + return ret; + } + + /* + * We should have now in place: + * encoder->[dsi encoder bridge]->[dw-mipi-dsi bridge]->[panel bridge]->[panel] + */ + + priv->encoders[MESON_ENC_DSI] = meson_encoder_dsi; + + dev_dbg(priv->dev, "DSI encoder initialized\n"); + + return 0; +} + +void meson_encoder_dsi_remove(struct meson_drm *priv) +{ + struct meson_encoder_dsi *meson_encoder_dsi; + + if (priv->encoders[MESON_ENC_DSI]) { + meson_encoder_dsi = priv->encoders[MESON_ENC_DSI]; + drm_bridge_remove(&meson_encoder_dsi->bridge); + drm_bridge_remove(meson_encoder_dsi->next_bridge); + } +} diff --git a/drivers/gpu/drm/meson/meson_encoder_dsi.h b/drivers/gpu/drm/meson/meson_encoder_dsi.h new file mode 100644 index 000000000000..9277d7015193 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_encoder_dsi.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2021 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef __MESON_ENCODER_DSI_H +#define __MESON_ENCODER_DSI_H + +int meson_encoder_dsi_init(struct meson_drm *priv); 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Tue, 30 May 2023 00:38:27 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id m4-20020a5d4a04000000b003079c402762sm2312013wrq.19.2023.05.30.00.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 00:38:27 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:13 +0200 Subject: [PATCH v5 12/17] drm/meson: add support for MIPI-DSI transceiver MIME-Version: 1.0 Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-12-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong , Jagan Teki , Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=19297; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=vdNged+bT879opvCVPv6gCiacGfP+EnbSlkc5Uackdg=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafiIkw9gKoaNh108AEtzF2eG4nQrk5QZ25klcNz aoxua/aJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn4gAKCRB33NvayMhJ0eQKD/ 9gAts/+rd7NIeBPNj1L6CiWSRU8DVHN75lhmUl4NR11ctuHHc5d2OeckKK49KuhVXfECOZW9f87Qj3 o6heThKy6y/WboNt03Es3aDEps85ou6hkGg/jAPL2A0R2ifteNyS614qEhVjsL+1qx+r6QEi5XfrN8 z3WHZMxFI5J+qinxR8IUuewJTxJmeg9K/onJS6zeN42xM2cAVp5q2HIKebAZpkhOe/0S1oAw6KmbMG tXwjrH0igxK7iPf5ZuoAp5LYKL6auAmzGDObL96s1t2FIMkct7BuEAUccV1Il9G/Kdc2wCgZYrLs6Z AtyGzjvVuWw224xEl28vCq0GK4FOHKurHT5wUXg3XFZcSbjy89F1SDQmwbtsTvfjtdiL9WLKV2MDZs qc9u2/yaO064xE5H2lpbn7y7QUtI9NvLBNTjQSVxsszVVOeq1t1j3z50O23sqxQPPIidp59iNug/sz 8spTyNn1CB3QmMRyaPH+HaxxFfZiZGwZadPoV50bjqvgDfmv9GSA6+0XI4LkFKPCtfagc/P9+UL7+e 0zBO1YHVg4z6zAQvJDXuvlBe4zFTBJh6rSqTHenbS/8Je9T/cZBlvFFHdMFC4f426qFgyXjE2j2XuK Eje8R/7+zrxqfZKsNB/b+suRIzvNB/R8MK4nxjf/6q896vvcvUHilBCvY4PQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_083829_806614_18A3F153 X-CRM114-Status: GOOD ( 24.48 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The Amlogic G12A/G12B/SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data inputs similar to the DW-HDMI Glue on other Amlogic SoCs. This adds support for the Glue managing the transceiver, mimicing the init flow provided by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the Analog PHY in the proper way. An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the DW-MIPI-DSI transceiver. Signed-off-by: Neil Armstrong Reviewed-by: Jagan Teki Signed-off-by: Neil Armstrong Reviewed-by: Nicolas Belin Tested-by: Nicolas Belin # on Khadas VIM3 + TS050 Panel --- drivers/gpu/drm/meson/Kconfig | 7 + drivers/gpu/drm/meson/Makefile | 1 + drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 352 ++++++++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 160 ++++++++++++++ 4 files changed, 520 insertions(+) diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig index 823909da87db..615fdd0ce41b 100644 --- a/drivers/gpu/drm/meson/Kconfig +++ b/drivers/gpu/drm/meson/Kconfig @@ -17,3 +17,10 @@ config DRM_MESON_DW_HDMI default y if DRM_MESON select DRM_DW_HDMI imply DRM_DW_HDMI_I2S_AUDIO + +config DRM_MESON_DW_MIPI_DSI + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display" + depends on DRM_MESON + default y if DRM_MESON + select DRM_DW_MIPI_DSI + select GENERIC_PHY_MIPI_DPHY diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index 833e18c20603..43071bdbd4b9 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -6,3 +6,4 @@ meson-drm-y += meson_encoder_hdmi.o meson_encoder_dsi.o obj-$(CONFIG_DRM_MESON) += meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c new file mode 100644 index 000000000000..dd505ac37976 --- /dev/null +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2021 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include