From patchwork Tue May 30 22:49:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 13261192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4C30C77B73 for ; Tue, 30 May 2023 22:53:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IXbhaGgSXemPXY0SErZrGxB1AV4NGuEQai6qWwl+HEg=; b=byThGsN4KvZZH8amrV8quHgT+O QV2MNJHrezT9Hei+Q2SRNFQ0Q6rblxYrEDzNJ6NW+/x3bpsLfsiBbkiEtyolVvuZrm4bAVUd/B59i DxfTdjU9OfDCXSa16CzTCudZ7dCtbTSgnQa3ghCT3NSW1qZoaiZESQekvUbZH1ZZ72kVMH3QxwdTB ULyQSLdhAS7MvRN52QKnXj9rwBCerADBWwsmxIoIyAFmSiOSgJueoqCYt34K+ljZ2153Cylt4FvU+ c8gDsleS1i0MVKSxxsfHQhqi0wNmMSYHKInTQv/qmwl2vqoQxeiKVhXpcdctFE9hyDgYOUaN/rTUm XiABZFqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q48Co-00FNyi-04; Tue, 30 May 2023 22:52:42 +0000 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q48Cj-00FNxI-1q for linux-arm-kernel@lists.infradead.org; Tue, 30 May 2023 22:52:39 +0000 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1b04782fe07so17931815ad.3 for ; Tue, 30 May 2023 15:52:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1685487156; x=1688079156; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=CHxg7TDDksTOHH9Hr1QUGjfXuBtyVKw+a+WQWARiSuk=; b=JkwDMXswaXZB72sVx/iU+h/vKB/WQBNWeGctJJnFlQ0WXvsdLevGxuU1OnVrV1ZQ8h sONlIbXdRfRotTDdXDQxLUcVmsQ7WOcHfOMbAwS6KZ9J6wQFxiidW4PjDtA1KRRAqcSL WE9KbdGvc+dz8t0hfZq39iHhzGo1uDqzzffLk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685487156; x=1688079156; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=CHxg7TDDksTOHH9Hr1QUGjfXuBtyVKw+a+WQWARiSuk=; b=dnd/3RmI5+cnbLMKodvRmxsDA9Aw0CRKzvcIAS7GI0KBSW7EaRV8rlxsMkO9UtJCtq YFiVvzTxUzHdZUXgbP9bbQyz47W7KhP2gzGroZsss8Hy3LynXeEtmHZ9GFrLyTmbJw1Z DKymnoPCelpzKZsCK5v8Is/YVNaRDyOuCRMhGjnVqQuc1Hd79VID5hvZM+TI5XzepwPB BnyMtnkmiZweSO9lYl78Y5ql/cfXZ+IsCtXjrUHnEp9g+fk9olAi7GWWxGVvFkhVFBLo 7X4JKO5AOOuVmKujttvDj1d5iFMzIP8T/3yXto1cy3zwli85ZeQJQ+JXk2ryILp1KMF3 +C+w== X-Gm-Message-State: AC+VfDxMcHt/XSr1A7JnXSfT1TVnoqPVivNQ4Lmh38LxbI2NdUKVfWPi S8P77on+PoYYEKNqJYUwCJqF3Q== X-Google-Smtp-Source: ACHHUZ5WlODrDTtoZX8GEYCbVj1jaRCwAA3DgwgGADMmFo2HRbK/qQRzvL7JF/EDSPcmpXzYCOp4Sw== X-Received: by 2002:a17:903:644:b0:1af:babd:7b6d with SMTP id kh4-20020a170903064400b001afbabd7b6dmr3075052plb.52.1685487156127; Tue, 30 May 2023 15:52:36 -0700 (PDT) Received: from stbirv-lnx-3.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id s3-20020a170902b18300b001a1b66af22fsm10805011plr.62.2023.05.30.15.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 15:52:35 -0700 (PDT) From: Florian Fainelli To: stable@vger.kernel.org Cc: Pierre Gondois , Sudeep Holla , Florian Fainelli , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , Akihiko Odaki , Palmer Dabbelt , Gavin Shan , Jeremy Linton , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list) Subject: [PATCH stable 6.3 1/4] cacheinfo: Add use_arch[|_cache]_info field/function Date: Tue, 30 May 2023 15:49:11 -0700 Message-Id: <20230530224914.1251409-2-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230530224914.1251409-1-florian.fainelli@broadcom.com> References: <20230530224914.1251409-1-florian.fainelli@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_155237_612041_D38581B6 X-CRM114-Status: GOOD ( 19.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pierre Gondois commit ef9f643a9f8b62bcbcc51f0e0af8599adc2e17ed upstream The cache information can be extracted from either a Device Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1 for arm64). The clidr_el1 register is used only if DT/ACPI information is not available. It does not states how caches are shared among CPUs. Add a use_arch_cache_info field/function to identify when the DT/ACPI doesn't provide cache information. Use this information to assume L1 caches are privates and L2 and higher are shared among all CPUs. Signed-off-by: Pierre Gondois Link: https://lore.kernel.org/r/20230414081453.244787-5-pierre.gondois@arm.com Signed-off-by: Sudeep Holla Signed-off-by: Florian Fainelli --- drivers/base/cacheinfo.c | 12 ++++++++++-- include/linux/cacheinfo.h | 6 ++++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index ea8f416852bd..8120ac1ddbe4 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -28,6 +28,9 @@ static DEFINE_PER_CPU(struct cpu_cacheinfo, ci_cpu_cacheinfo); #define per_cpu_cacheinfo_idx(cpu, idx) \ (per_cpu_cacheinfo(cpu) + (idx)) +/* Set if no cache information is found in DT/ACPI. */ +static bool use_arch_info; + struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu) { return ci_cacheinfo(cpu); @@ -40,7 +43,8 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, * For non DT/ACPI systems, assume unique level 1 caches, * system-wide shared caches for all other levels. */ - if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI))) + if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)) || + use_arch_info) return (this_leaf->level != 1) && (sib_leaf->level != 1); if ((sib_leaf->attributes & CACHE_ID) && @@ -343,6 +347,10 @@ static int cache_setup_properties(unsigned int cpu) else if (!acpi_disabled) ret = cache_setup_acpi(cpu); + // Assume there is no cache information available in DT/ACPI from now. + if (ret && use_arch_cache_info()) + use_arch_info = true; + return ret; } @@ -361,7 +369,7 @@ static int cache_shared_cpu_map_setup(unsigned int cpu) * to update the shared cpu_map if the cache attributes were * populated early before all the cpus are brought online */ - if (!last_level_cache_is_valid(cpu)) { + if (!last_level_cache_is_valid(cpu) && !use_arch_info) { ret = cache_setup_properties(cpu); if (ret) return ret; diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index 908e19d17f49..b91cc9991c7c 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -129,4 +129,10 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level) return -1; } +#ifdef CONFIG_ARM64 +#define use_arch_cache_info() (true) +#else +#define use_arch_cache_info() (false) +#endif + #endif /* _LINUX_CACHEINFO_H */ From patchwork Tue May 30 22:49:12 2023 Content-Type: text/plain; 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Tue, 30 May 2023 15:52:37 -0700 (PDT) Received: from stbirv-lnx-3.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id s3-20020a170902b18300b001a1b66af22fsm10805011plr.62.2023.05.30.15.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 15:52:37 -0700 (PDT) From: Florian Fainelli To: stable@vger.kernel.org Cc: Radu Rendec , Pierre Gondois , Sudeep Holla , Florian Fainelli , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , Akihiko Odaki , Palmer Dabbelt , Gavin Shan , Jeremy Linton , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list) Subject: [PATCH stable 6.3 2/4] cacheinfo: Add arch specific early level initializer Date: Tue, 30 May 2023 15:49:12 -0700 Message-Id: <20230530224914.1251409-3-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230530224914.1251409-1-florian.fainelli@broadcom.com> References: <20230530224914.1251409-1-florian.fainelli@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_155241_049788_D585E7AA X-CRM114-Status: GOOD ( 31.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Radu Rendec commit 6539cffa94957241c096099a57d05fa4d8c7db8a upstream This patch gives architecture specific code the ability to initialize the cache level and allocate cacheinfo memory early, when cache level initialization runs on the primary CPU for all possible CPUs. This is part of a patch series that attempts to further the work in commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU"). Previously, in the absence of any DT/ACPI cache info, architecture specific cache detection and info allocation for secondary CPUs would happen in non-preemptible context during early CPU initialization and trigger a "BUG: sleeping function called from invalid context" splat on an RT kernel. More specifically, this patch adds the early_cache_level() function, which is called by fetch_cache_info() as a fallback when the number of cache leaves cannot be extracted from DT/ACPI. In the default generic (weak) implementation, this new function returns -ENOENT, which preserves the original behavior for architectures that do not implement the function. Since early detection can get the number of cache leaves wrong in some cases*, additional logic is added to still call init_cache_level() later on the secondary CPU, therefore giving the architecture specific code an opportunity to go back and fix the initial guess. Again, the original behavior is preserved for architectures that do not implement the new function. * For example, on arm64, CLIDR_EL1 detection works only when it runs on the current CPU. In other words, a CPU cannot detect the cache depth for any other CPU than itself. Signed-off-by: Radu Rendec Reviewed-by: Pierre Gondois Link: https://lore.kernel.org/r/20230412185759.755408-2-rrendec@redhat.com Signed-off-by: Sudeep Holla Signed-off-by: Florian Fainelli --- drivers/base/cacheinfo.c | 75 +++++++++++++++++++++++++++------------ include/linux/cacheinfo.h | 2 ++ 2 files changed, 55 insertions(+), 22 deletions(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 8120ac1ddbe4..14aa62c3f10f 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -437,6 +437,11 @@ static void free_cache_attributes(unsigned int cpu) cache_shared_cpu_map_remove(cpu); } +int __weak early_cache_level(unsigned int cpu) +{ + return -ENOENT; +} + int __weak init_cache_level(unsigned int cpu) { return -ENOENT; @@ -462,56 +467,82 @@ int allocate_cache_info(int cpu) int fetch_cache_info(unsigned int cpu) { - struct cpu_cacheinfo *this_cpu_ci; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); unsigned int levels = 0, split_levels = 0; int ret; if (acpi_disabled) { ret = init_of_cache_level(cpu); - if (ret < 0) - return ret; } else { ret = acpi_get_cache_info(cpu, &levels, &split_levels); - if (ret < 0) + if (!ret) { + this_cpu_ci->num_levels = levels; + /* + * This assumes that: + * - there cannot be any split caches (data/instruction) + * above a unified cache + * - data/instruction caches come by pair + */ + this_cpu_ci->num_leaves = levels + split_levels; + } + } + + if (ret || !cache_leaves(cpu)) { + ret = early_cache_level(cpu); + if (ret) return ret; - this_cpu_ci = get_cpu_cacheinfo(cpu); - this_cpu_ci->num_levels = levels; - /* - * This assumes that: - * - there cannot be any split caches (data/instruction) - * above a unified cache - * - data/instruction caches come by pair - */ - this_cpu_ci->num_leaves = levels + split_levels; + if (!cache_leaves(cpu)) + return -ENOENT; + + this_cpu_ci->early_ci_levels = true; } - if (!cache_leaves(cpu)) - return -ENOENT; return allocate_cache_info(cpu); } -int detect_cache_attributes(unsigned int cpu) +static inline int init_level_allocate_ci(unsigned int cpu) { - int ret; + unsigned int early_leaves = cache_leaves(cpu); /* Since early initialization/allocation of the cacheinfo is allowed * via fetch_cache_info() and this also gets called as CPU hotplug * callbacks via cacheinfo_cpu_online, the init/alloc can be skipped * as it will happen only once (the cacheinfo memory is never freed). - * Just populate the cacheinfo. + * Just populate the cacheinfo. However, if the cacheinfo has been + * allocated early through the arch-specific early_cache_level() call, + * there is a chance the info is wrong (this can happen on arm64). In + * that case, call init_cache_level() anyway to give the arch-specific + * code a chance to make things right. */ - if (per_cpu_cacheinfo(cpu)) - goto populate_leaves; + if (per_cpu_cacheinfo(cpu) && !ci_cacheinfo(cpu)->early_ci_levels) + return 0; if (init_cache_level(cpu) || !cache_leaves(cpu)) return -ENOENT; - ret = allocate_cache_info(cpu); + /* + * Now that we have properly initialized the cache level info, make + * sure we don't try to do that again the next time we are called + * (e.g. as CPU hotplug callbacks). + */ + ci_cacheinfo(cpu)->early_ci_levels = false; + + if (cache_leaves(cpu) <= early_leaves) + return 0; + + kfree(per_cpu_cacheinfo(cpu)); + return allocate_cache_info(cpu); +} + +int detect_cache_attributes(unsigned int cpu) +{ + int ret; + + ret = init_level_allocate_ci(cpu); if (ret) return ret; -populate_leaves: /* * If LLC is valid the cache leaves were already populated so just go to * update the cpu map. diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index b91cc9991c7c..a5cfd44fab45 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -76,9 +76,11 @@ struct cpu_cacheinfo { unsigned int num_levels; unsigned int num_leaves; bool cpu_map_populated; + bool early_ci_levels; }; struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); +int early_cache_level(unsigned int cpu); int init_cache_level(unsigned int cpu); int init_of_cache_level(unsigned int cpu); int populate_cache_leaves(unsigned int cpu); From patchwork Tue May 30 22:49:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 13261195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E655C77B7A for ; Tue, 30 May 2023 22:53:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; 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Tue, 30 May 2023 15:52:39 -0700 (PDT) Received: from stbirv-lnx-3.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id s3-20020a170902b18300b001a1b66af22fsm10805011plr.62.2023.05.30.15.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 15:52:39 -0700 (PDT) From: Florian Fainelli To: stable@vger.kernel.org Cc: Radu Rendec , Pierre Gondois , Sudeep Holla , Florian Fainelli , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , Akihiko Odaki , Palmer Dabbelt , Gavin Shan , Jeremy Linton , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list) Subject: [PATCH stable 6.3 3/4] cacheinfo: Add arm64 early level initializer implementation Date: Tue, 30 May 2023 15:49:13 -0700 Message-Id: <20230530224914.1251409-4-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230530224914.1251409-1-florian.fainelli@broadcom.com> References: <20230530224914.1251409-1-florian.fainelli@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_155242_771913_247A2FAB X-CRM114-Status: GOOD ( 22.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Radu Rendec commit c931680cfa958c8fe9ace31a1dbeefff75597d54 upstream This patch adds an architecture specific early cache level detection handler for arm64. This is basically the CLIDR_EL1 based detection that was previously done (only) in init_cache_level(). This is part of a patch series that attempts to further the work in commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU"). Previously, in the absence of any DT/ACPI cache info, architecture specific cache detection and info allocation for secondary CPUs would happen in non-preemptible context during early CPU initialization and trigger a "BUG: sleeping function called from invalid context" splat on an RT kernel. This patch does not solve the problem completely for RT kernels. It relies on the assumption that on most systems, the CPUs are symmetrical and therefore have the same number of cache leaves. The cacheinfo memory is allocated early (on the primary CPU), relying on the new handler. If later (when CLIDR_EL1 based detection runs again on the secondary CPU) the initial assumption proves to be wrong and the CPU has in fact more leaves, the cacheinfo memory is reallocated, and that still triggers a splat on an RT kernel. In other words, asymmetrical CPU systems *must* still provide cacheinfo data in DT/ACPI to avoid the splat on RT kernels (unless secondary CPUs happen to have less leaves than the primary CPU). But symmetrical CPU systems (the majority) can now get away without the additional DT/ACPI data and rely on CLIDR_EL1 based detection. Signed-off-by: Radu Rendec Reviewed-by: Pierre Gondois Link: https://lore.kernel.org/r/20230412185759.755408-3-rrendec@redhat.com Signed-off-by: Sudeep Holla Signed-off-by: Florian Fainelli --- arch/arm64/kernel/cacheinfo.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index c307f69e9b55..d9c9218fa1fd 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -38,11 +38,9 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, this_leaf->type = type; } -int init_cache_level(unsigned int cpu) +static void detect_cache_level(unsigned int *level_p, unsigned int *leaves_p) { unsigned int ctype, level, leaves; - int fw_level, ret; - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { ctype = get_cache_type(level); @@ -54,6 +52,27 @@ int init_cache_level(unsigned int cpu) leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; } + *level_p = level; + *leaves_p = leaves; +} + +int early_cache_level(unsigned int cpu) +{ + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + + detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); + + return 0; +} + +int init_cache_level(unsigned int cpu) +{ + unsigned int level, leaves; + int fw_level, ret; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + + detect_cache_level(&level, &leaves); + if (acpi_disabled) { fw_level = of_find_last_cache_level(cpu); } else { From patchwork Tue May 30 22:49:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 13261193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A36F7C77B73 for ; Tue, 30 May 2023 22:53:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Mal7D3KD0+Etl+aU08Wy8dlx3VC/gfiSetxzJBU1i0o=; b=ePf9f7bPPZ6rVjsjXw08jSP1ck 680OAb6cnIlwRt4FnAbVMCAhC5Ob355jcGzY+e0sAFS9R0NPiE1zc8u7kXtdAeEt52Q6T4GRxw9b4 mZRGNPdXYp1F+2dmhGyn7iElPIOvL+c8r5vQl70Hac0VcFVc6RQd84qxgDCREDctkbQFIp31B8uP9 er9KVdLGZaYSuJhpH5G0+iGmdYMC/nZ9JNorJwC4Zwt0N7dX9PR0J0DNxHpwEdwKdxjKOBvaGvoPB ehPHB4/qPtAa+uan81/LKh27cwWRRWjZ3K1rxo0RapQaONfOx019uTajCATcNcSgc2r6TGYoEJaHg EMHwuhpQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q48D5-00FO4F-3D; Tue, 30 May 2023 22:53:00 +0000 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q48Cp-00FNyj-1O for linux-arm-kernel@lists.infradead.org; Tue, 30 May 2023 22:52:44 +0000 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-51f6461af24so3233279a12.2 for ; Tue, 30 May 2023 15:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1685487161; x=1688079161; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=+mY8f7+lQRr9+WWApLUgb/qq97rDifPoZmG/x+kSgj4=; b=exw11y2kgnwsbp4VEf/g4VsyoJkmnw96PnKWtKmIMVVqzgc3WamGpPHKnQJralxq86 WDye2S75Pba1TKHR1VERtIwfUAuqJ2h1ahqZtFkLy2+MeZNjb5MIx2fIBin4jR4iMxlx +aAoRT8lRDvimIvSJil3xZsHsCtcC8I7GYDuE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685487161; x=1688079161; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=+mY8f7+lQRr9+WWApLUgb/qq97rDifPoZmG/x+kSgj4=; b=U+8lT+0RiQoWl62Rieg1i3z2CxMOJQl789k6aVx8fvUf5RQn9f7Gv93KgCbddoMlpg xNOx/A9XWNZOF9nR5KCg0d4izLwqV97ExWsw5zT1AUYdPiF3ZX9ymRmhXjv/hktLVy4D JxNFHGSssWkYV779MExNBrFIzEvarQOqnxTxh6nhU++Gw/+m994RbHosvYLK7+3RbMCJ CMJxayA0n2ztTnHNjWVZRON/xW+av9+N1UE1VoNm8fJExbynG+qFgrIl8bssMVDf38NV puAFUjIP8GQNolKcRPO8obScXpI2uh/0tgUvjGanKpcK/epK98z1SgbLffy67z8O3keU Y0vQ== X-Gm-Message-State: AC+VfDwM6Q0VF6s/8aEBJJD4XwLxj/NMg6OE16j3Sk/clpuSGmJv3MCI 86TdMvG+KFQQNTak1RbNbUngWg== X-Google-Smtp-Source: ACHHUZ514tMNVAPyXUUwKU7m15MSmGf6kR5Vrqsm0Cgrx6cTalyH0/gkws0SpyTliJjKa47mardFWA== X-Received: by 2002:a17:903:120f:b0:1ae:1364:6079 with SMTP id l15-20020a170903120f00b001ae13646079mr4127903plh.44.1685487161594; Tue, 30 May 2023 15:52:41 -0700 (PDT) Received: from stbirv-lnx-3.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id s3-20020a170902b18300b001a1b66af22fsm10805011plr.62.2023.05.30.15.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 15:52:41 -0700 (PDT) From: Florian Fainelli To: stable@vger.kernel.org Cc: Radu Rendec , Pierre Gondois , Sudeep Holla , Florian Fainelli , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , "Rafael J. Wysocki" , Akihiko Odaki , Palmer Dabbelt , Gavin Shan , Jeremy Linton , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-kernel@vger.kernel.org (open list) Subject: [PATCH stable 6.3 4/4] cacheinfo: Allow early level detection when DT/ACPI info is missing/broken Date: Tue, 30 May 2023 15:49:14 -0700 Message-Id: <20230530224914.1251409-5-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230530224914.1251409-1-florian.fainelli@broadcom.com> References: <20230530224914.1251409-1-florian.fainelli@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_155243_468220_1B76407B X-CRM114-Status: GOOD ( 21.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Radu Rendec commit e103d55465db06c5344201fd5fa11bb19bc479c5 upstream Recent work enables cacheinfo memory for secondary CPUs to be allocated early, while still running on the primary CPU. That allows cacheinfo memory to be allocated safely on RT kernels. To make that work, the number of cache levels/leaves must be defined in the device tree or ACPI tables. Further work adds a path for early detection of the number of cache levels/leaves, which makes it possible to allocate the cacheinfo memory early without requiring extra DT/ACPI information. This patch addresses a specific issue with ACPI systems with no PPTT. In that case, parse_acpi_topology() returns an error code, which in turn makes init_cpu_topology() return early, before fetch_cache_info() is called. In that case, the early cache level detection doesn't run. The solution is to simply remove the "return" statement and let the code flow fall through to calling fetch_cache_info(). Signed-off-by: Radu Rendec Reported-by: Pierre Gondois Link: https://lore.kernel.org/all/dea94484-797f-3034-7b86-6d88801c0d91@arm.com/ Reviewed-by: Pierre Gondois Link: https://lore.kernel.org/r/20230412185759.755408-4-rrendec@redhat.com Signed-off-by: Sudeep Holla Signed-off-by: Florian Fainelli --- drivers/base/arch_topology.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index c4b6198d7461..b741b5ba82bd 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -835,10 +835,10 @@ void __init init_cpu_topology(void) if (ret) { /* * Discard anything that was parsed if we hit an error so we - * don't use partial information. + * don't use partial information. But do not return yet to give + * arch-specific early cache level detection a chance to run. */ reset_cpu_topology(); - return; } for_each_possible_cpu(cpu) {