From patchwork Wed May 31 15:03:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Detlev Casanova X-Patchwork-Id: 13262422 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10A5216423 for ; Wed, 31 May 2023 15:04:00 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9793412B; Wed, 31 May 2023 08:03:58 -0700 (PDT) Received: from arisu.mtl.collabora.ca (mtl.collabora.ca [66.171.169.34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9DBB26606EB1; Wed, 31 May 2023 16:03:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685545437; bh=ZwlXPYQPfk+GWd3QIJF4+YV66sRpXFI0cOCa/2Pkr1c=; h=From:To:Cc:Subject:Date:From; b=gJv5lCZCo9TpspztOoSp2+J7yKGfADEev9Peyk9pHP7lLl4bXSMcO45nu0OzA5AqA tg+zuNhlup2nWOeoe+1TGtwT97dGLvVmolwotYkCXOsdXoEwxLIAX6AuAUFTkjtr1f jVnkYEzZs/PraQjzYXfz3UpDNg8ZPbs2TH2Yi8KXAiQu888SPZ8sdF5iUt97+ohnXM j6XHJqmJvzugy/w5VxFSHrd6jdO5CT/kCq3FNjG5VSVRMpiE+KbiryXuLVKpIfeSWr SkNj24+b3ct8s/fR05oSjtFKD7aoinOrzpUK/b3uP6+QzO4m3BCIJR0NuJklenbgI+ J2ck/yqQlZBlw== From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , netdev@vger.kernel.org, devicetree@vger.kernel.org, Detlev Casanova Subject: [PATCH 1/2] dt-bindings: net: phy: Support external PHY xtal Date: Wed, 31 May 2023 11:03:39 -0400 Message-Id: <20230531150340.522994-1-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.39.3 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Ethernet PHYs can have external an clock that needs to be activated before probing the PHY. Signed-off-by: Detlev Casanova --- .../devicetree/bindings/net/ethernet-phy.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 4f574532ee13..e83a33c2aa59 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -93,6 +93,16 @@ properties: the turn around line low at end of the control phase of the MDIO transaction. + clock-names: + items: + - const: xtal + + clocks: + maxItems: 1 + description: + External clock connected to the PHY. If not specified it is assumed + that the PHY uses a fixed crystal or an internal oscillator. + enet-phy-lane-swap: $ref: /schemas/types.yaml#/definitions/flag description: From patchwork Wed May 31 15:03:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Detlev Casanova X-Patchwork-Id: 13262423 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4DC6154AB for ; Wed, 31 May 2023 15:04:21 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B14E5E43; Wed, 31 May 2023 08:04:12 -0700 (PDT) Received: from arisu.mtl.collabora.ca (mtl.collabora.ca [66.171.169.34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by madras.collabora.co.uk (Postfix) with ESMTPSA id D5F846606EB2; Wed, 31 May 2023 16:04:09 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685545451; bh=ojpftkR4i1FZMG72jz+SAgiRAqMlLbUDSyJeAdTo4nY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V7mMuiFuy/oZjT/E/zwMGXS97T7DIb4RyJ9VJp9TS9OvzuwpCTEXV5xrM8uS4ufMR MhCWdJhw/97WCAgQoMaMAshA2clPWxN+aEUuaXFCswmdlwGF7v60dei6rybplBpoAp CL82PTdQGLZhz4igNm94bDG0J28z772/+v2TWq+x0UhEVNgixsyUGZN8C7SMT9s8Iz xExkFD6cS8oXJ6zZnM538/tbRElTqVG5qbfsdvEpnUeESswWK6/BXNu7lS3UaT4YZT h0J8UO3PqOP0UmhikDx2wn+zy+nlwzyYKL567lhL8AS8L4LnaE+zCGtF0DryGOOHVE jLX6eljPHwUhg== From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , netdev@vger.kernel.org, devicetree@vger.kernel.org, Detlev Casanova Subject: [PATCH 2/2] net: phy: realtek: Add optional external PHY clock Date: Wed, 31 May 2023 11:03:40 -0400 Message-Id: <20230531150340.522994-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20230531150340.522994-1-detlev.casanova@collabora.com> References: <20230531150340.522994-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org In some cases, the PHY can use an external clock source instead of a crystal. Add an optional clock in the phy node to make sure that the clock source is enabled, if specified, before probing. Signed-off-by: Detlev Casanova --- drivers/net/phy/realtek.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 3d99fd6664d7..70c75dbbf799 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -12,6 +12,7 @@ #include #include #include +#include #define RTL821x_PHYSR 0x11 #define RTL821x_PHYSR_DUPLEX BIT(13) @@ -80,6 +81,7 @@ struct rtl821x_priv { u16 phycr1; u16 phycr2; bool has_phycr2; + struct clk *clk; }; static int rtl821x_read_page(struct phy_device *phydev) @@ -103,6 +105,11 @@ static int rtl821x_probe(struct phy_device *phydev) if (!priv) return -ENOMEM; + priv->clk = devm_clk_get_optional_enabled(dev, "xtal"); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "failed to get phy xtal clock\n"); + ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1); if (ret < 0) return ret;