From patchwork Fri Jun 2 09:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robbin Ehn X-Patchwork-Id: 13264987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 231BFC77B7A for ; Fri, 2 Jun 2023 09:41:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q51Hd-0002TU-9K; Fri, 02 Jun 2023 05:41:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q51Ha-0002T3-QL for qemu-devel@nongnu.org; Fri, 02 Jun 2023 05:41:19 -0400 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q51HX-0000D9-IK for qemu-devel@nongnu.org; Fri, 02 Jun 2023 05:41:18 -0400 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-4f5021faa16so2485369e87.2 for ; Fri, 02 Jun 2023 02:41:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1685698873; x=1688290873; h=mime-version:user-agent:content-transfer-encoding:date:cc:to:from :subject:message-id:from:to:cc:subject:date:message-id:reply-to; bh=le0QAAql+itTBpRz4mqbwg7nbDKJXpWGcULIraLJ6gs=; b=YAkIZpClkGm12/y2mCPaAEI0BCQCsKSP+Ue1zmJC2IKEkjEJ9Vgkbcf4LwFNI1Bcu8 EfDqS0CMhTxlRKKh023H3lIT8SIkOuCpdASP5G1u5JaPzQwam0IK5kjwBZZ/kn8n//0s WCG35xARzovH67Nf0IKexzfAB4PXpXrlfGk/OLZvT354BYZbrn5Uwg4oT11hEKnJUPIH 450XcLtoSQLDoNg9GjQsQZ09kQdpbrJsYVTvAz6oKz9jmJxVz6LeKf9uEr+WQ6K+LTC8 h8MbUQ6wzjc5knChC85JeUbOY9lgK+x6K66jDYlvPyI5+YjQUFMJ8XHfrMsOAYINubSB oxcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685698873; x=1688290873; h=mime-version:user-agent:content-transfer-encoding:date:cc:to:from :subject:message-id:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=le0QAAql+itTBpRz4mqbwg7nbDKJXpWGcULIraLJ6gs=; b=RYEF3WmrQQBwHVSTNjSYMa+We9CFQGLQIWRpXYIlEfMSRiDrn0gbgCQb49Of0DZSX/ Q2D1035dhOVb3WL2U/ClffeA+kVDiHvug/y4t7cC297wavCDBUALRntXxMWxkRVIc8u3 kMdGiee/v/pXpLHD4BIkRMQSKLPgB53qsC/HUzMYQuUfPd1JEq4NHhFi9DgtNexQJ6WW t/KiEnLhELMqbO8XDhbw5kQdUDDwcCqeu7PVcwSW1xi7Fznz8r8wQ8fQdvAvn6XNuwfn Koooan0zIX8ePuWvpZFcAXr9C6NHf6Oklj3+4GxVYPAxf72mo2SCXkrQFlRYvaEjH/AZ UPMA== X-Gm-Message-State: AC+VfDxdw35Sk02mHj93B4I2UwscrQucjZKjZ1BOOxZXYFGFNWKGwBH6 scLBQmHiB+ywdJJULAml76lIFQzo/rImT4XLbLAgAg== X-Google-Smtp-Source: ACHHUZ4sXF9WGhk8qBs83IDqR6DGcKxw03a20cWB6J5z580EDG99tpPVHd+WXTSJeRVEAfVF+PP9dA== X-Received: by 2002:a19:c214:0:b0:4f4:b92c:eef5 with SMTP id l20-20020a19c214000000b004f4b92ceef5mr1508280lfc.68.1685698873670; Fri, 02 Jun 2023 02:41:13 -0700 (PDT) Received: from [192.168.50.45] (h-155-4-92-80.A980.priv.bahnhof.se. [155.4.92.80]) by smtp.gmail.com with ESMTPSA id c24-20020ac25318000000b004eefdd8b37fsm105942lfh.194.2023.06.02.02.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 02:41:13 -0700 (PDT) Message-ID: Subject: [RFC v2] linux-user/riscv: Add syscall riscv_hwprobe From: Robbin Ehn To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, qemu-riscv@nongnu.org, richard.henderson@linaro.org Date: Fri, 02 Jun 2023 11:41:11 +0200 User-Agent: Evolution 3.48.1-0ubuntu1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::129; envelope-from=rehn@rivosinc.com; helo=mail-lf1-x129.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch adds the new syscall for the "RISC-V Hardware Probing Interface" (https://docs.kernel.org/riscv/hwprobe.html). Signed-off-by: Robbin Ehn --- v1->v2: Moved to syscall.c --- linux-user/riscv/syscall32_nr.h | 1 + linux-user/riscv/syscall64_nr.h | 1 + linux-user/syscall.c | 109 ++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+) diff --git a/linux-user/riscv/syscall32_nr.h b/linux-user/riscv/syscall32_nr.h index 1327d7dffa..412e58e5b2 100644 --- a/linux-user/riscv/syscall32_nr.h +++ b/linux-user/riscv/syscall32_nr.h @@ -228,6 +228,7 @@ #define TARGET_NR_accept4 242 #define TARGET_NR_arch_specific_syscall 244 #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15) +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14) #define TARGET_NR_prlimit64 261 #define TARGET_NR_fanotify_init 262 #define TARGET_NR_fanotify_mark 263 diff --git a/linux-user/riscv/syscall64_nr.h b/linux-user/riscv/syscall64_nr.h index 6659751933..29e1eb2075 100644 --- a/linux-user/riscv/syscall64_nr.h +++ b/linux-user/riscv/syscall64_nr.h @@ -251,6 +251,7 @@ #define TARGET_NR_recvmmsg 243 #define TARGET_NR_arch_specific_syscall 244 #define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15) +#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14) #define TARGET_NR_wait4 260 #define TARGET_NR_prlimit64 261 #define TARGET_NR_fanotify_init 262 diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 89b58b386b..cd394bbe26 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8772,6 +8772,74 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count) } #endif /* TARGET_NR_getdents64 */ +#if defined(TARGET_RISCV) + +#define RISCV_HWPROBE_KEY_MVENDORID 0 +#define RISCV_HWPROBE_KEY_MARCHID 1 +#define RISCV_HWPROBE_KEY_MIMPID 2 + +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) + +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) + +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) +#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) +#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) + +struct riscv_hwprobe { + int64_t key; + uint64_t value; +}; + +static void risc_hwprobe_fill_pairs(CPURISCVState *env, + struct riscv_hwprobe *pair, + size_t pair_count) +{ + const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); + + for (; pair_count > 0; pair_count--, pair++) { + pair->value = 0; + switch (pair->key) { + case RISCV_HWPROBE_KEY_MVENDORID: + pair->value = cfg->mvendorid; + break; + case RISCV_HWPROBE_KEY_MARCHID: + pair->value = cfg->marchid; + break; + case RISCV_HWPROBE_KEY_MIMPID: + pair->value = cfg->mimpid; + break; + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + pair->value = riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) ? + RISCV_HWPROBE_BASE_BEHAVIOR_IMA : 0; + break; + case RISCV_HWPROBE_KEY_IMA_EXT_0: + pair->value = riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) ? + RISCV_HWPROBE_IMA_FD : 0; + pair->value |= riscv_has_ext(env, RVC) ? + RISCV_HWPROBE_IMA_C : pair->value; + break; + case RISCV_HWPROBE_KEY_CPUPERF_0: + pair->value = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + break; + default: + pair->key = -1; + break; + } + } +} +#endif + #if defined(TARGET_NR_pivot_root) && defined(__NR_pivot_root) _syscall2(int, pivot_root, const char *, new_root, const char *, put_old) #endif @@ -13469,6 +13537,47 @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1, return ret; #endif +#if defined(TARGET_RISCV) + case TARGET_NR_riscv_hwprobe: + { + struct riscv_hwprobe *host_pairs; + + /* flags must be 0 */ + if (arg5 != 0) { + return -TARGET_EINVAL; + } + + /* check cpu_set */ + if (arg3 != 0) { + int ccpu; + size_t cpu_setsize = CPU_ALLOC_SIZE(arg3); + cpu_set_t *host_cpus = lock_user(VERIFY_READ, arg4, + cpu_setsize, 0); + if (!host_cpus) { + return -TARGET_EFAULT; + } + ccpu = CPU_COUNT_S(cpu_setsize, host_cpus); + unlock_user(host_cpus, arg4, cpu_setsize); + /* no selected cpu */ + if (ccpu == 0) { + return -TARGET_EINVAL; + } + } else if (arg4 != 0) { + return -TARGET_EINVAL; + } + + host_pairs = lock_user(VERIFY_WRITE, arg1, + sizeof(*host_pairs) * (size_t)arg2, 0); + if (host_pairs == NULL) { + return -TARGET_EFAULT; + } + risc_hwprobe_fill_pairs(cpu_env, host_pairs, arg2); + unlock_user(host_pairs, arg1, sizeof(*host_pairs) * (size_t)arg2); + ret = 0; + } + return ret; +#endif + default: qemu_log_mask(LOG_UNIMP, "Unsupported syscall: %d\n", num); return -TARGET_ENOSYS;