From patchwork Fri Jun 2 21:40:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Atwood X-Patchwork-Id: 13265874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6399C7EE2C for ; Fri, 2 Jun 2023 21:40:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 264C710E0F0; Fri, 2 Jun 2023 21:40:30 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id D498C10E0F0 for ; Fri, 2 Jun 2023 21:40:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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02 Jun 2023 14:40:27 -0700 From: Matt Atwood To: intel-gfx@lists.freedesktop.org Date: Fri, 2 Jun 2023 14:40:22 -0700 Message-Id: <20230602214022.1583682-1-matthew.s.atwood@intel.com> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: sync I915_PMU_MAX_GTS to I915_MAX_GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Set I915_PMU_MAX_GTS to value in I915_MAX_GT, theres no reason for these values to be different. v2: Change name of I915_PMU_MAX_GTS to I915_PMU_MAX_GT (Andi), Change I915_MAX_GT from 4 to 2 (Ashutosh), Explicitly set I915_PMU_MAX_GT to I915_MAX_GT (Andi) Cc: Tvrtko Ursulin Cc: Andi Shyti Cc: Umesh Nerlige Ramappa Cc: Ashutosh Dixit Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_pmu.c | 2 +- drivers/gpu/drm/i915/i915_pmu.h | 12 ++++++++---- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f1205ed3ba71..c3923f52ca56 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -314,7 +314,7 @@ struct drm_i915_private { /* * i915->gt[0] == &i915->gt0 */ -#define I915_MAX_GT 4 +#define I915_MAX_GT 2 struct intel_gt *gt[I915_MAX_GT]; struct kobject *sysfs_gt; diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index f96fe92dca4e..d35973b41186 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -132,7 +132,7 @@ static u32 frequency_enabled_mask(void) unsigned int i; u32 mask = 0; - for (i = 0; i < I915_PMU_MAX_GTS; i++) + for (i = 0; i < I915_PMU_MAX_GT; i++) mask |= config_mask(__I915_PMU_ACTUAL_FREQUENCY(i)) | config_mask(__I915_PMU_REQUESTED_FREQUENCY(i)); diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index d20592e7db99..260a39aaa06b 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -38,7 +38,11 @@ enum { __I915_NUM_PMU_SAMPLERS }; -#define I915_PMU_MAX_GTS 2 +#ifndef I915_MAX_GT +#define I915_MAX_GT 2 +#endif + +#define I915_PMU_MAX_GT I915_MAX_GT /* * How many different events we track in the global PMU mask. @@ -47,7 +51,7 @@ enum { */ #define I915_PMU_MASK_BITS \ (I915_ENGINE_SAMPLE_COUNT + \ - I915_PMU_MAX_GTS * __I915_PMU_TRACKED_EVENT_COUNT) + I915_PMU_MAX_GT * __I915_PMU_TRACKED_EVENT_COUNT) #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1) @@ -127,11 +131,11 @@ struct i915_pmu { * Only global counters are held here, while the per-engine ones are in * struct intel_engine_cs. */ - struct i915_pmu_sample sample[I915_PMU_MAX_GTS][__I915_NUM_PMU_SAMPLERS]; + struct i915_pmu_sample sample[I915_PMU_MAX_GT][__I915_NUM_PMU_SAMPLERS]; /** * @sleep_last: Last time GT parked for RC6 estimation. */ - ktime_t sleep_last[I915_PMU_MAX_GTS]; + ktime_t sleep_last[I915_PMU_MAX_GT]; /** * @irq_count: Number of interrupts *