From patchwork Fri Jun 2 23:40:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hancock X-Patchwork-Id: 13265973 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 689A6195 for ; Sat, 3 Jun 2023 00:39:58 +0000 (UTC) Received: from mx0d-0054df01.pphosted.com (mx0d-0054df01.pphosted.com [67.231.150.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84FBBE40 for ; Fri, 2 Jun 2023 17:39:56 -0700 (PDT) Received: from pps.filterd (m0209000.ppops.net [127.0.0.1]) by mx0c-0054df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 352NHxtr019830; Fri, 2 Jun 2023 19:41:46 -0400 Received: from can01-yt3-obe.outbound.protection.outlook.com (mail-yt3can01lp2169.outbound.protection.outlook.com [104.47.75.169]) by mx0c-0054df01.pphosted.com (PPS) with ESMTPS id 3ques3pcph-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Jun 2023 19:41:45 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=C05gMwMHdv/H2zQ/touj77d6s2JbuyKccOMY5MZkivlz/IAUN1gl8wf/lcsFbCo/KHV7R87rKU/mfLzTMgXFHUlZqHF8aOP6PKWvNUgBOtVvE4ctoJ/euLJ8N0SnLPZxUhex2Qheacg/UQvLN6/sFb4V0BO1S4JtFU2D52SAPL5JLiR0jvdFnjiSMRDdS3rS8s+BFeJ0StgII2j2US+oKVA8/EERy6H8/1fo3Dh+SzUiI9sdXeWwUSQwRpNQ+TaRRU94NrWV9OKMtoTndahSfiatiS1dHM6IQe9mUAFSm+VO003qX/r5uzdD/cBk+WIUYtHXnIlflKiCL2PUQWWsPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UPadptKD9Z2koX+L3eERKyBGmXqLU0A8id7eDjJyGp8=; b=EKW3YNZLcDZwMzsFeE9zIaKXRHtyB3ZXeZ9KNIscb8A631D5xLEG2DmQYX9lqL+PvfyjCvxvszGJFJYZJu94wRwqM6kwnYC+KL7APbVFQfWNqu9XJu3rptdGRGcadMq/iGH6KTG5h4ldYsrnl5XMQztwn80inpKXtlDGnWGAj/5DSL0xk8VPKBndaCe7QvR2Euc2ujavKEinDP8LiwynEQSy5dyw2XwaInQLb5oWYaLZcEnBrkN4q31iZPa951lQHUvYNf/S4hNJgTEsflzBM04pNFnbtGIS66a8jmzDzG7YTQ9WPATDXm3IUhthuVRx2QsVZDThBxXIpn/cT8id1A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=calian.com; dmarc=pass action=none header.from=calian.com; dkim=pass header.d=calian.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=calian.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UPadptKD9Z2koX+L3eERKyBGmXqLU0A8id7eDjJyGp8=; b=xGPs9HCJdvOFfAUKcwih3rorRWb9WeiR1DECFviMGxC0WMp8ANH8ZrdCWshUP8cj55UVehrq/FsjChyUPUuHkEOz9XR7TGR587VeDj2KiBV8VP9Op5dzTgxs2bl9waWlY7LGzSJewoUpAs5MBN91dCza/SsO43Mt58pUbD/bYo8= Received: from YT2PR01MB8838.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:b9::6) by YT1PR01MB8763.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:ca::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.27; Fri, 2 Jun 2023 23:41:44 +0000 Received: from YT2PR01MB8838.CANPRD01.PROD.OUTLOOK.COM ([fe80::c059:dcd5:ca20:4a0]) by YT2PR01MB8838.CANPRD01.PROD.OUTLOOK.COM ([fe80::c059:dcd5:ca20:4a0%6]) with mapi id 15.20.6455.028; Fri, 2 Jun 2023 23:41:44 +0000 From: Robert Hancock To: Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Robert Hancock Subject: [PATCH net-next 1/2] net: phy: micrel: Move KSZ9477 errata fixes to PHY driver Date: Fri, 2 Jun 2023 17:40:18 -0600 Message-Id: <20230602234019.436513-2-robert.hancock@calian.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230602234019.436513-1-robert.hancock@calian.com> References: <20230602234019.436513-1-robert.hancock@calian.com> X-ClientProxiedBy: MW4PR04CA0362.namprd04.prod.outlook.com (2603:10b6:303:81::7) To YT2PR01MB8838.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:b9::6) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: YT2PR01MB8838:EE_|YT1PR01MB8763:EE_ X-MS-Office365-Filtering-Correlation-Id: 180f30e2-7f1d-4543-5b37-08db63c2ec61 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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However, these errata are really a property of the PHY itself, not the switch they are part of, so this is kind of a layering violation. It makes more sense for these writes to be done inside the driver which binds to the PHY and not the driver for the containing device. This also addresses some issues where the ordering of when these writes are done may have been incorrect, causing the link to erratically fail to come up at the proper speed or at all. Doing this in the PHY driver during config_init ensures that they happen before anything else tries to change the state of the PHY on the port. The new code also ensures that autonegotiation is disabled during the register writes and re-enabled afterwards, as indicated by the latest version of the errata documentation from Microchip. Signed-off-by: Robert Hancock Reviewed-by: Andrew Lunn --- drivers/net/phy/micrel.c | 75 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 26ce0c5defcd..6d9f38b5ea17 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -1733,6 +1733,79 @@ static int ksz886x_read_status(struct phy_device *phydev) return genphy_read_status(phydev); } +struct ksz9477_errata_write { + u8 dev_addr; + u8 reg_addr; + u16 val; +}; + +static const struct ksz9477_errata_write ksz9477_errata_writes[] = { + /* Register settings are needed to improve PHY receive performance */ + {0x01, 0x6f, 0xdd0b}, + {0x01, 0x8f, 0x6032}, + {0x01, 0x9d, 0x248c}, + {0x01, 0x75, 0x0060}, + {0x01, 0xd3, 0x7777}, + {0x1c, 0x06, 0x3008}, + {0x1c, 0x08, 0x2000}, + + /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */ + {0x1c, 0x04, 0x00d0}, + + /* Energy Efficient Ethernet (EEE) feature select must be manually disabled */ + {0x07, 0x3c, 0x0000}, + + /* Register settings are required to meet data sheet supply current specifications */ + {0x1c, 0x13, 0x6eff}, + {0x1c, 0x14, 0xe6ff}, + {0x1c, 0x15, 0x6eff}, + {0x1c, 0x16, 0xe6ff}, + {0x1c, 0x17, 0x00ff}, + {0x1c, 0x18, 0x43ff}, + {0x1c, 0x19, 0xc3ff}, + {0x1c, 0x1a, 0x6fff}, + {0x1c, 0x1b, 0x07ff}, + {0x1c, 0x1c, 0x0fff}, + {0x1c, 0x1d, 0xe7ff}, + {0x1c, 0x1e, 0xefff}, + {0x1c, 0x20, 0xeeee}, +}; + +static int ksz9477_config_init(struct phy_device *phydev) +{ + int err; + int i; + + /* Apply PHY settings to address errata listed in + * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 + * Silicon Errata and Data Sheet Clarification documents. + * + * Document notes: Before configuring the PHY MMD registers, it is + * necessary to set the PHY to 100 Mbps speed with auto-negotiation + * disabled by writing to register 0xN100-0xN101. After writing the + * MMD registers, and after all errata workarounds that involve PHY + * register settings, write register 0xN100-0xN101 again to enable + * and restart auto-negotiation. + */ + err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX); + if (err) + return err; + + for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) { + const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i]; + + err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val); + if (err) + return err; + } + + err = genphy_restart_aneg(phydev); + if (err) + return err; + + return kszphy_config_init(phydev); +} + static int kszphy_get_sset_count(struct phy_device *phydev) { return ARRAY_SIZE(kszphy_hw_stats); @@ -3425,7 +3498,7 @@ static struct phy_driver ksphy_driver[] = { .phy_id_mask = MICREL_PHY_ID_MASK, .name = "Microchip KSZ9477", /* PHY_GBIT_FEATURES */ - .config_init = kszphy_config_init, + .config_init = ksz9477_config_init, .config_intr = kszphy_config_intr, .handle_interrupt = kszphy_handle_interrupt, .suspend = genphy_suspend, From patchwork Fri Jun 2 23:40:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Hancock X-Patchwork-Id: 13265969 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6481197 for ; Sat, 3 Jun 2023 00:09:10 +0000 (UTC) X-Greylist: delayed 1608 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 02 Jun 2023 17:09:03 PDT Received: from mx0c-0054df01.pphosted.com (mx0c-0054df01.pphosted.com [67.231.159.91]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F96FE49; Fri, 2 Jun 2023 17:09:03 -0700 (PDT) Received: from pps.filterd (m0208999.ppops.net [127.0.0.1]) by mx0c-0054df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 352NQfg4032013; Fri, 2 Jun 2023 19:41:49 -0400 Received: from can01-yqb-obe.outbound.protection.outlook.com (mail-yqbcan01lp2233.outbound.protection.outlook.com [104.47.75.233]) by mx0c-0054df01.pphosted.com (PPS) with ESMTPS id 3qucyv8gm2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Jun 2023 19:41:48 -0400 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PErWahYDnvFNOO09Kr08Es7viUMLPPpZTRaJwxsr3zlSwAfOLgA7eq/PBxzL1EG29zGa3SeSNbMoth6rdSwszOq1Q4FvupoXWe0XKHV8OgfW8jLyRdkDTju01RRbi+uyPKuGW3zD8vb6dgrlY6sj0VNHDIrGP0ZCxmGmS+Bx11WQrMGcFELtlY/lPgooFvkjsS9AJjC2BiLCM7BQK2oxq8RnpTZLklUpQSAZoXwdbRzltWwfBUNebUpxLtKvua/8JX5Gh0WA9eXatlwZBQmyjTtowMzHNZEJ7N6+Yiy8dmSpDBGLIQHS8gBTcOFMsLqGv8G6kWKj3I5HRHl5LVMWvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4a1GHjWv48hfwaafWrIPxfPJ79mO/X5LSe03tpJtXQk=; b=nKzabZnBAxFSpz4bF5tjHiVZdsraQrPYhoCj82OyRbldzJ3Xh4hLsc5NT9Zn2k6pG98rynUXCX8xujbD2AZqrTKed+ca1s9khrpVf4lrl0vjzVHmq8Zt1Su1Fr+fJJp8zdL9D0UYUQC8J+c6pkEGlnjGzJBjLiDI4j0nAg42y+3HXKbR+FUcZFNiibgLzsp+aV8gKjL2Ib9q6fsiZNK9V3G2yfTWn0l7frHgov+xq/BKoJP3ahHULcDi6JKWCIKzcWSA40XAqiJVda3WkOKBjTCAkznmnOX8mbCZ88ZOn+17YIvxUJXoIkNdhhK3BI8VdpLM8HV+5P58L1pCC2HpfA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=calian.com; dmarc=pass action=none header.from=calian.com; dkim=pass header.d=calian.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=calian.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4a1GHjWv48hfwaafWrIPxfPJ79mO/X5LSe03tpJtXQk=; b=pcJuhsBUix4ZPUrTb/Ks+iCNn6zj/YIdzELOdNiKas2N9weS0WNaQn58bvMLORaTZehmu2jDNpyTd2raI5+ilxWzCjIDGys9AvW1+yaiweaB4Z8/Cwg9iW1HwEZua8Sxsv33kugZla0mVcovJqyBYhLfeSpKCREOzLwHajCWpbs= Received: from YT2PR01MB8838.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:b9::6) by YT1PR01MB8763.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:ca::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.27; Fri, 2 Jun 2023 23:41:46 +0000 Received: from YT2PR01MB8838.CANPRD01.PROD.OUTLOOK.COM ([fe80::c059:dcd5:ca20:4a0]) by YT2PR01MB8838.CANPRD01.PROD.OUTLOOK.COM ([fe80::c059:dcd5:ca20:4a0%6]) with mapi id 15.20.6455.028; Fri, 2 Jun 2023 23:41:46 +0000 From: Robert Hancock To: Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. 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Remove it. Signed-off-by: Robert Hancock Reviewed-by: Andrew Lunn --- drivers/net/dsa/microchip/ksz9477.c | 74 ++------------------------ drivers/net/dsa/microchip/ksz_common.c | 4 -- drivers/net/dsa/microchip/ksz_common.h | 1 - 3 files changed, 4 insertions(+), 75 deletions(-) diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c index 47b54ecf2c6f..7720d53dc7a9 100644 --- a/drivers/net/dsa/microchip/ksz9477.c +++ b/drivers/net/dsa/microchip/ksz9477.c @@ -889,62 +889,6 @@ static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port) return interface; } -static void ksz9477_port_mmd_write(struct ksz_device *dev, int port, - u8 dev_addr, u16 reg_addr, u16 val) -{ - ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, - MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr)); - ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr); - ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, - MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr)); - ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); -} - -static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port) -{ - /* Apply PHY settings to address errata listed in - * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565 - * Silicon Errata and Data Sheet Clarification documents: - * - * Register settings are needed to improve PHY receive performance - */ - ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); - ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); - ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); - ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); - ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); - - /* Transmit waveform amplitude can be improved - * (1000BASE-T, 100BASE-TX, 10BASE-Te) - */ - ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); - - /* Energy Efficient Ethernet (EEE) feature select must - * be manually disabled (except on KSZ8565 which is 100Mbit) - */ - if (dev->info->gbit_capable[port]) - ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); - - /* Register settings are required to meet data sheet - * supply current specifications - */ - ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); - ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); -} - void ksz9477_get_caps(struct ksz_device *dev, int port, struct phylink_config *config) { @@ -1011,20 +955,10 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port) /* enable 802.1p priority */ ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); - if (dev->info->internal_phy[port]) { - /* do not force flow control */ - ksz_port_cfg(dev, port, REG_PORT_CTRL_0, - PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, - false); - - if (dev->info->phy_errata_9477) - ksz9477_phy_errata_setup(dev, port); - } else { - /* force flow control */ - ksz_port_cfg(dev, port, REG_PORT_CTRL_0, - PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, - true); - } + /* force flow control for non-PHY ports only */ + ksz_port_cfg(dev, port, REG_PORT_CTRL_0, + PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL, + !dev->info->internal_phy[port]); if (cpu_port) member = dsa_user_ports(ds); diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c index 423f944cc34c..42cb5742f552 100644 --- a/drivers/net/dsa/microchip/ksz_common.c +++ b/drivers/net/dsa/microchip/ksz_common.c @@ -1212,7 +1212,6 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 7, /* total physical port count */ .port_nirqs = 4, .ops = &ksz9477_dev_ops, - .phy_errata_9477 = true, .mib_names = ksz9477_mib_names, .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt = MIB_COUNTER_NUM, @@ -1244,7 +1243,6 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 6, /* total physical port count */ .port_nirqs = 2, .ops = &ksz9477_dev_ops, - .phy_errata_9477 = true, .mib_names = ksz9477_mib_names, .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt = MIB_COUNTER_NUM, @@ -1276,7 +1274,6 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 7, /* total physical port count */ .port_nirqs = 2, .ops = &ksz9477_dev_ops, - .phy_errata_9477 = true, .mib_names = ksz9477_mib_names, .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt = MIB_COUNTER_NUM, @@ -1356,7 +1353,6 @@ const struct ksz_chip_data ksz_switch_chips[] = { .port_cnt = 7, /* total physical port count */ .port_nirqs = 3, .ops = &ksz9477_dev_ops, - .phy_errata_9477 = true, .mib_names = ksz9477_mib_names, .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), .reg_mib_cnt = MIB_COUNTER_NUM, diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h index 055d61ff3fb8..9c5e8ea229fa 100644 --- a/drivers/net/dsa/microchip/ksz_common.h +++ b/drivers/net/dsa/microchip/ksz_common.h @@ -47,7 +47,6 @@ struct ksz_chip_data { int port_cnt; u8 port_nirqs; const struct ksz_dev_ops *ops; - bool phy_errata_9477; bool ksz87xx_eee_link_erratum; const struct ksz_mib_names *mib_names; int mib_cnt;