From patchwork Sat Jun 3 01:10:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20535C77B7A for ; Sat, 3 Jun 2023 01:11:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236891AbjFCBLJ (ORCPT ); Fri, 2 Jun 2023 21:11:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236772AbjFCBLG (ORCPT ); Fri, 2 Jun 2023 21:11:06 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED1C9E50 for ; Fri, 2 Jun 2023 18:11:03 -0700 (PDT) Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-2553b096ddfso2387464a91.1 for ; Fri, 02 Jun 2023 18:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754663; x=1688346663; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=NU+ycyGnxu88uw+EwETUIF4qNqsYgJat1S24XSYVjxU=; b=e5NNdTWQ1K2mv9p3/IYVxsicV6Twj5YqaoVaRDDMw+57CPht33+iismaab5Um2jnwA yVMjAmOr3waiqCHDGR8jd7dj1vSMo7majCIl4eKh5jHq8pTdPmNncvguNcNACVT9IwSv 2Bb05+PWypB8ig/lxkl3NZJ2l3TwDaGk650FUe5wEdSSt5ZBq0DZmx2uupHPUJMAHnQM cPe1AyWMwDZs2Mbr5cpyBR0NXunxnx14opDdpnmJREGzQuwyXMu+FEvepyYNFU0Qu/a5 ArCLErlsyUcuB5kCUc3FoLyfkvK+SINHJ+HunqIggJQ5IRO9e/f4kCmoNwXyLjvBVHbY wOBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754663; x=1688346663; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NU+ycyGnxu88uw+EwETUIF4qNqsYgJat1S24XSYVjxU=; b=NtqzSJtAaorrV9x58KYzLo6Jm9kw9QPVvgTu4FXKlUW88Sv8NQlv/OIkSdDxGdDFq9 snwWtu29g11x5s1nAkILhb1gJ3VgpxAPAudnHcieW4DBBLspKXw8fCTrLBTpRe0xK9Fv 5cRe5DkAcU75o6IdUyIw3+Nd+fahatxDCS+gIBZq9AIjvLwny0xNR/ktNozyG6nrD0nz a4RZTzx2t/SNxEh6Uy8QtPHQDg6HhkpxNk4k6SBxZqDsMfzBfLJdkFcOQ7Ijo2WvPJg0 IwC35DvrfyNemqND1bUo8VawFOAsK3LBRKmrevIlumrf2hbhXPWYH0nQoPy/nxAZMQn5 jA+Q== X-Gm-Message-State: AC+VfDx2i4iSKzenxopoHrAAQxEzu88Cyj5JZ2U1Etq2mbraaqOfoyuU I1CWb0Um6rTWg/PpSu2+qKBBN/kwki0= X-Google-Smtp-Source: ACHHUZ790PdH3Eci3gX3EL755X3qEWX8Az2bLyIOmZK6vS3ODTcxHS/0JC9dmzaYgl8W1LDU93utrGQgqvU= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90b:394e:b0:256:2192:2c58 with SMTP id oe14-20020a17090b394e00b0025621922c58mr312633pjb.4.1685754663465; Fri, 02 Jun 2023 18:11:03 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:47 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-2-seanjc@google.com> Subject: [PATCH v7 01/12] KVM: x86/pmu: Rename global_ovf_ctrl_mask to global_status_mask From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Rename global_ovf_ctrl_mask to global_status_mask to avoid confusion now that Intel has renamed GLOBAL_OVF_CTRL to GLOBAL_STATUS_RESET in PMU v4. GLOBAL_OVF_CTRL and GLOBAL_STATUS_RESET are the same MSR index, i.e. are just different names for the same thing, but the SDM provides different entries in the IA-32 Architectural MSRs table, which gets really confusing when looking at PMU v4 definitions since it *looks* like GLOBAL_STATUS has bits that don't exist in GLOBAL_OVF_CTRL, but in reality the bits are simply defined in the GLOBAL_STATUS_RESET entry. No functional change intended. Cc: Like Xu Signed-off-by: Sean Christopherson --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index fb9d1f2d6136..28bd38303d70 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -523,7 +523,7 @@ struct kvm_pmu { u64 global_status; u64 counter_bitmask[2]; u64 global_ctrl_mask; - u64 global_ovf_ctrl_mask; + u64 global_status_mask; u64 reserved_bits; u64 raw_event_mask; struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC]; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 741efe2c497b..fb96cbfc9ae8 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -427,7 +427,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) } break; case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - if (data & pmu->global_ovf_ctrl_mask) + /* + * GLOBAL_OVF_CTRL, a.k.a. GLOBAL STATUS_RESET, clears bits in + * GLOBAL_STATUS, and so the set of reserved bits is the same. + */ + if (data & pmu->global_status_mask) return 1; if (!msr_info->host_initiated) @@ -531,7 +535,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->reserved_bits = 0xffffffff00200000ull; pmu->raw_event_mask = X86_RAW_EVENT_MASK; pmu->global_ctrl_mask = ~0ull; - pmu->global_ovf_ctrl_mask = ~0ull; + pmu->global_status_mask = ~0ull; pmu->fixed_ctr_ctrl_mask = ~0ull; pmu->pebs_enable_mask = ~0ull; pmu->pebs_data_cfg_mask = ~0ull; @@ -585,11 +589,17 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) counter_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) | (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED)); pmu->global_ctrl_mask = counter_mask; - pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask + + /* + * GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET) + * share reserved bit definitions. The kernel just happens to use + * OVF_CTRL for the names. + */ + pmu->global_status_mask = pmu->global_ctrl_mask & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF | MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD); if (vmx_pt_mode_is_host_guest()) - pmu->global_ovf_ctrl_mask &= + pmu->global_status_mask &= ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI; entry = kvm_find_cpuid_entry_index(vcpu, 7, 0); From patchwork Sat Jun 3 01:10:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265978 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 312D7C7EE2D for ; Sat, 3 Jun 2023 01:11:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237065AbjFCBLL (ORCPT ); Fri, 2 Jun 2023 21:11:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236989AbjFCBLI (ORCPT ); Fri, 2 Jun 2023 21:11:08 -0400 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14FC6B9 for ; Fri, 2 Jun 2023 18:11:06 -0700 (PDT) Received: by mail-pf1-x449.google.com with SMTP id d2e1a72fcca58-6537ff2c93fso424237b3a.2 for ; Fri, 02 Jun 2023 18:11:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754665; x=1688346665; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=zNS+2nUop8HSFhXhjGUsYHrKCz8noRLlXBPZS+z46QI=; b=zD9YgFffhnt58QHSD5hvMYuW98to2PwClt4O7Q5PboHoKYWMUYyrdJRIsO9wOabfrO wbIZ5xULWSadmjrlN0rX9UFk2OB96dKBbdLaudCvmoJUFEPojXphaikBq7HlrEo3Kc5B QUHmKGIPRHLHv+D2zzZVmj1V0GVVepFaZoJ1hUx+xFhXca0H1VaovUViPyU9u0WHtLnr TdbtyI2knorbbWKSj9JxzoWVtBh+3XM8xmV76f/l0Q6XIsMGRTSKTKF5r89qp9DiGQ4t q2hhevSK8TfoK8BDjKnq3gso1vshT8TMMUSvzYuPlEjNAJWuzxrT+i+LXQUOhHHhx5cP f8tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754665; x=1688346665; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=zNS+2nUop8HSFhXhjGUsYHrKCz8noRLlXBPZS+z46QI=; b=WjQ66ihUj2B7JBuBxr0+KRSj0Xa6U3ka7joIvOruO4i4GCu6NEj/XKqNTZS9aOkGCQ ZCwtGsodUh8PptPclOkrG6KoaRd5mzAxFftlZF/ZnsrsK7arXwpWHp89dUyFwEnJq1vH LZMZenGkzb+ocxFeMtmNCjs3vDLC6gQewnxwmbCcRv0aGQJfhZEwKDvxQJcUHtJEcLhD Xlc3dHYJ5JAPMu494T+x0O+aON7G7I0CYDAkCLNCZozbgycRR/3HHvCxrzuudmbikH93 fxrAfl9BeyTMixZxq5zIrTNa2Dy4N715bqG0WOBOmdbUEL8jaNdSG0uqZoOGqaTXpeFg ILEg== X-Gm-Message-State: AC+VfDwVJCqzKIClIp6aO14UDzBEZziTfwjObHLXgwffqFd3PVx8pzIW VBvL4n/BvgOGTkMzR0Y8B8LbkuXt1dU= X-Google-Smtp-Source: ACHHUZ66VR1ERObfdJKcvipVCvg4VTNcwOGsEvlE1HEOn8bBw52eibfHaJuuXnFKXKd+qxws+6C6rP9MTXk= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6a00:2e0e:b0:647:3f80:c607 with SMTP id fc14-20020a056a002e0e00b006473f80c607mr5051252pfb.4.1685754665454; Fri, 02 Jun 2023 18:11:05 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:48 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-3-seanjc@google.com> Subject: [PATCH v7 02/12] KVM: x86/pmu: Move reprogram_counters() to pmu.h From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Move reprogram_counters() out of Intel specific PMU code and into pmu.h so that it can be used to implement AMD PMU v2 support. No functional change intended. Suggested-by: Sean Christopherson Signed-off-by: Like Xu [sean: rewrite changelog] Signed-off-by: Sean Christopherson --- arch/x86/kvm/pmu.h | 12 ++++++++++++ arch/x86/kvm/vmx/pmu_intel.c | 12 ------------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 5c7bbf03b599..986563aeeef8 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -201,6 +201,18 @@ static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) kvm_make_request(KVM_REQ_PMU, pmc->vcpu); } +static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff) +{ + int bit; + + if (!diff) + return; + + for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) + set_bit(bit, pmu->reprogram_pmi); + kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index fb96cbfc9ae8..edcf8670eb4e 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -73,18 +73,6 @@ static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx) } } -static void reprogram_counters(struct kvm_pmu *pmu, u64 diff) -{ - int bit; - - if (!diff) - return; - - for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) - set_bit(bit, pmu->reprogram_pmi); - kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); -} - static bool intel_hw_event_available(struct kvm_pmc *pmc) { struct kvm_pmu *pmu = pmc_to_pmu(pmc); From patchwork Sat Jun 3 01:10:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 208B1C77B7A for ; Sat, 3 Jun 2023 01:11:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237106AbjFCBLV (ORCPT ); Fri, 2 Jun 2023 21:11:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236989AbjFCBLP (ORCPT ); Fri, 2 Jun 2023 21:11:15 -0400 Received: from mail-oi1-x24a.google.com (mail-oi1-x24a.google.com [IPv6:2607:f8b0:4864:20::24a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AC7BE4C for ; Fri, 2 Jun 2023 18:11:08 -0700 (PDT) Received: by mail-oi1-x24a.google.com with SMTP id 5614622812f47-397f122786fso2224969b6e.1 for ; Fri, 02 Jun 2023 18:11:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754667; x=1688346667; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=OHgmCWhsFgWWc85nvi+clBbGRI79fcIkNTIgsGqvymM=; b=rlxDfPJjRdF2a+2a8IL9CQM3ryLHp/fQFGIDzVWEwkAjbu3rsh9eN4/R438auoMsLx irdotbBF0L1VqKT7sLdHg3PikykqWcUlNX6wVlhaUAfH5PKTV+UUR+TyBafKzG8MjC4E tp1WnkLmqwfZvQaRXg6jlLso8YEnv2L36GuDh8uar0YoEOeMWHsovwHhs2G9+A+3kHmr V/qpzImsl5mxJI5ns7EKgEttGZ561aBmdHz/ppbAqpuZmX8j8rgPc/m4SgD+T641muzY vWeaDVcIuFit0C86mc8OyyT6Pgkn1zccHXMcLo0+BpC9MFyGHv6tOIf9BOGgQIFhgJGx UvHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754667; x=1688346667; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=OHgmCWhsFgWWc85nvi+clBbGRI79fcIkNTIgsGqvymM=; b=bNyW6JWT4McGX68cFfQGHWQtIoBHCqRKEpbmg0LNXFkcd60O920FnqQytWKF9xWOGz r3FbKfDmstfvV5Ti1S27B8rdZIM8jzsFopF3Wcgfq1d7hydQ7YxLJBj8HmSz7MQYkJsL BHAsEg1SCzW+dna5JO4NbQmsGBGrZa2kYJiKTxdPhCD1/IKXCAtalpKFtg+KrRVzavX7 Km8jetgvDafAJf+QQYu6mev9vBS+iN6qaXxwX+4pcVzDQlQ7fO8l6ZsgsvxWloibAMnZ quYSBJgjWyg6Ig6aVur5CpH/gAiCE3GA7oYq1g4F1g2OI3KOf1pVd2+KpcIerrrIcnnb XHrQ== X-Gm-Message-State: AC+VfDwXZUbQoMoNhEsb63TiIASJobSd7OoINp3r/qxb85J/FCLswPvO WH7HT3fKQ5nvrLMvGm/8CY+59d5mkd4= X-Google-Smtp-Source: ACHHUZ7fj12g6vQgJPTgDrxbgsW/k0ZxqGChmghKukBdZMacw+XVprDLohrghb7z31IURsAjBSVpN4gjegg= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:aca:a888:0:b0:399:ee8f:6cdc with SMTP id r130-20020acaa888000000b00399ee8f6cdcmr341691oie.9.1685754667468; Fri, 02 Jun 2023 18:11:07 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:49 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-4-seanjc@google.com> Subject: [PATCH v7 03/12] KVM: x86/pmu: Reject userspace attempts to set reserved GLOBAL_STATUS bits From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Reject userspace writes to MSR_CORE_PERF_GLOBAL_STATUS that attempt to set reserved bits. Allowing userspace to stuff reserved bits doesn't harm KVM itself, but it's architecturally wrong and the guest can't clear the unsupported bits, e.g. makes the guest's PMI handler very confused. Signed-off-by: Like Xu [sean: rewrite changelog to avoid use of #GP, rebase on name change] Signed-off-by: Sean Christopherson --- arch/x86/kvm/vmx/pmu_intel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index edcf8670eb4e..efd113f24c1b 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -402,6 +402,9 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (!msr_info->host_initiated) return 1; /* RO MSR */ + if (data & pmu->global_status_mask) + return 1; + pmu->global_status = data; break; case MSR_CORE_PERF_GLOBAL_CTRL: From patchwork Sat Jun 3 01:10:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FFAAC77B7A for ; Sat, 3 Jun 2023 01:11:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237087AbjFCBLR (ORCPT ); Fri, 2 Jun 2023 21:11:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237064AbjFCBLK (ORCPT ); Fri, 2 Jun 2023 21:11:10 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54D8DB9 for ; Fri, 2 Jun 2023 18:11:09 -0700 (PDT) Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-2553b096ddfso2387507a91.1 for ; Fri, 02 Jun 2023 18:11:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754669; x=1688346669; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=swEcMgjVxKvw1b5Bf6E2j3Zu7xMBEr/QXOoV0DUFx6c=; b=vql83tzz8Nv6CwSsZWAIWzRxPyJ4JmBNCY+I8T31VQtwJ3ApMXLSmkUmWeesDkcEng tgjPq6G53Bb69bCGwixT7FFAw7ypzpUPiqupkbpz8nBTmWyIh4pnI1RAW6dZ+htcw+IM fLkm5YZHz6oA/IvaRUEyWkIi29Kwdf/bBotQDYy+z+kHAdCv4p/S+piL343KvO5ii61N UiMsju2/61shtM2gy4fg/jDR38oGWFscLBhhz8e4wd4O8I7kxHE2r+Wo0z1fsvH3aN91 fwytyIybOf6rDlQ1Afqb9BT+pqgaGCbTFbQz41m+5pPkxM8sxn/o09rzphrQAv5ZVgjd 4K+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754669; x=1688346669; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=swEcMgjVxKvw1b5Bf6E2j3Zu7xMBEr/QXOoV0DUFx6c=; b=ZdrbEUX1bbMhIGpbsVYwKhuwb8J0/FeHBlNMoKFuHQJbvPkHBR1WNY4XsDSiMN8HeP FMzzQAIt6a9zCREFrLRpTRBoMDt1PlRyx2c0t4L+m+KuUImHZ7aOtBONVUUnn2DC+Kp9 GcW9fLz/9PDRve3Qnm7sUsv1Vvybvji3N8pYrhrKJFZiS6n0qBDfr99VQYHG2NFN3EbY NXQI9MmgCWvb/SAxXWhGe3BFa5e+BB5Z95vlZcMNJf375lk+TpboblJ/8NZmA8jhOn5x zjqfwSXX89KpictF0OAkKdEwkqHBhsv2PdwueJPuKighpcqRXkZ7jHbIFRWQZ0RDsfPD 63TA== X-Gm-Message-State: AC+VfDw34sOXuA9S3Rup6NBtDq86tFIw9Xop0xdia5Gq78WLPN1RJ+WN 5ydaomU6zbT9IKZRRy01JWKKQr+3DEY= X-Google-Smtp-Source: ACHHUZ70p7wq6NQEoxnxEnQSJY6ePLYxl303VkojN4lsCoDxiKggcGzVH00pnhDKkQO/g20AINPrfjFAI50= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:90a:e2cb:b0:256:bc5e:7d76 with SMTP id fr11-20020a17090ae2cb00b00256bc5e7d76mr313305pjb.3.1685754669034; Fri, 02 Jun 2023 18:11:09 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:50 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-5-seanjc@google.com> Subject: [PATCH v7 04/12] KVM: x86/pmu: Move handling PERF_GLOBAL_CTRL and friends to common x86 From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Move the handling of GLOBAL_CTRL, GLOBAL_STATUS, and GLOBAL_OVF_CTRL, a.k.a. GLOBAL_STATUS_RESET, from Intel PMU code to generic x86 PMU code. AMD PerfMonV2 defines three registers that have the same semantics as Intel's variants, just with different names and indices. Conveniently, since KVM virtualizes GLOBAL_CTRL on Intel only for PMU v2 and above, and AMD's version shows up in v2, KVM can use common code for the existence check as well. Signed-off-by: Like Xu Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- arch/x86/kvm/pmu.c | 71 ++++++++++++++++++++++++++++++++++-- arch/x86/kvm/pmu.h | 14 +++++++ arch/x86/kvm/vmx/nested.c | 4 +- arch/x86/kvm/vmx/pmu_intel.c | 47 +----------------------- arch/x86/kvm/vmx/vmx.h | 12 ------ 5 files changed, 86 insertions(+), 62 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 1690d41c1830..c720cc186ab4 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -562,6 +562,14 @@ void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu) bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) { + switch (msr) { + case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_CORE_PERF_GLOBAL_CTRL: + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + return kvm_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu)); + default: + break; + } return static_call(kvm_x86_pmu_msr_idx_to_pmc)(vcpu, msr) || static_call(kvm_x86_pmu_is_valid_msr)(vcpu, msr); } @@ -577,13 +585,70 @@ static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr) int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { - return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info); + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + u32 msr = msr_info->index; + + switch (msr) { + case MSR_CORE_PERF_GLOBAL_STATUS: + msr_info->data = pmu->global_status; + break; + case MSR_CORE_PERF_GLOBAL_CTRL: + msr_info->data = pmu->global_ctrl; + break; + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + msr_info->data = 0; + break; + default: + return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info); + } + + return 0; } int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { - kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); - return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info); + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + u32 msr = msr_info->index; + u64 data = msr_info->data; + u64 diff; + + switch (msr) { + case MSR_CORE_PERF_GLOBAL_STATUS: + if (!msr_info->host_initiated) + return 1; /* RO MSR */ + + if (data & pmu->global_status_mask) + return 1; + + pmu->global_status = data; + break; + case MSR_CORE_PERF_GLOBAL_CTRL: + if (!kvm_valid_perf_global_ctrl(pmu, data)) + return 1; + + if (pmu->global_ctrl != data) { + diff = pmu->global_ctrl ^ data; + pmu->global_ctrl = data; + reprogram_counters(pmu, diff); + } + break; + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + /* + * GLOBAL_OVF_CTRL, a.k.a. GLOBAL STATUS_RESET, clears bits in + * GLOBAL_STATUS, and so the set of reserved bits is the same. + */ + if (data & pmu->global_status_mask) + return 1; + + if (!msr_info->host_initiated) + pmu->global_status &= ~data; + break; + default: + kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); + return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info); + } + + return 0; } /* refresh PMU settings. This function generally is called when underlying diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 986563aeeef8..7c2c64142443 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -41,6 +41,20 @@ struct kvm_pmu_ops { void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops); +static inline bool kvm_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu) +{ + /* + * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is + * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is + * greater than zero. However, KVM only exposes and emulates the MSR + * to/for the guest if the guest PMU supports at least "Architectural + * Performance Monitoring Version 2". + * + * AMD's version of PERF_GLOBAL_CTRL conveniently shows up with v2. + */ + return pmu->version > 1; +} + static inline u64 pmc_bitmask(struct kvm_pmc *pmc) { struct kvm_pmu *pmu = pmc_to_pmu(pmc); diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index e35cf0bd0df9..ba2ed6d87364 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -2649,7 +2649,7 @@ static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, } if ((vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) && - intel_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu)) && + kvm_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu)) && WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, vmcs12->guest_ia32_perf_global_ctrl))) { *entry_failure_code = ENTRY_FAIL_DEFAULT; @@ -4524,7 +4524,7 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu, vcpu->arch.pat = vmcs12->host_ia32_pat; } if ((vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) && - intel_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu))) + kvm_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu))) WARN_ON_ONCE(kvm_set_msr(vcpu, MSR_CORE_PERF_GLOBAL_CTRL, vmcs12->host_ia32_perf_global_ctrl)); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index efd113f24c1b..ff2f52d1e22f 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -100,7 +100,7 @@ static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) { struct kvm_pmu *pmu = pmc_to_pmu(pmc); - if (!intel_pmu_has_perf_global_ctrl(pmu)) + if (!kvm_pmu_has_perf_global_ctrl(pmu)) return true; return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); @@ -186,11 +186,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) switch (msr) { case MSR_CORE_PERF_FIXED_CTR_CTRL: - case MSR_CORE_PERF_GLOBAL_STATUS: - case MSR_CORE_PERF_GLOBAL_CTRL: - case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - return intel_pmu_has_perf_global_ctrl(pmu); - break; + return kvm_pmu_has_perf_global_ctrl(pmu); case MSR_IA32_PEBS_ENABLE: ret = vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; break; @@ -340,15 +336,6 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_CORE_PERF_FIXED_CTR_CTRL: msr_info->data = pmu->fixed_ctr_ctrl; break; - case MSR_CORE_PERF_GLOBAL_STATUS: - msr_info->data = pmu->global_status; - break; - case MSR_CORE_PERF_GLOBAL_CTRL: - msr_info->data = pmu->global_ctrl; - break; - case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - msr_info->data = 0; - break; case MSR_IA32_PEBS_ENABLE: msr_info->data = pmu->pebs_enable; break; @@ -398,36 +385,6 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) if (pmu->fixed_ctr_ctrl != data) reprogram_fixed_counters(pmu, data); break; - case MSR_CORE_PERF_GLOBAL_STATUS: - if (!msr_info->host_initiated) - return 1; /* RO MSR */ - - if (data & pmu->global_status_mask) - return 1; - - pmu->global_status = data; - break; - case MSR_CORE_PERF_GLOBAL_CTRL: - if (!kvm_valid_perf_global_ctrl(pmu, data)) - return 1; - - if (pmu->global_ctrl != data) { - diff = pmu->global_ctrl ^ data; - pmu->global_ctrl = data; - reprogram_counters(pmu, diff); - } - break; - case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - /* - * GLOBAL_OVF_CTRL, a.k.a. GLOBAL STATUS_RESET, clears bits in - * GLOBAL_STATUS, and so the set of reserved bits is the same. - */ - if (data & pmu->global_status_mask) - return 1; - - if (!msr_info->host_initiated) - pmu->global_status &= ~data; - break; case MSR_IA32_PEBS_ENABLE: if (data & pmu->pebs_enable_mask) return 1; diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 9e66531861cf..32384ba38499 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -93,18 +93,6 @@ union vmx_exit_reason { u32 full; }; -static inline bool intel_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu) -{ - /* - * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is - * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is - * greater than zero. However, KVM only exposes and emulates the MSR - * to/for the guest if the guest PMU supports at least "Architectural - * Performance Monitoring Version 2". - */ - return pmu->version > 1; -} - struct lbr_desc { /* Basic info about guest LBR records. */ struct x86_pmu_lbr records; From patchwork Sat Jun 3 01:10:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E265AC77B7A for ; Sat, 3 Jun 2023 01:11:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237132AbjFCBL2 (ORCPT ); Fri, 2 Jun 2023 21:11:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237081AbjFCBLP (ORCPT ); Fri, 2 Jun 2023 21:11:15 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE1EFE50 for ; Fri, 2 Jun 2023 18:11:11 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-ba8337a5861so6200272276.0 for ; Fri, 02 Jun 2023 18:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754671; x=1688346671; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=miuZ/wWNZFN7b1zXGKrPaL8HShf8kZjo9bpVR4m4UMo=; b=UgbLBc4fVtdWOUVtfm4nNyElNGayvvDDwY1KZMzt8nVX6GVH2B0GkwmSdQLH0D0kpW YNLrpedmHG9B+WwhIofgdE7jwof0BDUmIwklc/1oXmfGXb4i33rurcbzJVOgeXGrUR1Y /QlyqKdfSOMKR733tzhsKRqj9yoYXSWmjcGCvM5gmyC0gFSfM9wp6BMcPpuJO5HqOffZ WfYaOc6IrQ5PJ/R54pSb/++xbxHNIgpQnDzhmdTTNFs2OWRjET9UMOJ+KuZJyZe0AjwL 4Myx6cVXEuQUOvcvf/xBBruUdiequrkT/o54W/u+olHnOv66G1hdmZiiXbSkELmh3Vvk PMCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754671; x=1688346671; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=miuZ/wWNZFN7b1zXGKrPaL8HShf8kZjo9bpVR4m4UMo=; b=T1zV8tr+luy9QbS142+XbeAvZ8iMX9/I6GPiPUS1uN2PgefjybbQwXz7hSyEbuRMoe RLuFJ+63G8ZA+15wdUaqck5o9QS4ebGZiGgnU5tER7qBC2CweWpetwRR0PtEOkZSYk0P CRc/WBFap6SKBbWDHAkV5RKRwJqUZufD1+OUisGMXEDF9TNrpJRv6hSDPMxtDFFBGUQ6 Fjeg4dXQqfu1ukTayswU3gxCMIsDH+XC+rZOIMclbnq/9qOVLrUsplb6Fg2M7YOAVeZz mLVBKdFF8Ie3yB2oxOvaEif7ztRGp2GkSOTrv8O6OaNlI/wfoheYqFc3Zpyt2MjbOaZY BYdw== X-Gm-Message-State: AC+VfDzXQdWXzmxFlezhf2b5gb78PHK7ddoYBXBrFHkjGgTU3UgKWt8v Ed+vi77f8DHV//eVbmcz1v7r1aFRu/k= X-Google-Smtp-Source: ACHHUZ4NXGHPKErIR2VubFeyjDpxmVj0sNjMQFrGfjVgY8rD6PU4Ts/23SzEIduMQVBpzgkBF53LXC+6WW0= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:1003:b0:ba8:1e5f:8514 with SMTP id w3-20020a056902100300b00ba81e5f8514mr3214688ybt.5.1685754671139; Fri, 02 Jun 2023 18:11:11 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:51 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-6-seanjc@google.com> Subject: [PATCH v7 05/12] KVM: x86/pmu: Provide Intel PMU's pmc_is_enabled() as generic x86 code From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Move the Intel PMU implementation of pmc_is_enabled() to common x86 code as pmc_is_globally_enabled(), and drop AMD's implementation. AMD PMU currently supports only v1, and thus not PERF_GLOBAL_CONTROL, thus the semantics for AMD are unchanged. And when support for AMD PMU v2 comes along, the common behavior will also Just Work. Signed-off-by: Like Xu Co-developed-by: Sean Christopherson Signed-off-by: Sean Christopherson --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 - arch/x86/kvm/pmu.c | 5 ----- arch/x86/kvm/pmu.h | 16 +++++++++++++++- arch/x86/kvm/svm/pmu.c | 9 --------- arch/x86/kvm/vmx/pmu_intel.c | 14 +------------- 5 files changed, 16 insertions(+), 29 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/kvm-x86-pmu-ops.h index c17e3e96fc1d..6c98f4bb4228 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -13,7 +13,6 @@ BUILD_BUG_ON(1) * at the call sites. */ KVM_X86_PMU_OP(hw_event_available) -KVM_X86_PMU_OP(pmc_is_enabled) KVM_X86_PMU_OP(pmc_idx_to_pmc) KVM_X86_PMU_OP(rdpmc_ecx_to_pmc) KVM_X86_PMU_OP(msr_idx_to_pmc) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index c720cc186ab4..4315f46aabfb 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -93,11 +93,6 @@ void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops) #undef __KVM_X86_PMU_OP } -static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) -{ - return static_call(kvm_x86_pmu_pmc_is_enabled)(pmc); -} - static void kvm_pmi_trigger_fn(struct irq_work *irq_work) { struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work); diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 7c2c64142443..f77bfc7ede42 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -20,7 +20,6 @@ struct kvm_pmu_ops { bool (*hw_event_available)(struct kvm_pmc *pmc); - bool (*pmc_is_enabled)(struct kvm_pmc *pmc); struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, unsigned int idx, u64 *mask); @@ -227,6 +226,21 @@ static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff) kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); } +/* + * Check if a PMC is enabled by comparing it against global_ctrl bits. + * + * If the vPMU doesn't have global_ctrl MSR, all vPMCs are enabled. + */ +static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) +{ + struct kvm_pmu *pmu = pmc_to_pmu(pmc); + + if (!kvm_pmu_has_perf_global_ctrl(pmu)) + return true; + + return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 5fa939e411d8..70143275e0a7 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -78,14 +78,6 @@ static bool amd_hw_event_available(struct kvm_pmc *pmc) return true; } -/* check if a PMC is enabled by comparing it against global_ctrl bits. Because - * AMD CPU doesn't have global_ctrl MSR, all PMCs are enabled (return TRUE). - */ -static bool amd_pmc_is_enabled(struct kvm_pmc *pmc) -{ - return true; -} - static bool amd_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -220,7 +212,6 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) struct kvm_pmu_ops amd_pmu_ops __initdata = { .hw_event_available = amd_hw_event_available, - .pmc_is_enabled = amd_pmc_is_enabled, .pmc_idx_to_pmc = amd_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc, .msr_idx_to_pmc = amd_msr_idx_to_pmc, diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index ff2f52d1e22f..b2f279f934b1 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -95,17 +95,6 @@ static bool intel_hw_event_available(struct kvm_pmc *pmc) return true; } -/* check if a PMC is enabled by comparing it with globl_ctrl bits. */ -static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) -{ - struct kvm_pmu *pmu = pmc_to_pmu(pmc); - - if (!kvm_pmu_has_perf_global_ctrl(pmu)) - return true; - - return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); -} - static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -759,7 +748,7 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) pmc = intel_pmc_idx_to_pmc(pmu, bit); if (!pmc || !pmc_speculative_in_use(pmc) || - !intel_pmc_is_enabled(pmc) || !pmc->perf_event) + !pmc_is_globally_enabled(pmc) || !pmc->perf_event) continue; /* @@ -774,7 +763,6 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) struct kvm_pmu_ops intel_pmu_ops __initdata = { .hw_event_available = intel_hw_event_available, - .pmc_is_enabled = intel_pmc_is_enabled, .pmc_idx_to_pmc = intel_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc, .msr_idx_to_pmc = intel_msr_idx_to_pmc, From patchwork Sat Jun 3 01:10:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5409C7EE2D for ; Sat, 3 Jun 2023 01:11:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237161AbjFCBLa (ORCPT ); Fri, 2 Jun 2023 21:11:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237094AbjFCBLT (ORCPT ); Fri, 2 Jun 2023 21:11:19 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76903E58 for ; Fri, 2 Jun 2023 18:11:13 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-ba87bd29e9dso3437079276.3 for ; Fri, 02 Jun 2023 18:11:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754672; x=1688346672; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=TY+mHBGwLnRemiSJpkessBMR8rKQ3vloA3kicsPHpfA=; b=OnCY01X+GhNF4B2rPl8w92fKWWhN75yMAb8AqNhGWytXTk7TqUGYHT4OfJ96dUILgN E0bsOfYhf01+Inn8Hb6VeZ6WNJw2DFAiK2w3enJaLGHRu43Ky7Gx3hZn8pD39bwy0Gws Pad3T+POsq3NcQF2v5vfXQsnEM4TUIUlQkztXz65WFLxy4JlqanGy6UfX758JWeLDd4M KcaCut6eaMR2T4teMNKH2Z05voP9MFb0ztfhUx3byu1XA+0QDhHk70OGTH4ztvcGvRvU rLn4EKN+VlU6cICCZ1x7EZaZZD7BlmE2FecwXrKWJaYtOzJOWSJUNogS5FyzwctEfSC8 u+nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754672; x=1688346672; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=TY+mHBGwLnRemiSJpkessBMR8rKQ3vloA3kicsPHpfA=; b=bf9Vcn//aNsxTtBsDNfBWz6P/KEZuXZ5YbyaT6HsB3aNTgKCJejZO1PX12WRHT/qkS 5cQMnxukpBJQyLbwNjEUqR/tFZ0vUZGkQ6jycykEmdZIQSyE+fuUbP5xlfFP/BmgEY1Y 2vz7utLenO068M7E7BPtEQwlwPIs2zCaw37zj1goAc9uwI3Zm0RQBrZHfYa4GaYdsaJp OEcp0Z4WKXzspYZGAtt+yYYJJJxmNT3jrD7Xsd+xLYOvMPZINlRilQB62Q8kNwOpq1lu J80OKvD1+KpIhBK1yyNQP82qC/PDl12dc2baWzEd6HEHfvRUBNPTsyklMfI/XoZF0APM cKLA== X-Gm-Message-State: AC+VfDwxsAkfPhqCEJZko0sXJbHRdsPZPom7FKZSfpdyNeY9WGzZJYiC 7qPnyzlhT5KkkRnUGiE1pmSR/bCH6BM= X-Google-Smtp-Source: ACHHUZ71ab2vlYdbFm7muMp7lZeJGYFIK9nlaLC/YaAwP+jTh+T1gLgrwoU8lFKVlrgSzxu0x8mqtLJ90yw= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:1142:b0:bac:fd63:b567 with SMTP id p2-20020a056902114200b00bacfd63b567mr2769901ybu.4.1685754672783; Fri, 02 Jun 2023 18:11:12 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:52 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-7-seanjc@google.com> Subject: [PATCH v7 06/12] KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Add an explicit !enable_pmu check as relying on kvm_pmu_cap to be zeroed isn't obvious. Although when !enable_pmu, KVM will have zero-padded kvm_pmu_cap to do subsequent CPUID leaf assignments. Suggested-by: Sean Christopherson Signed-off-by: Like Xu Signed-off-by: Sean Christopherson --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 0c9660a07b23..61bc71882f07 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -948,7 +948,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) union cpuid10_eax eax; union cpuid10_edx edx; - if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { + if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { entry->eax = entry->ebx = entry->ecx = entry->edx = 0; break; } From patchwork Sat Jun 3 01:10:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265984 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6B05C77B7A for ; Sat, 3 Jun 2023 01:11:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237114AbjFCBLd (ORCPT ); Fri, 2 Jun 2023 21:11:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237079AbjFCBL1 (ORCPT ); Fri, 2 Jun 2023 21:11:27 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39526E62 for ; Fri, 2 Jun 2023 18:11:15 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id d2e1a72fcca58-6540e7d7db6so182591b3a.1 for ; Fri, 02 Jun 2023 18:11:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754674; x=1688346674; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=zr+/pnb/J2jPCGA1Q1JKmqMm9BtDe3UI/Uh5NJfZaa0=; b=W6Vz7Xw1rbw0gXa2rsXOXRYx9YEGjz4vKv2uzqozbUhgFxNAOk9kfVUKB+AJhWcN1+ wpQ10OmxsNP3yWnjcyC5p/scv4pyLFvcBHi84A9pe5DlHO4mJ5iGsQq1dqopovSnEPOy Q2Xrpm+0Eq/hvEM14iRld1pFqKnm3BTumBvvyN8vXrGGOcc7oROUj7Rb9zFvKW9IGUvV zBfimPAEhr8ADG+4l6OPTeJCAqSqDk1j6r6HTLtlUBDDA4eoV6a5wjWZJS/adiuARAqD 2bJ1Iqhfq7vcWI3RPYcQypDU5RfldmC+YlfMFwI5OcU2Fc7YfxJStT/9auzVNgKIiuqc NHHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754674; x=1688346674; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=zr+/pnb/J2jPCGA1Q1JKmqMm9BtDe3UI/Uh5NJfZaa0=; b=VVMB3Z6weLX1Jc7d45OF5h7TRjUr/wXeH03uhO4C0ojmWpsadgOXrkub5g/Zfv0ZXY AUg11J/8+X+WBjPPkc0j3+9PAkkY2fS5CxSlHDha0Kg6BufLRaUxShrit5/Mj8j/K0hR XpL9EMWAxbC9pPtZUtVERt8TKJt7ba6fFbyLXT6GhccHxCGH9XliuEX4ivflETM4fdP0 05DxO8GA0M15rFhzAdmFyfbHGfD9EoI2D6z1Nvq2tOOx8OOHr5oZTaBBQmVGUDjI5p3E yV6Y6D4FMsAJE2AhPpHGw8lRMMwKRRn6A7gDrNyVC3KjnIxpWYb4uWlqL6bXI+xxlA5Z 86Sw== X-Gm-Message-State: AC+VfDzqeb/Ei+zr8WYoDvzj2+GJVNq/XtA3SfEilQME34nRoQ3OjEn+ E4IZ/sp+4T20W3i2RAKHGbYfr+5KwhE= X-Google-Smtp-Source: ACHHUZ5XAS8BSRnTJQzXlIkYsfeCLg9EJh+dmhJjUP7A+EonEwCcxy3lNQoPjRXB0ILz1JUba+A4Ih51Ml0= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a63:495f:0:b0:53f:7713:5e0e with SMTP id y31-20020a63495f000000b0053f77135e0emr2571629pgk.5.1685754674630; Fri, 02 Jun 2023 18:11:14 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:53 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-8-seanjc@google.com> Subject: [PATCH v7 07/12] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Disable PMU support when running on AMD and perf reports fewer than four general purpose counters. All AMD PMUs must define at least four counters due to AMD's legacy architecture hardcoding the number of counters without providing a way to enumerate the number of counters to software, e.g. from AMD's APM: The legacy architecture defines four performance counters (PerfCtrn) and corresponding event-select registers (PerfEvtSeln). Virtualizing fewer than four counters can lead to guest instability as software expects four counters to be available. Rather than bleed AMD details into the common code, just define a const unsigned int and provide a convenient location to document why Intel and AMD have different mins (in particular, AMD's lack of any way to enumerate less than four counters to the guest). Keep the minimum number of counters at Intel at one, even though old P6 and Core Solo/Duo processor effectively require a minimum of two counters. KVM can, and more importantly has up until this point, supported a vPMU so long as the CPU has at least one counter. Perf's support for P6/Core CPUs does require two counters, but perf will happily chug along with a single counter when running on a modern CPU. Cc: Jim Mattson Suggested-by: Sean Christopherson Signed-off-by: Like Xu [sean: set Intel min to '1', not '2'] Signed-off-by: Sean Christopherson --- arch/x86/kvm/pmu.h | 14 ++++++++++---- arch/x86/kvm/svm/pmu.c | 1 + arch/x86/kvm/vmx/pmu_intel.c | 1 + 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index f77bfc7ede42..7d9ba301c090 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -36,6 +36,7 @@ struct kvm_pmu_ops { const u64 EVENTSEL_EVENT; const int MAX_NR_GP_COUNTERS; + const int MIN_NR_GP_COUNTERS; }; void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops); @@ -174,6 +175,7 @@ extern struct x86_pmu_capability kvm_pmu_cap; static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops) { bool is_intel = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL; + int min_nr_gp_ctrs = pmu_ops->MIN_NR_GP_COUNTERS; /* * Hybrid PMUs don't play nice with virtualization without careful @@ -188,11 +190,15 @@ static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops) perf_get_x86_pmu_capability(&kvm_pmu_cap); /* - * For Intel, only support guest architectural pmu - * on a host with architectural pmu. + * WARN if perf did NOT disable hardware PMU if the number of + * architecturally required GP counters aren't present, i.e. if + * there are a non-zero number of counters, but fewer than what + * is architecturally required. */ - if ((is_intel && !kvm_pmu_cap.version) || - !kvm_pmu_cap.num_counters_gp) + if (!kvm_pmu_cap.num_counters_gp || + WARN_ON_ONCE(kvm_pmu_cap.num_counters_gp < min_nr_gp_ctrs)) + enable_pmu = false; + else if (is_intel && !kvm_pmu_cap.version) enable_pmu = false; } diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 70143275e0a7..e5c69062a909 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -224,4 +224,5 @@ struct kvm_pmu_ops amd_pmu_ops __initdata = { .reset = amd_pmu_reset, .EVENTSEL_EVENT = AMD64_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_AMD_PMC_MAX_GENERIC, + .MIN_NR_GP_COUNTERS = AMD64_NUM_COUNTERS, }; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index b2f279f934b1..30ec9ccdea47 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -777,4 +777,5 @@ struct kvm_pmu_ops intel_pmu_ops __initdata = { .cleanup = intel_pmu_cleanup, .EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT, .MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC, + .MIN_NR_GP_COUNTERS = 1, }; From patchwork Sat Jun 3 01:10:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DB6BC77B7A for ; Sat, 3 Jun 2023 01:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237194AbjFCBLm (ORCPT ); Fri, 2 Jun 2023 21:11:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237134AbjFCBL2 (ORCPT ); Fri, 2 Jun 2023 21:11:28 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 779B4E74 for ; Fri, 2 Jun 2023 18:11:17 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-bad475920a8so8800728276.1 for ; Fri, 02 Jun 2023 18:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754676; x=1688346676; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=9mEKg+5dKinZ3o/gKM2CFOEFc6et6wjklTlAkP2Ylko=; b=q6p+9D8qbbuObxrHFz+nYKPtoZwhdWYziXBWxqr37YSs6to0F7StpHNbvtTfIWq0Sw lBR26pE0sYw6CXLdXhJHydn11m66uJ4O1XHwgnYOyebl03LpxV6tFqOb0Gl13HfZHZA2 V2lfNXHNbh0lHwcbvkE7GMb1EA/EyRgDUzJ8GXp4UpoFxcjkihJm19pzeeeoy2ApqcFq owrzIU6aIVCvXuxeJnGf2CVjh0Z7LP+BQSLa5+8otX7ul9UvzUA3AVJzndHLva9e6kRr pkzIgbnSD8GJ94RDO0EXbm10j3jsdpWcWz6ebGFS3BVJTxsu1wAi8nGtuimZ1iZ0pF20 g5Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754676; x=1688346676; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9mEKg+5dKinZ3o/gKM2CFOEFc6et6wjklTlAkP2Ylko=; b=jV4jrJY8sHGDv7qGgqQGSgg5bY1LTAYwySMiFW4OIOyEJLqbib9dI3X3jk8QRv9enq qjQZfeKsQnPHUnvKK57Kp7qPMpd/30xZBmnsj2tHc3/4JuiFbXfcZFSRxVAMCrl7/Bzx Gc5OK3eM0zAHzSRmC3yYRxzuWfl59A4pJdoo2Q9zyrqCD7pobTzs64b9umb5SWGS4RQP S9wK3k7nnjRx/NCd+pHF2ST/2d+OHteVqAIH11DhQYPcSEbBRn91KsCP5pSGkoe2+U0Z 00nVtLoYppWcxiuHThAt4LjfAf8tz8+01/KZzqYgRpjYCr8KJ88S4gV4WPWqGGhVauia pBZQ== X-Gm-Message-State: AC+VfDwYGoFo4rEw35cQGHOT3w74BIVkttFTN/EzSky7BmszKtk5voQn BeLwzBfaBEhvEyr45DJJ2fNm2+nHilw= X-Google-Smtp-Source: ACHHUZ7zFWMBwqK2A328pbGfSmAyVdVtLXmwv119oW090cAAvAY5vcpazqYtCNQZ7iz27J7VR0Yl6Wn8Fao= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:6d56:0:b0:bb1:d903:eae9 with SMTP id i83-20020a256d56000000b00bb1d903eae9mr2423730ybc.2.1685754676575; Fri, 02 Jun 2023 18:11:16 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:54 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-9-seanjc@google.com> Subject: [PATCH v7 08/12] KVM: x86/pmu: Advertise PERFCTR_CORE iff the min nr of counters is met From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Enable and advertise PERFCTR_CORE if and only if the minimum number of required counters are available, i.e. if perf says there are less than six general purpose counters. Opportunistically, use kvm_cpu_cap_check_and_set() instead of open coding the check for host support. Suggested-by: Sean Christopherson Signed-off-by: Like Xu [sean: massage shortlog and changelog] Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/svm.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index ca32389f3c36..d9669e3cc00a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5025,9 +5025,18 @@ static __init void svm_set_cpu_caps(void) boot_cpu_has(X86_FEATURE_AMD_SSBD)) kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); - /* AMD PMU PERFCTR_CORE CPUID */ - if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) - kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE); + if (enable_pmu) { + /* + * Enumerate support for PERFCTR_CORE if and only if KVM has + * access to enough counters to virtualize "core" support, + * otherwise limit vPMU support to the legacy number of counters. + */ + if (kvm_pmu_cap.num_counters_gp < AMD64_NUM_COUNTERS_CORE) + kvm_pmu_cap.num_counters_gp = min(AMD64_NUM_COUNTERS, + kvm_pmu_cap.num_counters_gp); + else + kvm_cpu_cap_check_and_set(X86_FEATURE_PERFCTR_CORE); + } /* CPUID 0x8000001F (SME/SEV features) */ sev_set_cpu_caps(); From patchwork Sat Jun 3 01:10:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B14AC7EE2C for ; Sat, 3 Jun 2023 01:11:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237056AbjFCBLw (ORCPT ); Fri, 2 Jun 2023 21:11:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237110AbjFCBLa (ORCPT ); Fri, 2 Jun 2023 21:11:30 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABCE110CC for ; Fri, 2 Jun 2023 18:11:19 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id d2e1a72fcca58-653843401d5so914316b3a.3 for ; Fri, 02 Jun 2023 18:11:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754678; x=1688346678; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=srE51TmJQHtlw1biDESTiNR2nLQR2FcTNrE5RKigF3Q=; b=iio8BhYA5NHbSfjdHUMcPlrVK7oQLcO4eGZLyOfc9szChSEAewXzlRkxlo6w57iyet wu5ivizMYbpgkF0Z92y/70R+NB/lkt7sFiS6Omn7QaF5OnZ0vKcC2jcCEql+cR3vVQUq M1Mo1Uo/qFycQHiFv8ySrIUZ+3v4wnEbJidQGRZHsAEC8HvRMzjjXc6CN+OtlNnmvYF6 wtRDG8Y4fV09qD/3TBzaMflqxFtro8Y3fu55v1mMHFkI41qukIc3Hn++yI/cCoM0vTk9 N06XlVY3EgZdG0QpeQX9FO83+rK7sM5Y0YhYd0KZaNegp5H/PoF6tfh1rovjzArgRvr3 O6nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754678; x=1688346678; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=srE51TmJQHtlw1biDESTiNR2nLQR2FcTNrE5RKigF3Q=; b=EcC/WyQnJ2FtnMEyRGd+QIbJlN60RfsFeP6k9E8Hj+jPHY3AGdiGwUQKqTCrns8viU o9Jr6uTtTnPDGWpOPkr6nf0vTeUDlcBTiD3phVsZ7sZmUxUe+jG1MXJD+HKYmM/ncPF0 2YCpP0GyFzIGryb/XKt0FzV19FWytHZiO/ZobOFZW0sNsXNCZ/SF+c+1oo6V35LuUz/z RzWPqaCqUenEyjKLL1zrNcqmpQIQWTZdDYeJYeFYg2wTx49NCSRZJRW4Q7Ea6BUUVlCd BIquXZLi45x/8evGaqiromNDEtxJoxlXabQ6G1RBrSbPJMGNIVaMnjbHreSqwviVF3wG AVSA== X-Gm-Message-State: AC+VfDyiXbLUgOeSmn9lRnxbIbHxTubW60NU41TC41VMGnhGgqZIiskF tR9R1VYn1mlVJSGde/PU7H4FJtZnko8= X-Google-Smtp-Source: ACHHUZ6rk8V5LUzWINE9mTURsU/+yccuxSJPXW34KbNxljXjIHJQrfw7zZ5SU0Zy0xRrptKnhFRdv3Gk7kg= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6a00:9a3:b0:653:b76d:4d52 with SMTP id u35-20020a056a0009a300b00653b76d4d52mr729527pfg.2.1685754678499; Fri, 02 Jun 2023 18:11:18 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:55 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-10-seanjc@google.com> Subject: [PATCH v7 09/12] KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Cap the number of general purpose counters enumerated on AMD to what KVM actually supports, i.e. don't allow userspace to coerce KVM into thinking there are more counters than actually exist, e.g. by enumerating X86_FEATURE_PERFCTR_CORE in guest CPUID when its not supported. Suggested-by: Sean Christopherson Signed-off-by: Like Xu [sean: massage changelog] Signed-off-by: Sean Christopherson --- arch/x86/kvm/svm/pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index e5c69062a909..c03958063a76 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -170,6 +170,9 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) else pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS; + pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters, + kvm_pmu_cap.num_counters_gp); + pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1; pmu->reserved_bits = 0xfffffff000280000ull; pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; From patchwork Sat Jun 3 01:10:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEC36C77B7A for ; Sat, 3 Jun 2023 01:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237240AbjFCBL7 (ORCPT ); Fri, 2 Jun 2023 21:11:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237096AbjFCBLo (ORCPT ); Fri, 2 Jun 2023 21:11:44 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF40A10E6 for ; Fri, 2 Jun 2023 18:11:21 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-bad06cc7fb7so3997163276.3 for ; Fri, 02 Jun 2023 18:11:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754680; x=1688346680; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=7zN3kqHNvCh1Otwz2V0BbGSa363179wUZXnCVirEw3o=; b=fQ2ArVgdVKtsRKDC1mFspyqAB1rKkpyxJ+tHZ4JpKxAOHj30bXemR+G/PUS39TSKjC jUj2rKGBVe8m8+UkbZ62AU666oR5aZcP67CvMfwcT2u1Ko6o3HLtZTXFIysnLaeIi4g0 +4fadOqdCCssLPqH+5i4HiE6nzRVXRJnojd6SXAKZqEmMfDp0fTSljRTbDxnnE2dfrOy xVb39pj77YBjOORmEYsq9UAJ8XpCZHE7LVxFdaSUrZiVajML8qgMWHh9h06CRWX9Vvz2 /wWQLRqmRNykDOtmJVA6Q3gjlGX+X4HjnRqZrEQj0IfvLKmE2kFuiKRALuPdeGrA+Hj8 dY5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754680; x=1688346680; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7zN3kqHNvCh1Otwz2V0BbGSa363179wUZXnCVirEw3o=; b=Moun8mgUMtsvxaqN5SpuEj2ep5qdnLyRAuxTz6PJMH9E9UxoCOt2b797zu4QFnpuHj ZzVa5zybzD9T++4Q5IjBlS0ojy4psS0S0TS01ZCXSQH6EUFrQNX7+ABkjUdthlEX7NDS ejiDZgE0yYADwNb679YxzxSpq2VAohc+hZXDegM/+ufAEFYY6TLidcPKg0XBfr5u6t8R dy0uZNfbGkV4XyfmhRKucLcUD2Z7zChzKgtU9WyXO2WkDdg7wn8MX1c9hZ5iH1diFeUP XTuTvwu2vW8Q5FMchrlXPt5ZXYcP+BFkxbSm4LOR5S0QeqFNYCnE0Hg/y+i716ZH/bMw aQEw== X-Gm-Message-State: AC+VfDwyrbSP/2ikclxfbh92GSdR/D5DQRF4E22da1/eH5FB1cmKa2m1 /Vqa5U0VgHGtL1YDGxQk1uTvkpC+qqg= X-Google-Smtp-Source: ACHHUZ6M56Lc+0oNspslFzbSVvTeJtlLsggZcvJQZNDQswnP85AG+PH1oRPTtIqzQRXOU552Np0uogO3+is= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:4aa:b0:ba8:939b:6574 with SMTP id r10-20020a05690204aa00b00ba8939b6574mr2808892ybs.12.1685754680252; Fri, 02 Jun 2023 18:11:20 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:56 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-11-seanjc@google.com> Subject: [PATCH v7 10/12] KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Add a KVM-only leaf for AMD's PerfMonV2 to redirect the kernel's scattered version to its architectural location, e.g. so that KVM can query guest support via guest_cpuid_has(). Suggested-by: Sean Christopherson Signed-off-by: Like Xu [sean: massage changelog] Signed-off-by: Sean Christopherson --- arch/x86/kvm/reverse_cpuid.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index a5717282bb9c..56cbdb24400a 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -15,6 +15,7 @@ enum kvm_only_cpuid_leafs { CPUID_12_EAX = NCAPINTS, CPUID_7_1_EDX, CPUID_8000_0007_EDX, + CPUID_8000_0022_EAX, NR_KVM_CPU_CAPS, NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS, @@ -47,6 +48,9 @@ enum kvm_only_cpuid_leafs { /* CPUID level 0x80000007 (EDX). */ #define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8) +/* CPUID level 0x80000022 (EAX) */ +#define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0) + struct cpuid_reg { u32 function; u32 index; @@ -74,6 +78,7 @@ static const struct cpuid_reg reverse_cpuid[] = { [CPUID_7_1_EDX] = { 7, 1, CPUID_EDX}, [CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX}, [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, + [CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX}, }; /* @@ -108,6 +113,8 @@ static __always_inline u32 __feature_translate(int x86_feature) return KVM_X86_FEATURE_SGX_EDECCSSA; else if (x86_feature == X86_FEATURE_CONSTANT_TSC) return KVM_X86_FEATURE_CONSTANT_TSC; + else if (x86_feature == X86_FEATURE_PERFMON_V2) + return KVM_X86_FEATURE_PERFMON_V2; return x86_feature; } From patchwork Sat Jun 3 01:10:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52F14C77B7A for ; Sat, 3 Jun 2023 01:12:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237254AbjFCBMH (ORCPT ); Fri, 2 Jun 2023 21:12:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237205AbjFCBLp (ORCPT ); Fri, 2 Jun 2023 21:11:45 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15F2D10F8 for ; Fri, 2 Jun 2023 18:11:23 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-565c380565dso61344527b3.1 for ; Fri, 02 Jun 2023 18:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754682; x=1688346682; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=Ru4NXMiYqBKlufWL9jxqCVd/0d0D25zGIOSPpyTm3aM=; b=V3X79M39GOaEpzyiwPbShLWgs/39VTBmFVjJc2GZySWh481lXM2HZbFBC8L4O9uI24 4TK1ZpDDjZo9KyaD8pfYqBc8cyLMtrwuq+Vs611gm4VRZ5shL0dBL0z8L2oj7TlPFF13 gB4GnKoHO0FVTVjBZRKS6OkcU6XCC5b1MXMqIwXS0gv3bBmgaxgz3+dSCXTqH+13Mh0P Jje/hUBZbjB1CmIS7iOUBGXv3NHL2bBDSMOlKLIdEWkTTv6F7jShljDAuSuQil3C8r5G +TwQuwlkNYRgyrjHjN+pNeb4KlCRuAHEs4Gsg3WX0WpvmdgHzwzm7fgoW0OuSZDSP5r4 DMyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754682; x=1688346682; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Ru4NXMiYqBKlufWL9jxqCVd/0d0D25zGIOSPpyTm3aM=; b=adISME95/QFb6gAtAEDaud9ALyBxDZI7nNVdKQZ5XvlQQv2ZMd1RdNUONx/5/yM09W xS19TIjvIGtPrEpUIPXsszbuEDSuSPRm31xunC9wUddEX6WjnHJhpVTRWEeIx8goZRU3 e1fMOzCndkT9TdA2AyaA2OUQp4eF7Yir/JAzK4RrRaPaqHFmk1DxXcu3aElvj+TWj6Dn Myw/R5lcNUxyIVZjb0aNCAmC5OmafurTSJ0EXEvj+GIxKLx3N+dKc9AiD7JJheZMm2nX R5Y5uMg9GP0UePv1ygnr78r16Efj/48KmoWbWlbWnbCEkopQzBSU/fwA3WKtZFLl9tEH 9G7w== X-Gm-Message-State: AC+VfDxllYOBgLroDkI6xSEqGZ7ndtRXby7M93xT6Ud9VfijH3js9lsq 0wLKgerk0Sa25vEJgZGunvX3avuvhMc= X-Google-Smtp-Source: ACHHUZ4Ax00P3OBB5zcoiD+bjlYBSQ75XLvh6ta/bvdoFWmeGs8yJxOlppBceCDSIr1q1PDDh3eGpHnhMcE= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a81:700c:0:b0:561:4723:2088 with SMTP id l12-20020a81700c000000b0056147232088mr908922ywc.4.1685754682122; Fri, 02 Jun 2023 18:11:22 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:57 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-12-seanjc@google.com> Subject: [PATCH v7 11/12] KVM: x86/svm/pmu: Add AMD PerfMonV2 support From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu If AMD Performance Monitoring Version 2 (PerfMonV2) is detected by the guest, it can use a new scheme to manage the Core PMCs using the new global control and status registers. In addition to benefiting from the PerfMonV2 functionality in the same way as the host (higher precision), the guest also can reduce the number of vm-exits by lowering the total number of MSRs accesses. In terms of implementation details, amd_is_valid_msr() is resurrected since three newly added MSRs could not be mapped to one vPMC. The possibility of emulating PerfMonV2 on the mainframe has also been eliminated for reasons of precision. Co-developed-by: Sandipan Das Signed-off-by: Sandipan Das Signed-off-by: Like Xu [sean: drop "Based on the observed HW." comments] Signed-off-by: Sean Christopherson --- arch/x86/kvm/pmu.c | 18 +++++++++++++- arch/x86/kvm/svm/pmu.c | 55 ++++++++++++++++++++++++++++++++++-------- arch/x86/kvm/x86.c | 10 ++++++++ 3 files changed, 72 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 4315f46aabfb..bf653df86112 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -585,11 +585,14 @@ int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) switch (msr) { case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: msr_info->data = pmu->global_status; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: case MSR_CORE_PERF_GLOBAL_CTRL: msr_info->data = pmu->global_ctrl; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: case MSR_CORE_PERF_GLOBAL_OVF_CTRL: msr_info->data = 0; break; @@ -607,16 +610,28 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) u64 data = msr_info->data; u64 diff; + /* + * Note, AMD ignores writes to reserved bits and read-only PMU MSRs, + * whereas Intel generates #GP on attempts to write reserved/RO MSRs. + */ switch (msr) { case MSR_CORE_PERF_GLOBAL_STATUS: if (!msr_info->host_initiated) return 1; /* RO MSR */ + fallthrough; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + /* Per PPR, Read-only MSR. Writes are ignored. */ + if (!msr_info->host_initiated) + break; if (data & pmu->global_status_mask) return 1; pmu->global_status = data; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + data &= ~pmu->global_ctrl_mask; + fallthrough; case MSR_CORE_PERF_GLOBAL_CTRL: if (!kvm_valid_perf_global_ctrl(pmu, data)) return 1; @@ -634,7 +649,8 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) */ if (data & pmu->global_status_mask) return 1; - + fallthrough; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: if (!msr_info->host_initiated) pmu->global_status &= ~data; break; diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index c03958063a76..cef5a3d0abd0 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -94,12 +94,6 @@ static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, return amd_pmc_idx_to_pmc(vcpu_to_pmu(vcpu), idx & ~(3u << 30)); } -static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) -{ - /* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough. */ - return false; -} - static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -111,6 +105,29 @@ static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) return pmc; } +static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + + switch (msr) { + case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: + return pmu->version > 0; + case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: + return guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE); + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + return pmu->version > 1; + default: + if (msr > MSR_F15H_PERF_CTR5 && + msr < MSR_F15H_PERF_CTL0 + 2 * pmu->nr_arch_gp_counters) + return pmu->version > 1; + break; + } + + return amd_msr_idx_to_pmc(vcpu, msr); +} + static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -164,23 +181,39 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) static void amd_pmu_refresh(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + union cpuid_0x80000022_ebx ebx; - if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) + pmu->version = 1; + if (guest_cpuid_has(vcpu, X86_FEATURE_PERFMON_V2)) { + pmu->version = 2; + /* + * Note, PERFMON_V2 is also in 0x80000022.0x0, i.e. the guest + * CPUID entry is guaranteed to be non-NULL. + */ + BUILD_BUG_ON(x86_feature_cpuid(X86_FEATURE_PERFMON_V2).function != 0x80000022 || + x86_feature_cpuid(X86_FEATURE_PERFMON_V2).index); + ebx.full = kvm_find_cpuid_entry_index(vcpu, 0x80000022, 0)->ebx; + pmu->nr_arch_gp_counters = ebx.split.num_core_pmc; + } else if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) { pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE; - else + } else { pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS; + } pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters, kvm_pmu_cap.num_counters_gp); + if (pmu->version > 1) { + pmu->global_ctrl_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1); + pmu->global_status_mask = pmu->global_ctrl_mask; + } + pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1; pmu->reserved_bits = 0xfffffff000280000ull; pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; - pmu->version = 1; /* not applicable to AMD; but clean them to prevent any fall out */ pmu->counter_bitmask[KVM_PMC_FIXED] = 0; pmu->nr_arch_fixed_counters = 0; - pmu->global_status = 0; bitmap_set(pmu->all_valid_pmc_idx, 0, pmu->nr_arch_gp_counters); } @@ -211,6 +244,8 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) pmc_stop_counter(pmc); pmc->counter = pmc->prev_counter = pmc->eventsel = 0; } + + pmu->global_ctrl = pmu->global_status = 0; } struct kvm_pmu_ops amd_pmu_ops __initdata = { diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c0778ca39650..abfba3cae0ba 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1483,6 +1483,10 @@ static const u32 msrs_to_save_pmu[] = { MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, + + MSR_AMD64_PERF_CNTR_GLOBAL_CTL, + MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, + MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, }; static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) + @@ -7150,6 +7154,12 @@ static void kvm_probe_msr_to_save(u32 msr_index) kvm_pmu_cap.num_counters_fixed) return; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) + return; + break; case MSR_IA32_XFD: case MSR_IA32_XFD_ERR: if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) From patchwork Sat Jun 3 01:10:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13265989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7FA7C7EE2C for ; Sat, 3 Jun 2023 01:12:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237212AbjFCBMJ (ORCPT ); Fri, 2 Jun 2023 21:12:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237073AbjFCBLq (ORCPT ); Fri, 2 Jun 2023 21:11:46 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85B5B1703 for ; Fri, 2 Jun 2023 18:11:24 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1b05714b3bfso12195925ad.0 for ; Fri, 02 Jun 2023 18:11:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685754684; x=1688346684; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=O6aZ99/gTomPSpDx04dBgMUhLAou1VtK/fDnLslrZmU=; b=x7HWDH8/Bs9YtzCXj/mrZ81zxYF5I7CITbLVs3xIKM9SDl8Dj5A8nTCf6r3RXcbCn2 blMFBeeTkuC5motXASnEpV1/tXRACqNxLOenferCAhBm54ivgYoqeyd48H878wW44RUh Be2SKu4/9omccwscEsK5eKJS32/tTOLSkQ/MwCfR1wvFCrEtth7QbICvOK5L2RRkCHhw GIKF2gf1ztel2DMowiBL4haf3VfY/E/eR3BvaajX65im7/Y3zWITDuCfOC8qWpfWQ2Av 4uZxD2JZrD2g+4zgtsr6pxlRtA51RsTEYC4LdQQ/KJSmyBYowcXw1YoXo021O2sAwHNA XO+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685754684; x=1688346684; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=O6aZ99/gTomPSpDx04dBgMUhLAou1VtK/fDnLslrZmU=; b=AtAYwSB7w1kusVPunuNFzcDCsbxnamEwZKFyg7mdPElke69pwCgJ7SFm6kng5QCgPa gRkrPYbHGY8WoDOYdXWII6N5dVasEhumnHMIZF5S2uuqUcvouDw5sd6gEu4bnnNR2ye6 YieAYflbAClsde+yvmb7v7NTxxes5GeB4wmJMMQwCY0aW0OJhTFh/cK6JppX2k7pBSgE 64zGC1dz0ybiC9PJGGxEPyy3NgtSxOh/GLpjpBwYIb+fxeJfc/r2qiZR+OUhWppNPwEU aPKSXP5LJQvEi1xoVtNUC4hHAveZY7erp3Q7xLil9uX7UueiZWU/0+S9fdREDhuq+pnG WMeA== X-Gm-Message-State: AC+VfDxuvCQiGdcDBWuz9Chs6oemMz2iIRDZKbxqQeJ/U9hZF+Q/jVEp 1WT0AgxBGCz39HGlznb7GPCG4oJ2X98= X-Google-Smtp-Source: ACHHUZ5j4aR8F78dxip8RbVwwtN7tQSfuK9BhguCjo7+vHSO3ZVYBRQZ6EYSIpVmjSUrhNK8nWPG//nOytk= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:c204:b0:1a6:b4cf:f6c0 with SMTP id 4-20020a170902c20400b001a6b4cff6c0mr375741pll.4.1685754683772; Fri, 02 Jun 2023 18:11:23 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 18:10:58 -0700 In-Reply-To: <20230603011058.1038821-1-seanjc@google.com> Mime-Version: 1.0 References: <20230603011058.1038821-1-seanjc@google.com> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230603011058.1038821-13-seanjc@google.com> Subject: [PATCH v7 12/12] KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu , Like Xu , Jim Mattson , Sandipan Das Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu CPUID leaf 0x80000022 i.e. ExtPerfMonAndDbg advertises some new performance monitoring features for AMD processors. Bit 0 of EAX indicates support for Performance Monitoring Version 2 (PerfMonV2) features. If found to be set during PMU initialization, the EBX bits of the same CPUID function can be used to determine the number of available PMCs for different PMU types. Expose the relevant bits via KVM_GET_SUPPORTED_CPUID so that guests can make use of the PerfMonV2 features. Co-developed-by: Sandipan Das Signed-off-by: Sandipan Das Signed-off-by: Like Xu Signed-off-by: Sean Christopherson --- arch/x86/kvm/cpuid.c | 28 +++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.c | 4 ++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 61bc71882f07..0e5584f4acd7 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -734,6 +734,10 @@ void kvm_set_cpu_caps(void) F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ ); + kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX, + F(PERFMON_V2) + ); + /* * Synthesize "LFENCE is serializing" into the AMD-defined entry in * KVM's supported CPUID if the feature is reported as supported by the @@ -1128,7 +1132,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->edx = 0; break; case 0x80000000: - entry->eax = min(entry->eax, 0x80000021); + entry->eax = min(entry->eax, 0x80000022); /* * Serializing LFENCE is reported in a multitude of ways, and * NullSegClearsBase is not reported in CPUID on Zen2; help @@ -1233,6 +1237,28 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->ebx = entry->ecx = entry->edx = 0; cpuid_entry_override(entry, CPUID_8000_0021_EAX); break; + /* AMD Extended Performance Monitoring and Debug */ + case 0x80000022: { + union cpuid_0x80000022_ebx ebx; + + entry->ecx = entry->edx = 0; + if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { + entry->eax = entry->ebx; + break; + } + + cpuid_entry_override(entry, CPUID_8000_0022_EAX); + + if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) + ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; + else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) + ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; + else + ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; + + entry->ebx = ebx.full; + break; + } /*Add support for Centaur's CPUID instruction*/ case 0xC0000000: /*Just support up to 0xC0000004 now*/ diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index d9669e3cc00a..ff48cdea1fbf 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5036,6 +5036,10 @@ static __init void svm_set_cpu_caps(void) kvm_pmu_cap.num_counters_gp); else kvm_cpu_cap_check_and_set(X86_FEATURE_PERFCTR_CORE); + + if (kvm_pmu_cap.version != 2 || + !kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) + kvm_cpu_cap_clear(X86_FEATURE_PERFMON_V2); } /* CPUID 0x8000001F (SME/SEV features) */