From patchwork Sun Jun 4 10:28:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13266535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F0AAC7EE23 for ; Sun, 4 Jun 2023 10:30:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5kz1-00011g-6r; Sun, 04 Jun 2023 06:29:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q5kz0-00011Q-8u; Sun, 04 Jun 2023 06:29:10 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q5kyy-0005o9-K8; Sun, 04 Jun 2023 06:29:09 -0400 Received: by mail-oi1-x229.google.com with SMTP id 5614622812f47-38c35975545so3348203b6e.1; Sun, 04 Jun 2023 03:29:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685874546; x=1688466546; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=N424z4fvxORhlJsYYBVuPg930NH8Qs7g6+F84APsNP8=; b=cg6iG79Hrg2o/QGmGWKOxFH2g4lM+hEjKhczcIY3l24D7Ngq3JkItePqMa+ch7kVkp R2SAAG3bjlqZd1Pduex6cF7ahg+2dg4RR7FZfCa3MdulcPa0mvVLWWaoow38HwkQ2Gi3 zYfRZubCS25ciu0v+YQb8rskGk9drooyN7NyGeNops0iR9jQ+l27L1sg09E9+hRMEx2m HQOx/1VBmEAV4X6FVgOtwn0oMNrML7BuX7QhDVC8LqxAlNLTNb8l+wRY44++N7nk2g/z EVPTqtC2NF/qSBxtyeTLbzwNN21VxygeJEuWC20nVVD6MTkMGqN7hSXPM2tFhExC0m8l as/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685874546; x=1688466546; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=N424z4fvxORhlJsYYBVuPg930NH8Qs7g6+F84APsNP8=; b=ZHTESS3Hqvm41pGLfkmc6gIrQBIZo9kA1o0Zm/rvEV7ViL/8T/6+RRjNb0XXo58kEH N2Yq8bgTWsKPdEGStDFLCZWmRfavLhdpdmWbFbnUYQigFXl6SyEx0YpVrPOZ6cMBp+q2 pF5BhgP6O/wdQ49TDgPmpph04RJ8zQQfiHWtMlGq1YKMxThAi85mFmBVH5FasRMklWwz Jnr9M68J9Ha/IhJXdXbSit6znPFFBVBZZuoiWCtJBblNMPZoA7VCHrR2mtnNsrhS4UoZ kdW60Ykl+M1D2ip8SMGE/SUDP6J1cLomahBTH5i9T2uNIc1/i7tXEdMbFU9kE3SqfLo1 VPww== X-Gm-Message-State: AC+VfDzsDmMmvvqE3LARCDD+6id7vBsd9xiS3OKfSw4j1PWQOwM/pz+L nGZ5o+nnosWsSGTnlm2dfsE= X-Google-Smtp-Source: ACHHUZ6pQghZT+VxTcF7Bf8YiTl9fKA5IH4O1kCadvbMlHE71AXAORWYDTkE79W6FoLl1oO/vKyXYg== X-Received: by 2002:a05:6808:6c3:b0:398:bd63:b5fe with SMTP id m3-20020a05680806c300b00398bd63b5femr4699882oih.18.1685874546210; Sun, 04 Jun 2023 03:29:06 -0700 (PDT) Received: from wheely.local0.net ([203.221.142.9]) by smtp.gmail.com with ESMTPSA id ik8-20020a170902ab0800b001ae0152d280sm4489241plb.193.2023.06.04.03.29.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Jun 2023 03:29:05 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH 1/4] target/ppc: Fix lqarx to set cpu_reserve Date: Sun, 4 Jun 2023 20:28:54 +1000 Message-Id: <20230604102858.148584-1-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=npiggin@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org lqarx does not set cpu_reserve, which causes stqcx. to never succeed. Fix this and slightly rearrange gen_load_locked so the two functions match more closely. Cc: qemu-stable@nongnu.org Fixes: 94bf2658676 ("target/ppc: Use atomic load for LQ and LQARX") Fixes: 57b38ffd0c6 ("target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ") Signed-off-by: Nicholas Piggin --- cpu_reserve got lost in the parallel part with the first patch, then from serial part when it was merged with the parallel by the second patch. Thanks, Nick target/ppc/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3650d2985d..e129cdcb8f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3583,8 +3583,8 @@ static void gen_load_locked(DisasContext *ctx, MemOp memop) gen_set_access_type(ctx, ACCESS_RES); gen_addr_reg_index(ctx, t0); - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); tcg_gen_mov_tl(cpu_reserve, t0); + tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); tcg_gen_mov_tl(cpu_reserve_val, gpr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -3872,6 +3872,7 @@ static void gen_lqarx(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_RES); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); + tcg_gen_mov_tl(cpu_reserve, EA); /* Note that the low part is always in RD+1, even in LE mode. */ lo = cpu_gpr[rd + 1]; From patchwork Sun Jun 4 10:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13266534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41CD1C7EE2E for ; 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Sun, 04 Jun 2023 03:29:10 -0700 (PDT) Received: from wheely.local0.net ([203.221.142.9]) by smtp.gmail.com with ESMTPSA id ik8-20020a170902ab0800b001ae0152d280sm4489241plb.193.2023.06.04.03.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Jun 2023 03:29:09 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH 2/4] target/ppc: Ensure stcx size matches larx Date: Sun, 4 Jun 2023 20:28:55 +1000 Message-Id: <20230604102858.148584-2-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230604102858.148584-1-npiggin@gmail.com> References: <20230604102858.148584-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=npiggin@gmail.com; helo=mail-oa1-x33.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Differently-sized larx/stcx. pairs can succeed if the starting address matches. Add a size check to require stcx. exactly match the larx that established the reservation. Signed-off-by: Nicholas Piggin Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 4 ++-- target/ppc/translate.c | 8 ++++++++ 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 7959bfed0a..1d71f325d8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1124,6 +1124,7 @@ struct CPUArchState { target_ulong ca32; target_ulong reserve_addr; /* Reservation address */ + target_ulong reserve_size; /* Reservation size */ target_ulong reserve_val; /* Reservation value */ target_ulong reserve_val2; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 944a74befe..082981b148 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7421,8 +7421,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); } - qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", - env->reserve_addr); + qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", + (int)env->reserve_size, env->reserve_addr); if (flags & CPU_DUMP_FPU) { for (i = 0; i < 32; i++) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e129cdcb8f..5195047146 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -71,6 +71,7 @@ static TCGv cpu_cfar; #endif static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; +static TCGv cpu_reserve_size; static TCGv cpu_reserve_val; static TCGv cpu_reserve_val2; static TCGv cpu_fpscr; @@ -141,6 +142,9 @@ void ppc_translate_init(void) cpu_reserve = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, reserve_addr), "reserve_addr"); + cpu_reserve_size = tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, reserve_size), + "reserve_size"); cpu_reserve_val = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, reserve_val), "reserve_val"); @@ -3584,6 +3588,7 @@ static void gen_load_locked(DisasContext *ctx, MemOp memop) gen_set_access_type(ctx, ACCESS_RES); gen_addr_reg_index(ctx, t0); tcg_gen_mov_tl(cpu_reserve, t0); + tcg_gen_movi_tl(cpu_reserve_size, memop_size(memop)); tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); tcg_gen_mov_tl(cpu_reserve_val, gpr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -3816,6 +3821,7 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop) gen_set_access_type(ctx, ACCESS_RES); gen_addr_reg_index(ctx, t0); tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, memop_size(memop), l1); t0 = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, @@ -3873,6 +3879,7 @@ static void gen_lqarx(DisasContext *ctx) EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_size, 128); /* Note that the low part is always in RD+1, even in LE mode. */ lo = cpu_gpr[rd + 1]; @@ -3907,6 +3914,7 @@ static void gen_stqcx_(DisasContext *ctx) gen_addr_reg_index(ctx, EA); tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, 128, lab_fail); cmp = tcg_temp_new_i128(); val = tcg_temp_new_i128(); From patchwork Sun Jun 4 10:28:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13266532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BD14C7EE23 for ; Sun, 4 Jun 2023 10:30:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5kzB-00016F-K5; Sun, 04 Jun 2023 06:29:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q5kz9-00013y-QZ; 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Sun, 04 Jun 2023 03:29:13 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH 3/4] target/ppc: Remove larx/stcx. memory barrier semantics Date: Sun, 4 Jun 2023 20:28:56 +1000 Message-Id: <20230604102858.148584-3-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230604102858.148584-1-npiggin@gmail.com> References: <20230604102858.148584-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org larx and stcx. are not defined to order any memory operations. Remove the barriers. Signed-off-by: Nicholas Piggin Reviewed-by: Richard Henderson --- target/ppc/translate.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5195047146..77e1c5abb6 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3591,7 +3591,6 @@ static void gen_load_locked(DisasContext *ctx, MemOp memop) tcg_gen_movi_tl(cpu_reserve_size, memop_size(memop)); tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); tcg_gen_mov_tl(cpu_reserve_val, gpr); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } #define LARX(name, memop) \ @@ -3835,11 +3834,6 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop) gen_set_label(l1); - /* - * Address mismatch implies failure. But we still need to provide - * the memory barrier semantics of the instruction. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); gen_set_label(l2); @@ -3943,11 +3937,6 @@ static void gen_stqcx_(DisasContext *ctx) tcg_gen_br(lab_over); gen_set_label(lab_fail); - /* - * Address mismatch implies failure. But we still need to provide - * the memory barrier semantics of the instruction. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); gen_set_label(lab_over); From patchwork Sun Jun 4 10:28:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13266533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F82BC7EE2A for ; Sun, 4 Jun 2023 10:30:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q5kzE-00017O-GO; Sun, 04 Jun 2023 06:29:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q5kzB-00016S-SN; Sun, 04 Jun 2023 06:29:22 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q5kzA-0005pm-1k; Sun, 04 Jun 2023 06:29:21 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-652d1d3e040so1455541b3a.1; Sun, 04 Jun 2023 03:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685874558; x=1688466558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dqSUGBzCwFM3BYWfaK+JzwNF/GE/uwEKUodIuU1CLhs=; b=P8L20qM/FEP+WnZXi06jOqw/gGd4DhnoLeLRUrDyt2nV1e3WG1U5aueNwQLZWJdCKW 4jvDYGMoWMBnmDXsAFyXmh5UcKnVOZscRDjLUAJkgAs0QA/yXmeggAqzjasRUa1X6zeX ZXXp64crp7GPUyTFJs/RIzIpxJFNnx8rKGtCG2oYmHrvhR7xs8fGZc3xkM1Cu7XyCy9d BE4pHHFi0+ZrnKQTOTrK06nIBh27luCSDY/JKJgjS6kKvPPNyS+Dkc+TI73pJ995djyL IkTG/L+qoqygODXU3hNidYp3DUywxWdvMwPanjXH2OT8lw7M9W5mBSFUEciFbn1/MwrZ GQ7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685874558; x=1688466558; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dqSUGBzCwFM3BYWfaK+JzwNF/GE/uwEKUodIuU1CLhs=; b=OoVetBFncN1KeYkDetQRfSFW3LNwzaxhpBf9ggsv619LmkFDxktNVwqyLJ5qz2K40B f9zopbLeeMueZzgKIgmjjmlcxljA/+QZQRikl2M6fnixChqsP6qKf/A5dvOXXWB500Lx HiUT+uflseRhqEr73ocSgsNs1T2cgbvW3dv68wqeykGITUKk7hIy6/t7Ea9tKyNWZUdi kJjiXCmCWhKPkJfQkDcDYp2Wm37AnUGeIPa/vQL1Kz4pSbQWc8M+YotryfNuATc9IUx8 +iUhn9MRMjdYfF+yi8B6hpQ5e96GwP8Mz/UqimcbeTqPK/o2HJM3Q9zqtKQrxtwCtKli wsZg== X-Gm-Message-State: AC+VfDwiRTLo/YxVeHgBk93PAzu7s7hbjuMbf7dmade1uN8k2bu8GPSK ntd4VxcEz08JWaakXGbQHXLCMeBO5gk= X-Google-Smtp-Source: ACHHUZ5V04CT2Cpe72AopXmncBfudugGLKLU76cigNoBKqLwCIlPvz35yXIShQav+P52rbR3HdmiDA== X-Received: by 2002:a17:903:284:b0:1a9:581d:3efb with SMTP id j4-20020a170903028400b001a9581d3efbmr3090494plr.6.1685874557676; Sun, 04 Jun 2023 03:29:17 -0700 (PDT) Received: from wheely.local0.net ([203.221.142.9]) by smtp.gmail.com with ESMTPSA id ik8-20020a170902ab0800b001ae0152d280sm4489241plb.193.2023.06.04.03.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Jun 2023 03:29:17 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH 4/4] target/ppc: Rework store conditional to avoid branch Date: Sun, 4 Jun 2023 20:28:57 +1000 Message-Id: <20230604102858.148584-4-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230604102858.148584-1-npiggin@gmail.com> References: <20230604102858.148584-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rework store conditional to avoid a branch in the success case. Change some of the variable names and layout while here so gen_conditional_store more closely matches gen_stqcx_. Signed-off-by: Nicholas Piggin Reviewed-by: Richard Henderson --- target/ppc/translate.c | 65 ++++++++++++++++++++---------------------- 1 file changed, 31 insertions(+), 34 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 77e1c5abb6..cf99e961f7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3812,31 +3812,32 @@ static void gen_stdat(DisasContext *ctx) static void gen_conditional_store(DisasContext *ctx, MemOp memop) { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGv t0 = tcg_temp_new(); - int reg = rS(ctx->opcode); + TCGLabel *lfail; + TCGv EA; + TCGv cr0; + TCGv t0; + int rs = rS(ctx->opcode); + lfail = gen_new_label(); + EA = tcg_temp_new(); + cr0 = tcg_temp_new(); + t0 = tcg_temp_new(); + + tcg_gen_mov_tl(cr0, cpu_so); gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, t0); - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, memop_size(memop), l1); + gen_addr_reg_index(ctx, EA); + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, memop_size(memop), lfail); - t0 = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, - cpu_gpr[reg], ctx->mem_idx, - DEF_MEMOP(memop) | MO_ALIGN); + cpu_gpr[rs], ctx->mem_idx, + memop | MO_ALIGN); tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(t0, t0, cpu_so); - tcg_gen_trunc_tl_i32(cpu_crf[0], t0); - tcg_gen_br(l2); + tcg_gen_or_tl(cr0, cr0, t0); - gen_set_label(l1); - - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - - gen_set_label(l2); + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); tcg_gen_movi_tl(cpu_reserve, -1); } @@ -3890,25 +3891,26 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { - TCGLabel *lab_fail, *lab_over; - int rs = rS(ctx->opcode); + TCGLabel *lfail; TCGv EA, t0, t1; + TCGv cr0; TCGv_i128 cmp, val; + int rs = rS(ctx->opcode); if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } - lab_fail = gen_new_label(); - lab_over = gen_new_label(); + lfail = gen_new_label(); + EA = tcg_temp_new(); + cr0 = tcg_temp_new(); + tcg_gen_mov_tl(cr0, cpu_so); gen_set_access_type(ctx, ACCESS_RES); - EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); - - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, 128, lab_fail); + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, 128, lfail); cmp = tcg_temp_new_i128(); val = tcg_temp_new_i128(); @@ -3931,15 +3933,10 @@ static void gen_stqcx_(DisasContext *ctx) tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(t0, t0, cpu_so); - tcg_gen_trunc_tl_i32(cpu_crf[0], t0); - - tcg_gen_br(lab_over); - gen_set_label(lab_fail); - - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + tcg_gen_or_tl(cr0, cr0, t0); - gen_set_label(lab_over); + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); tcg_gen_movi_tl(cpu_reserve, -1); } #endif /* defined(TARGET_PPC64) */