From patchwork Sun Jun 4 12:26:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 13266596 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C555DC7EE29 for ; Sun, 4 Jun 2023 12:27:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229904AbjFDM1J (ORCPT ); Sun, 4 Jun 2023 08:27:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229705AbjFDM1J (ORCPT ); Sun, 4 Jun 2023 08:27:09 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83AEF83; Sun, 4 Jun 2023 05:27:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1685881623; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=OrYR5qPyKXvfTrOCl2QZ+y5ZmDrd9I/Nr/7WM1Hie54=; b=R+gd789bh+l/TKhakJMMD4gDQF4qUuYwOmR/XtZPBQjJeMsIS9+pbJBsPYLQrc2UXWIhEo w1XcH9tRBZP9uReeYljG1XsGO+3lvTMVC+hGws6+Y8j9DP1FoMEvkfb5/hXPZlbl49ZWiL uqFhxVc43nKjZWn22iv3NjB+8aWnoLU= From: Paul Cercueil To: Thomas Bogendoerfer Cc: Paul Burton , Siarhei Volkau , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, list@opendingux.net Subject: [PATCH 1/4] MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccess Date: Sun, 4 Jun 2023 14:26:52 +0200 Message-Id: <20230604122655.69698-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Siarhei Volkau The LXW, LXH, LXHU opcodes are part of the MXU ASE found in Ingenic XBurst based SoCs. While technically part of the MXU ASE, they do not touch any of the SIMD registers, and can be used even when the MXU ASE is disabled. This patch makes it possible to emulate unaligned access for those instructions. Signed-off-by: Siarhei Volkau --- arch/mips/include/uapi/asm/inst.h | 33 +++++++++++++++++++++++++ arch/mips/kernel/unaligned.c | 41 +++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index 43d1faa02933..c29dbc8c1d49 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -272,6 +272,27 @@ enum lx_func { lbx_op = 0x16, }; +/* + * func field for special2 MXU opcodes (Ingenic XBurst MXU). + */ +enum mxu_func { + /* TODO, other MXU funcs */ + mxu_lx_op = 0x28, +}; + +/* + * op field for special2 MXU LX opcodes (Ingenic XBurst MXU). + */ +enum lx_ingenic_func { + mxu_lxb_op, + mxu_lxh_op, + /* reserved */ + mxu_lxw_op = 3, + mxu_lxbu_op, + mxu_lxhu_op, + /* more reserved */ +}; + /* * BSHFL opcodes */ @@ -774,6 +795,17 @@ struct dsp_format { /* SPEC3 DSP format instructions */ ;)))))) }; +struct mxu_lx_format { /* SPEC2 MXU LX format instructions */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int rd : 5, + __BITFIELD_FIELD(unsigned int strd : 2, + __BITFIELD_FIELD(unsigned int op : 3, + __BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + struct spec3_format { /* SPEC3 */ __BITFIELD_FIELD(unsigned int opcode:6, __BITFIELD_FIELD(unsigned int rs:5, @@ -1125,6 +1157,7 @@ union mips_instruction { struct loongson3_lswc2_format loongson3_lswc2_format; struct loongson3_lsdc2_format loongson3_lsdc2_format; struct loongson3_lscsr_format loongson3_lscsr_format; + struct mxu_lx_format mxu_lx_format; }; union mips16e_instruction { diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index 7b5aba5df02e..f4cf94e92ec3 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -160,6 +160,47 @@ static void emulate_load_store_insn(struct pt_regs *regs, * The remaining opcodes are the ones that are really of * interest. */ +#ifdef CONFIG_MACH_INGENIC + case spec2_op: + if (insn.mxu_lx_format.func != mxu_lx_op) + goto sigbus; /* other MXU instructions we don't care */ + + switch (insn.mxu_lx_format.op) { + case mxu_lxw_op: + if (user && !access_ok(addr, 4)) + goto sigbus; + LoadW(addr, value, res); + if (res) + goto fault; + compute_return_epc(regs); + regs->regs[insn.mxu_lx_format.rd] = value; + break; + case mxu_lxh_op: + if (user && !access_ok(addr, 2)) + goto sigbus; + LoadHW(addr, value, res); + if (res) + goto fault; + compute_return_epc(regs); + regs->regs[insn.dsp_format.rd] = value; + break; + case mxu_lxhu_op: + if (user && !access_ok(addr, 2)) + goto sigbus; + LoadHWU(addr, value, res); + if (res) + goto fault; + compute_return_epc(regs); + regs->regs[insn.dsp_format.rd] = value; + break; + case mxu_lxb_op: + case mxu_lxbu_op: + goto sigbus; + default: + goto sigill; + } + break; +#endif case spec3_op: if (insn.dsp_format.func == lx_op) { switch (insn.dsp_format.op) { From patchwork Sun Jun 4 12:26:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 13266597 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4A3AC7EE29 for ; Sun, 4 Jun 2023 12:27:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229705AbjFDM1Q (ORCPT ); Sun, 4 Jun 2023 08:27:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230487AbjFDM1O (ORCPT ); Sun, 4 Jun 2023 08:27:14 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEA0FB5; Sun, 4 Jun 2023 05:27:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1685881625; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4bJflcJlGAugVDPpSX1OH5WDNgjOC+VFuKrhAQwMRcU=; b=JqvH8eUiOElpSqMVcgKMQrKSuZSdvWmTf88YMdix3ODjmaEnQe2d/9wmdCLfDRGNWbKAAF si2Z+ZxJfZT98oDJjyFYkqTKJHuAkcwtQ0sIA4xiBfRQHcfP2HVG/8zk4qbZduFCTqAxpC 12jioFl0IDKozCSfZvDSrhQOnabGerc= From: Paul Cercueil To: Thomas Bogendoerfer Cc: Paul Burton , Siarhei Volkau , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, list@opendingux.net, Paul Cercueil Subject: [PATCH 2/4] mips: ingenic: Remove useless __maybe_unused Date: Sun, 4 Jun 2023 14:26:53 +0200 Message-Id: <20230604122655.69698-2-paul@crapouillou.net> In-Reply-To: <20230604122655.69698-1-paul@crapouillou.net> References: <20230604122655.69698-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org These flags are useless in this case as the code referencing these data structures is always seen by the compiler (and not behind #ifdef guards). Signed-off-by: Paul Cercueil --- arch/mips/generic/board-ingenic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c index c422bbc890ed..7a4fce06875d 100644 --- a/arch/mips/generic/board-ingenic.c +++ b/arch/mips/generic/board-ingenic.c @@ -117,14 +117,14 @@ static void ingenic_halt(void) ingenic_wait_instr(); } -static int __maybe_unused ingenic_pm_enter(suspend_state_t state) +static int ingenic_pm_enter(suspend_state_t state) { ingenic_wait_instr(); return 0; } -static const struct platform_suspend_ops ingenic_pm_ops __maybe_unused = { +static const struct platform_suspend_ops ingenic_pm_ops = { .valid = suspend_valid_only_mem, .enter = ingenic_pm_enter, }; From patchwork Sun Jun 4 12:26:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 13266598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E57CC7EE23 for ; Sun, 4 Jun 2023 12:27:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231134AbjFDM1Y (ORCPT ); Sun, 4 Jun 2023 08:27:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231152AbjFDM1W (ORCPT ); Sun, 4 Jun 2023 08:27:22 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD049187; Sun, 4 Jun 2023 05:27:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1685881627; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ItyejJVAd6OmifZFydELiYIvaMkIzY4VNO5Z5lE6lpY=; b=pCOt4FSLUZ9o/qBct4J+gDN7wJ1Clrg08+OKw1ufTb5i+korp0e/tiFSgeUtir2Eju5mfK G0BXuWpmI6FUqV3DKjLj9XZONbtSwNufnglQRub1jwspbt7uFkKmQJjUe6Y8FhygwgIphA oYBIVwxme48hxM6f3RNMYVcEWGHHmx0= From: Paul Cercueil To: Thomas Bogendoerfer Cc: Paul Burton , Siarhei Volkau , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, list@opendingux.net, Paul Cercueil Subject: [PATCH 3/4] mips: ingenic: Enable EXT/2 divider on JZ4750/55/60 if EXT is 24 MHz Date: Sun, 4 Jun 2023 14:26:54 +0200 Message-Id: <20230604122655.69698-3-paul@crapouillou.net> In-Reply-To: <20230604122655.69698-1-paul@crapouillou.net> References: <20230604122655.69698-1-paul@crapouillou.net> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The JZ4750, JZ4755 and JZ4760 (non-B version) support using a 24 MHz external crystal oscillator instead of the typical 12 MHz one. However, most of the SoC's IP blocks only work with a 12 MHz clock. Thanksfully, there is a /2 divider we can enable when a 24 MHz external crystal is present. Force-enable this /2 divider when the oscillator is 24 MHz, so that the SoC always uses a 12 MHz clock internally. It is done here, and not in the clocks driver, because we need the EXT clock to be 12 MHz for the early console to work, and the clocks driver probes way too late. Signed-off-by: Paul Cercueil --- arch/mips/generic/board-ingenic.c | 57 +++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c index 7a4fce06875d..1f4906875e7b 100644 --- a/arch/mips/generic/board-ingenic.c +++ b/arch/mips/generic/board-ingenic.c @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -60,6 +61,50 @@ static __init char *ingenic_get_system_type(unsigned long machtype) } } +#define INGENIC_CGU_BASE 0x10000000 +#define JZ4750_CGU_CPCCR_ECS BIT(30) +#define JZ4760_CGU_CPCCR_ECS BIT(31) + +static __init void ingenic_force_12M_ext(const void *fdt, unsigned int mask) +{ + const __be32 *prop; + unsigned int cpccr; + void __iomem *cgu; + bool use_div; + int offset; + + offset = fdt_path_offset(fdt, "/ext"); + if (offset < 0) + return; + + prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); + if (!prop) + return; + + /* + * If the external oscillator is 24 MHz, enable the /2 divider to + * drive it down to 12 MHz, since this is what the hardware can work + * with. + * The 16 MHz cutoff value is arbitrary; setting it to 12 MHz would not + * work as the crystal frequency (as reported in the Device Tree) might + * be slightly above this value. + */ + use_div = be32_to_cpup(prop) >= 16000000; + + cgu = ioremap(INGENIC_CGU_BASE, 0x4); + if (!cgu) + return; + + cpccr = ioread32(cgu); + if (use_div) + cpccr |= mask; + else + cpccr &= ~mask; + iowrite32(cpccr, cgu); + + iounmap(cgu); +} + static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_data) { /* @@ -73,6 +118,18 @@ static __init const void *ingenic_fixup_fdt(const void *fdt, const void *match_d mips_machtype = (unsigned long)match_data; system_type = ingenic_get_system_type(mips_machtype); + switch (mips_machtype) { + case MACH_INGENIC_JZ4750: + case MACH_INGENIC_JZ4755: + ingenic_force_12M_ext(fdt, JZ4750_CGU_CPCCR_ECS); + break; + case MACH_INGENIC_JZ4760: + ingenic_force_12M_ext(fdt, JZ4760_CGU_CPCCR_ECS); + break; + default: + break; + } + return fdt; } From patchwork Sun Jun 4 12:26:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Cercueil X-Patchwork-Id: 13266599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 482F2C7EE23 for ; Sun, 4 Jun 2023 12:27:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231264AbjFDM1k (ORCPT ); Sun, 4 Jun 2023 08:27:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231213AbjFDM1g (ORCPT ); Sun, 4 Jun 2023 08:27:36 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F1411BF; Sun, 4 Jun 2023 05:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1685881633; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s1RJUCGj4nB1iNY8d5w8aIK40sAZLfxM8ksgaf5zRXc=; b=cPQrviulFS4Raq43BCRWx1X92wf5oie9PpfnuONQ1O9WBlIBs4bGm+zEjfv/TlHWHMrP0m w1g8C+Oe7vEwEoN/NXgKazr8ZnhNniDtFc55i7ELZtAkjQhvS1Y7ZHJaBI59wQWOr0Fj85 HsfTgp0jXbE2xhp81GiE3SlEPOC0CaM= From: Paul Cercueil To: Thomas Bogendoerfer Cc: Paul Burton , Siarhei Volkau , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, list@opendingux.net, Paul Cercueil , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org Subject: [PATCH 4/4] MIPS: DTS: qi_lb60: Don't use unit address for regulators Date: Sun, 4 Jun 2023 14:26:55 +0200 Message-Id: <20230604122655.69698-4-paul@crapouillou.net> In-Reply-To: <20230604122655.69698-1-paul@crapouillou.net> References: <20230604122655.69698-1-paul@crapouillou.net> MIME-Version: 1.0 X-Spam: Yes Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The regulators don't have any "reg" property, and therefore shouldn't use an unit address in their node names. Signed-off-by: Paul Cercueil --- Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: devicetree@vger.kernel.org --- arch/mips/boot/dts/ingenic/qi_lb60.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/qi_lb60.dts b/arch/mips/boot/dts/ingenic/qi_lb60.dts index ba0218971572..24f987244a12 100644 --- a/arch/mips/boot/dts/ingenic/qi_lb60.dts +++ b/arch/mips/boot/dts/ingenic/qi_lb60.dts @@ -27,7 +27,7 @@ chosen { stdout-path = &uart0; }; - vcc: regulator@0 { + vcc: regulator-0 { compatible = "regulator-fixed"; regulator-name = "vcc"; @@ -36,7 +36,7 @@ vcc: regulator@0 { regulator-always-on; }; - mmc_power: regulator@1 { + mmc_power: regulator-1 { compatible = "regulator-fixed"; regulator-name = "mmc_vcc"; gpio = <&gpd 2 0>; @@ -45,7 +45,7 @@ mmc_power: regulator@1 { regulator-max-microvolt = <3300000>; }; - amp_supply: regulator@2 { + amp_supply: regulator-2 { compatible = "regulator-fixed"; regulator-name = "amp_supply"; gpio = <&gpd 4 0>;