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Cc: qemu-stable@nongnu.org Fixes: 94bf2658676 ("target/ppc: Use atomic load for LQ and LQARX") Fixes: 57b38ffd0c6 ("target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ") Signed-off-by: Nicholas Piggin Reviewed-by: Richard Henderson --- v2: - Fix bugs vs memory access fault [Richard] target/ppc/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3650d2985d..7a5bf1d820 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3881,6 +3881,7 @@ static void gen_lqarx(DisasContext *ctx) tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); tcg_gen_extr_i128_i64(lo, hi, t16); + tcg_gen_mov_tl(cpu_reserve, EA); tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); } From patchwork Mon Jun 5 02:54:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13266851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 763F5C7EE2D for ; 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Sun, 04 Jun 2023 19:54:56 -0700 (PDT) Received: from wheely.local0.net ([203.221.142.9]) by smtp.gmail.com with ESMTPSA id q5-20020a170902c74500b001ae59169f05sm5316778plq.182.2023.06.04.19.54.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Jun 2023 19:54:56 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH v2 2/4] target/ppc: Ensure stcx size matches larx Date: Mon, 5 Jun 2023 12:54:43 +1000 Message-Id: <20230605025445.161932-2-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605025445.161932-1-npiggin@gmail.com> References: <20230605025445.161932-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=npiggin@gmail.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Differently-sized larx/stcx. pairs can succeed if the starting address matches. Add a check to require the size of stcx. exactly match the larx that established the reservation. Use the term "reserve_length" for this state, which matches the terminology used in the ISA. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- v2: - Changed lqarx/stqcx. reservation size to 16 [Richard] - Changed name to reserve_length [Richard] target/ppc/cpu.h | 5 +++-- target/ppc/cpu_init.c | 4 ++-- target/ppc/translate.c | 9 +++++++++ 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 7959bfed0a..45d84ce06a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1123,8 +1123,9 @@ struct CPUArchState { target_ulong ov32; target_ulong ca32; - target_ulong reserve_addr; /* Reservation address */ - target_ulong reserve_val; /* Reservation value */ + target_ulong reserve_addr; /* Reservation address */ + target_ulong reserve_length; /* Reservation larx op size (bytes) */ + target_ulong reserve_val; /* Reservation value */ target_ulong reserve_val2; /* These are used in supervisor mode only */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 944a74befe..c3dd7052a3 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7421,8 +7421,8 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) } qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); } - qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", - env->reserve_addr); + qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", + (int)env->reserve_length, env->reserve_addr); if (flags & CPU_DUMP_FPU) { for (i = 0; i < 32; i++) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 7a5bf1d820..538f757dec 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -71,6 +71,7 @@ static TCGv cpu_cfar; #endif static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; +static TCGv cpu_reserve_length; static TCGv cpu_reserve_val; static TCGv cpu_reserve_val2; static TCGv cpu_fpscr; @@ -141,6 +142,10 @@ void ppc_translate_init(void) cpu_reserve = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, reserve_addr), "reserve_addr"); + cpu_reserve_length = tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, + reserve_length), + "reserve_length"); cpu_reserve_val = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, reserve_val), "reserve_val"); @@ -3585,6 +3590,7 @@ static void gen_load_locked(DisasContext *ctx, MemOp memop) gen_addr_reg_index(ctx, t0); tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); tcg_gen_mov_tl(cpu_reserve, t0); + tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); tcg_gen_mov_tl(cpu_reserve_val, gpr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } @@ -3816,6 +3822,7 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop) gen_set_access_type(ctx, ACCESS_RES); gen_addr_reg_index(ctx, t0); tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), l1); t0 = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, @@ -3882,6 +3889,7 @@ static void gen_lqarx(DisasContext *ctx) tcg_gen_extr_i128_i64(lo, hi, t16); tcg_gen_mov_tl(cpu_reserve, EA); + tcg_gen_movi_tl(cpu_reserve_length, 16); tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); } @@ -3907,6 +3915,7 @@ static void gen_stqcx_(DisasContext *ctx) gen_addr_reg_index(ctx, EA); tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lab_fail); cmp = tcg_temp_new_i128(); val = tcg_temp_new_i128(); From patchwork Mon Jun 5 02:54:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13266852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B4CCC77B73 for ; Mon, 5 Jun 2023 02:56:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q60N8-0008JB-U6; Sun, 04 Jun 2023 22:55:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q60N6-0008In-Es; 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Sun, 04 Jun 2023 19:54:59 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH v2 3/4] target/ppc: Remove larx/stcx. memory barrier semantics Date: Mon, 5 Jun 2023 12:54:44 +1000 Message-Id: <20230605025445.161932-3-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605025445.161932-1-npiggin@gmail.com> References: <20230605025445.161932-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org larx and stcx. are not defined to order any memory operations. Remove the barriers. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- target/ppc/translate.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 538f757dec..acb99d8691 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3592,7 +3592,6 @@ static void gen_load_locked(DisasContext *ctx, MemOp memop) tcg_gen_mov_tl(cpu_reserve, t0); tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); tcg_gen_mov_tl(cpu_reserve_val, gpr); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); } #define LARX(name, memop) \ @@ -3836,11 +3835,6 @@ static void gen_conditional_store(DisasContext *ctx, MemOp memop) gen_set_label(l1); - /* - * Address mismatch implies failure. But we still need to provide - * the memory barrier semantics of the instruction. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); gen_set_label(l2); @@ -3944,11 +3938,6 @@ static void gen_stqcx_(DisasContext *ctx) tcg_gen_br(lab_over); gen_set_label(lab_fail); - /* - * Address mismatch implies failure. But we still need to provide - * the memory barrier semantics of the instruction. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); gen_set_label(lab_over); From patchwork Mon Jun 5 02:54:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13266853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E493AC7EE2C for ; Mon, 5 Jun 2023 02:56:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q60NE-0008KH-26; Sun, 04 Jun 2023 22:55:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q60NA-0008Jw-CN; Sun, 04 Jun 2023 22:55:09 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q60N8-0002lc-JM; Sun, 04 Jun 2023 22:55:08 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1b0424c5137so37867185ad.1; Sun, 04 Jun 2023 19:55:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685933704; x=1688525704; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H20rRWKHpUByaL9Luvoyr4JNaBAvvzn8iPUUfaQ3Ss0=; b=iKydRJz/5Pg8xh6gQNi1Wz66drXyW7pRFfW/iP+0sejwNAYJWroYXW/l1r1pfodeg5 i9s0LdTi87UJ8eiLwud22ULZ98pzqvOtFhPZNSSpF6GDxo6tdpoaTqRbPxhZoFuMJkeq 2tgsBc7aec8JlKyd3nEDQG9GpvEicmWcjYPgdOR+TydcDYHnAz3E1S0kzapbQik01QIq rTAGyvUGBD3kpHTRoC2AxobBGVwO2RuVvJAwwfxKN+5u5zzqkkQid/kV8SLdJx1XNBWY 0zesye0rwOiGUKXURhFcws8x0kz+SPPxLXeQkcQMBUhbkoQ7q251x/ahI785vaxBVVKJ IKpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685933704; x=1688525704; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H20rRWKHpUByaL9Luvoyr4JNaBAvvzn8iPUUfaQ3Ss0=; b=cowfCunJAxGYSWlWaqyT6M4Ib5b56D7cko7uRdgoz4DEvxkdV7wjX4W1lN5KpxIrjY u/gG9pih2Y4Mzjl0MwRkXNx0yNofNz5VV5C9cOvPxR0ujun4sdhg34sFmXSimOGp4uw+ Eelp99jVdCpCKER1eb4x+C7Fu3dzCW3gZxSe3xLGr5TnqeWySsKjEmopP5F3mHfUiog9 es5J3toXc8snLUgzqQWoolCaybEbM3+yfuW3u6X0V25ALVh5wz6bhFMDhh6o2Hg/mfVi bOQLQNejzw/wjIdy00rSy6YaHnZdajGhviEmB/siIjYq8rFX5A2ycLDigAYSlEeCpyE2 fXoA== X-Gm-Message-State: AC+VfDwAk72oufjlgNzxPO18DH3LmyElmva/hc9Eaxl/ODYHUtMH9wQ1 Ml57o9q4nj2P+e0iylbXO1Y9ggwNkH0= X-Google-Smtp-Source: ACHHUZ6pbg5+Cr7WeLVNdWTlt64kBR/NceU8FS5NyWDMr5ylHQJ1w6ookdnwODu06QLtpoXmxYrZ/Q== X-Received: by 2002:a17:902:c40f:b0:1b1:c72c:753f with SMTP id k15-20020a170902c40f00b001b1c72c753fmr8433631plk.59.1685933704188; Sun, 04 Jun 2023 19:55:04 -0700 (PDT) Received: from wheely.local0.net ([203.221.142.9]) by smtp.gmail.com with ESMTPSA id q5-20020a170902c74500b001ae59169f05sm5316778plq.182.2023.06.04.19.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Jun 2023 19:55:03 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH v2 4/4] target/ppc: Rework store conditional to avoid branch Date: Mon, 5 Jun 2023 12:54:45 +1000 Message-Id: <20230605025445.161932-4-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605025445.161932-1-npiggin@gmail.com> References: <20230605025445.161932-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=npiggin@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rework store conditional to avoid a branch in the success case. Change some of the variable names and layout while here so gen_conditional_store more closely matches gen_stqcx_. Reviewed-by: Richard Henderson Signed-off-by: Nicholas Piggin --- v2: - Reinstate lost DEF_MEMOP [Richard] I think the DEF_MEMOP is redundant here, but admit that's not something that should be changed with this patch. I will look at cleaning those up later. Thanks, Nick target/ppc/translate.c | 63 ++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 33 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index acb99d8691..434caad258 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3813,31 +3813,32 @@ static void gen_stdat(DisasContext *ctx) static void gen_conditional_store(DisasContext *ctx, MemOp memop) { - TCGLabel *l1 = gen_new_label(); - TCGLabel *l2 = gen_new_label(); - TCGv t0 = tcg_temp_new(); - int reg = rS(ctx->opcode); + TCGLabel *lfail; + TCGv EA; + TCGv cr0; + TCGv t0; + int rs = rS(ctx->opcode); + lfail = gen_new_label(); + EA = tcg_temp_new(); + cr0 = tcg_temp_new(); + t0 = tcg_temp_new(); + + tcg_gen_mov_tl(cr0, cpu_so); gen_set_access_type(ctx, ACCESS_RES); - gen_addr_reg_index(ctx, t0); - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), l1); + gen_addr_reg_index(ctx, EA); + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); - t0 = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, - cpu_gpr[reg], ctx->mem_idx, + cpu_gpr[rs], ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN); tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(t0, t0, cpu_so); - tcg_gen_trunc_tl_i32(cpu_crf[0], t0); - tcg_gen_br(l2); + tcg_gen_or_tl(cr0, cr0, t0); - gen_set_label(l1); - - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - - gen_set_label(l2); + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); tcg_gen_movi_tl(cpu_reserve, -1); } @@ -3891,25 +3892,26 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { - TCGLabel *lab_fail, *lab_over; - int rs = rS(ctx->opcode); + TCGLabel *lfail; TCGv EA, t0, t1; + TCGv cr0; TCGv_i128 cmp, val; + int rs = rS(ctx->opcode); if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } - lab_fail = gen_new_label(); - lab_over = gen_new_label(); + lfail = gen_new_label(); + EA = tcg_temp_new(); + cr0 = tcg_temp_new(); + tcg_gen_mov_tl(cr0, cpu_so); gen_set_access_type(ctx, ACCESS_RES); - EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); - - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lab_fail); + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); cmp = tcg_temp_new_i128(); val = tcg_temp_new_i128(); @@ -3932,15 +3934,10 @@ static void gen_stqcx_(DisasContext *ctx) tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); - tcg_gen_or_tl(t0, t0, cpu_so); - tcg_gen_trunc_tl_i32(cpu_crf[0], t0); - - tcg_gen_br(lab_over); - gen_set_label(lab_fail); - - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + tcg_gen_or_tl(cr0, cr0, t0); - gen_set_label(lab_over); + gen_set_label(lfail); + tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); tcg_gen_movi_tl(cpu_reserve, -1); } #endif /* defined(TARGET_PPC64) */