From patchwork Mon Jun 5 11:06:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39FF0C7EE2F for ; Mon, 5 Jun 2023 15:40:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230324AbjFEPj7 (ORCPT ); Mon, 5 Jun 2023 11:39:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234824AbjFEPjo (ORCPT ); Mon, 5 Jun 2023 11:39:44 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A21F103 for ; Mon, 5 Jun 2023 08:39:42 -0700 (PDT) Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-53482b44007so2510655a12.2 for ; Mon, 05 Jun 2023 08:39:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979582; x=1688571582; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=xZD7AFVtobxh1FGjEKQD2QW8IDIT5bzbSx/S1GQl+8U=; b=ThHvOBpo59by52p4+jOSX8l8hNtU/M+FRtpBWS5wO9S1Ftj+KDeHvoi4qxb6y5lLlA klRc1tpT6wmq9fEsliWnmRX6vlH8Kc+bCJRFfGkoRHshaIALNsYdCc2xbs2FlgkuVE+a 9NtsfsFMHlAHzOxpaytXXVIKMf5ZnmvEqVZr3WNtAXnIt8o5kGu12PeWcnv4ioXbSMuf jN/C83ZeDQ0qQxTYfKWRRByNKh5d0S+3cEsHH8UKRVCG5lbq8T8G22yixHNLydlJssXu xa6hUsw3HQ2NufRvFPAxAU702WJccbvy4Ho1ymVAmBN/78Xpr0SiOoVA+8OmGWfUUcX3 cS8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979582; x=1688571582; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xZD7AFVtobxh1FGjEKQD2QW8IDIT5bzbSx/S1GQl+8U=; b=Li5M6f9Ty2Nmu+7y6/gtbppJgk4COLtf3T/J6iFFW3Az15zmvnlnigMmoMpInivIHG 44zvJw7qZrdS4tzhX2hKN13nJ2hK/OcvzZ+9uVHULibrVOQdDajhUlfDZyYNK6ZbslRp itjKmbRgTtI+Wku2cvogMtG799tb2ZvBG8/jDx7ms02Vt2OKkiR6fJMCXmUYx3BF9ZO4 qbmQrOoI0jYnWdoPLiS+FrRO5S7MK8Of2IdmjKxp4IAZZLrSyiy4hBStpl29IMpYzJK/ LZZYUJS19J7i7DHC+NFL3Qupzem9ZNVlrGdplLm0Ag1vdvq9z4N0CqkRY1D2UQP/SfIG dZhA== X-Gm-Message-State: AC+VfDzI4KevJ5zgQaClwcNyrc63ygDq9CgYoLvNraoXhvKpf3g84SOl +N917VwsjYqzJ4582TCEM+225Q== X-Google-Smtp-Source: ACHHUZ72dieQPrM1WO2qg0OnZlgNQI7fj+3mSJL13ptwQ3koIpZJKneVebsItPgSW3CMo5AGhAYPcg== X-Received: by 2002:a17:902:f68a:b0:1ae:626b:4771 with SMTP id l10-20020a170902f68a00b001ae626b4771mr4573871plg.36.1685979581841; Mon, 05 Jun 2023 08:39:41 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.39.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:39:41 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Guo Ren , Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Guo Ren , Conor Dooley , Jisheng Zhang Subject: [PATCH -next v21 01/27] riscv: Rename __switch_to_aux() -> fpu Date: Mon, 5 Jun 2023 11:06:58 +0000 Message-Id: <20230605110724.21391-2-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren The name of __switch_to_aux() is not clear and rename it with the determine function: __switch_to_fpu(). Next we could add other regs' switch. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Signed-off-by: Greentime Hu Reviewed-by: Anup Patel Reviewed-by: Palmer Dabbelt Signed-off-by: Andy Chiu Tested-by: Heiko Stuebner Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/include/asm/switch_to.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 60f8ca01d36e..4b96b13dee27 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -46,7 +46,7 @@ static inline void fstate_restore(struct task_struct *task, } } -static inline void __switch_to_aux(struct task_struct *prev, +static inline void __switch_to_fpu(struct task_struct *prev, struct task_struct *next) { struct pt_regs *regs; @@ -66,7 +66,7 @@ static __always_inline bool has_fpu(void) static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) #define fstate_restore(task, regs) do { } while (0) -#define __switch_to_aux(__prev, __next) do { } while (0) +#define __switch_to_fpu(__prev, __next) do { } while (0) #endif extern struct task_struct *__switch_to(struct task_struct *, @@ -77,7 +77,7 @@ do { \ struct task_struct *__prev = (prev); \ struct task_struct *__next = (next); \ if (has_fpu()) \ - __switch_to_aux(__prev, __next); \ + __switch_to_fpu(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) From patchwork Mon Jun 5 11:06:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 156EBC7EE2C for ; Mon, 5 Jun 2023 15:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234545AbjFEPj5 (ORCPT ); Mon, 5 Jun 2023 11:39:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234935AbjFEPjx (ORCPT ); Mon, 5 Jun 2023 11:39:53 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13B65F7 for ; Mon, 5 Jun 2023 08:39:51 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1b02d0942caso22477275ad.1 for ; Mon, 05 Jun 2023 08:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979590; x=1688571590; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=QTuL2uiI0oFuPEE6djzm9/PdbC+T6hk/9J64Mz+FPUg=; b=ZhP8GjWEpGFoayG38V5gvFyNU8chjofIbB/n0RNUU/iMJM81Ux4LoiFJDPWjmeBbOi SZnF6FLwqVoWo23YTZGnROW6cGlIJAfo8nlF+ho21iZP1nw5dLmdA3GtaOWizicz7LVi IeQbbknQb1HhK7mPHziObWBIp9DmhImbOP0FNLs2D8rSWVnVaY256cEoWLaqkFhO6e2B dSXpi/6VfR9NSQd8RnNZkTmLSQnmfS8VwpoK6LmViKcIW/wo9cf+vxHps60i7aJvmziy 6XuOXzqAUrkNDI9wFxmlYbcOwgJ50foR9bQgel3VwyTmFTlrO+uByafyiYfr7orr+N3V OEIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979590; x=1688571590; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=QTuL2uiI0oFuPEE6djzm9/PdbC+T6hk/9J64Mz+FPUg=; b=Nx/jhNct3Qr2wY39JfJ4FKr2f9wFx/u3AFWozNX03OYLCO5zRp9GApdg8+DYHGNUx0 LYwvrd2f6gHgvzPShZZaoUyf7WEjL7yketKaoKCMR2oZLLmMYNJnLm2bmRR49LUv1No0 /4SpJJsYYZQWGgpE72ooJkG/dZASYqJbceotNTSwei1B8fSYpfl1Sqw0DUQg9GsVppT5 xLXa5u4WXzlNuuHMXOEJjwmXADKoLa68QK3P+Kx3J4TTAs6bMfAdBMvfW93Cni4CCsWL pkSK8UHCXqCC/yaPvXaAVPUM2iBRKsAJJ6byH8wAtls4MF9/IJvkilTPfGbVB40fhA6h y57Q== X-Gm-Message-State: AC+VfDzR8b59nHx+MfowMLCvHOLYKVrwo52DKznGVwHM+79/VYJXqIWV fNFUV15R7mOZEdw///FOYvZ9rQ== X-Google-Smtp-Source: ACHHUZ5iCIIsrXrKTV4YvyRboc0MLsM11Lz4h8qRpKBqgpdjkuJM73cXRy4Xbnn6WlDgx2Wd7WCO0w== X-Received: by 2002:a17:902:e850:b0:1b0:fd8:e693 with SMTP id t16-20020a170902e85000b001b00fd8e693mr3879112plg.7.1685979590559; Mon, 05 Jun 2023 08:39:50 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.39.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:39:49 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Guo Ren , Andy Chiu , Paul Walmsley , Albert Ou , Conor Dooley , Andrew Jones , Heiko Stuebner , Anup Patel , Jisheng Zhang , Vincent Chen , Guo Ren Subject: [PATCH -next v21 02/27] riscv: Extending cpufeature.c to detect V-extension Date: Mon, 5 Jun 2023 11:06:59 +0000 Message-Id: <20230605110724.21391-3-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren Add V-extension into riscv_isa_ext_keys array and detect it with isa string parsing. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Signed-off-by: Greentime Hu Suggested-by: Vineet Gupta Co-developed-by: Andy Chiu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Palmer Dabbelt --- Changelog v20: s/riscv_has_extension_likely/riscv_has_extension_unlikely/ (Palmer) --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/vector.h | 26 ++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 11 +++++++++++ 4 files changed, 39 insertions(+) create mode 100644 arch/riscv/include/asm/vector.h diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e0c40a4c63d5..574385930ba7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -22,6 +22,7 @@ #define RISCV_ISA_EXT_m ('m' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') +#define RISCV_ISA_EXT_v ('v' - 'a') /* * These macros represent the logical IDs of each multi-letter RISC-V ISA diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h new file mode 100644 index 000000000000..bdbb05b70151 --- /dev/null +++ b/arch/riscv/include/asm/vector.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2020 SiFive + */ + +#ifndef __ASM_RISCV_VECTOR_H +#define __ASM_RISCV_VECTOR_H + +#include + +#ifdef CONFIG_RISCV_ISA_V + +#include + +static __always_inline bool has_vector(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); +} + +#else /* ! CONFIG_RISCV_ISA_V */ + +static __always_inline bool has_vector(void) { return false; } + +#endif /* CONFIG_RISCV_ISA_V */ + +#endif /* ! __ASM_RISCV_VECTOR_H */ diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..c52bb7bbbabe 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -21,5 +21,6 @@ #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) #endif /* _UAPI_ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b1d6b7e4b829..7aaf92fff64e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -107,6 +107,7 @@ void __init riscv_fill_hwcap(void) isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; elf_hwcap = 0; @@ -267,6 +268,16 @@ void __init riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + /* + * ISA string in device tree might have 'v' flag, but + * CONFIG_RISCV_ISA_V is disabled in kernel. + * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. + */ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; + } + memset(print_str, 0, sizeof(print_str)); for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) From patchwork Mon Jun 5 11:07:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D182EC7EE23 for ; Mon, 5 Jun 2023 15:40:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232812AbjFEPkK (ORCPT ); Mon, 5 Jun 2023 11:40:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234707AbjFEPj7 (ORCPT ); Mon, 5 Jun 2023 11:39:59 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5238F7 for ; Mon, 5 Jun 2023 08:39:58 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1b00ecabdf2so45869935ad.2 for ; Mon, 05 Jun 2023 08:39:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979598; x=1688571598; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=3y8ZxaitI4vDMB0+bZfjoHdHul+aXR4kvCb6HBDbSsk=; b=JaqNg7sN/e7gIeih2uZhtfREFG2IH1olkhz63U6B6sCbbDXJ+OSaBFdImVqpTtz7dQ k7dh1Kj3qgCbGUwraqgZGgGxaTIc6oX9sYPr1SVxsEbXdCwqE/9QQkgyIb6IcRTqvumO 7n4xeE37coXrJ431vwE9t4gOlstc/yaKtSMg026KWweGp9qc6qDenmzprcxJdC4pgktU KFBdLVfhS9+755LCUU+/m+C+SW7Xn+C9lThCIaQ48tHJQ3jDNH2szJaoWf2GRnhArOvK 0OaSEoMvpudVAuesI1tkV0oZqmvO79O6POYuNbVc1r4XHZlhfGaXBVw6OpLv3qdwf/pV jxpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979598; x=1688571598; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=3y8ZxaitI4vDMB0+bZfjoHdHul+aXR4kvCb6HBDbSsk=; b=RL0c1VIwqY4mABq+SQOBmCm6cQo2XnlV+1RkX9LT6hB+s0dsZGGztW1Hq6q+kxs30R 200vhlESXlUdW9WsqtPJPExDl0mRMeQGzoG5lSgcNRP35G0HtIFeiquk4ab2oYSDk1QH J3qA6jztDLtbVb+8lUErd4zLDWFsHnTp8w0VUheMa3Px7hUhU9xSc2o/54UbaDRslPet 6v62BwhiCA+fMFo7OSI3YOaDgbM0O4Mcy4zZOintocL/7YPVvOF/YPF4EoazaHvsnlrx eM6ZTIWu3zrhvW/+OOQaauu++2qvT6Gse7Pr5nCJrphf2ZVIs4tUazlbIFZRyJUkGZ34 tJ5g== X-Gm-Message-State: AC+VfDxs1clBpIpo/I4lS/6D3CTUfK4fq2zTPLgH2P5tgRI3wIZnqQwL rYezXe69lbBa/m7nRH6bYGKbwg== X-Google-Smtp-Source: ACHHUZ6VLVHTULzJC3UwlOIGxh1xz1Hej5pdJKL54f/HWuLX+oy5kWMBPi/AnZJSJIE42NhnPdD6dQ== X-Received: by 2002:a17:903:41c7:b0:1a1:b3bb:cd5b with SMTP id u7-20020a17090341c700b001a1b3bbcd5bmr9720134ple.62.1685979598362; Mon, 05 Jun 2023 08:39:58 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.39.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:39:57 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Jonathan Corbet , Paul Walmsley , Albert Ou , Heiko Stuebner , Evan Green , Conor Dooley , Andrew Jones , Celeste Liu , Andrew Bresticker Subject: [PATCH -next v21 03/27] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 Date: Mon, 5 Jun 2023 11:07:00 +0000 Message-Id: <20230605110724.21391-4-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Probing kernel support for Vector extension is available now. This only add detection for V only. Extenions like Zvfh, Zk are not in this scope. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Evan Green Reviewed-by: Palmer Dabbelt Reviewed-by: Heiko Stuebner --- Changelog v20: - Fix a typo in document, and remove duplicated probes (Heiko) - probe V extension in RISCV_HWPROBE_KEY_IMA_EXT_0 key only (Palmer, Evan) --- Documentation/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 4 ++++ 3 files changed, 8 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 9f0dd62dcb5d..7431d9d01c73 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -64,6 +64,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. + * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by + version 1.0 of the RISC-V Vector extension manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 8d745a4ad8a2..7c6fdcf7ced5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_IMA_V (1 << 2) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5db29683ebee..88357a848797 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -171,6 +172,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, if (riscv_isa_extension_available(NULL, c)) pair->value |= RISCV_HWPROBE_IMA_C; + if (has_vector()) + pair->value |= RISCV_HWPROBE_IMA_V; + break; case RISCV_HWPROBE_KEY_CPUPERF_0: From patchwork Mon Jun 5 11:07:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1072CC7EE2D for ; Mon, 5 Jun 2023 15:40:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234863AbjFEPkL (ORCPT ); Mon, 5 Jun 2023 11:40:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234301AbjFEPkH (ORCPT ); Mon, 5 Jun 2023 11:40:07 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34F3E10A for ; Mon, 5 Jun 2023 08:40:03 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1b0236ee816so35850765ad.1 for ; Mon, 05 Jun 2023 08:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979602; x=1688571602; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=d1t0mcJTBhtsZBYqWTjUk/5U+5ffoYMHXYjoCjqrD1Y=; b=hLdQHV3mhu7NrU7gLSA+e3puQfnjTRlWFg2kePX+RJDYCD5Px3f1yC+TretEeMOzG/ fhkMPKSl5gybiIwJpnXwM8y3zWz7VFwZuDNsgaOxpNHniTlB7qJt6O7T5cfZhANKOBWJ iyX829rvWPljpKWsazgogJqwIuq/gyS+ShhCbN0NFRaDfS2EAUSOtLXX+pT5GHIKYJqL 8TQg37t6ZBGfO6N639D+ixjv/4keIoxVNMitaVNIHVTDYuap4A2IidHFeNHdwfQgk8qQ 3/K7QMtF/Xtq/ouXJkBY7GyyZw88mqinRofO0i24tkRdD/8xFFONMXThaFS4Skezd+Cq UxTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979603; x=1688571603; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=d1t0mcJTBhtsZBYqWTjUk/5U+5ffoYMHXYjoCjqrD1Y=; b=HSCHdq4haL2BuG3WaogusJEYaf9e+RrOsjoNQjno8HNstA/8PiTzjZBkhs2h4iFSRV lHXqt1qDntglAmLGY1ivTgZLTHQBLJiUrAV2ZhbMyjhDF6RRAUHi6e/hODAEhS//r5tB qNSDO7q8agzBaSsf9Hmryf/3qB7FYbYLIbH07CDSNflItOkKMwmNeJVK2zwsiPpUDz8A NZAmJtCHPZIdUN94JfXlTcCiGSZsODJXcwWVjv8qp0byY1QJfrrZMKpOYowa96y5gOk7 RsHT9gmN7IZfpF5iw2zW884oVnzkuPjl0thdOcDzSZktlObMWuUyHQYFAHZWeMVjrmsj dDCQ== X-Gm-Message-State: AC+VfDzPnkPSDDqGExCMc2T3Kpsbg5xveyxmFxrW4wKBuiRw4NuhLoRd 58+ufyMI/HgVpNtHuQKg1EmEjw== X-Google-Smtp-Source: ACHHUZ4biNRG8kD3a9Fs8sx7VC+IQ8g8hB5i4oIU0XWsT6nRq3hDin/sLuRVSx2ZBcuwL9/OkWm9jA== X-Received: by 2002:a17:903:189:b0:1b1:76c2:2966 with SMTP id z9-20020a170903018900b001b176c22966mr8471125plg.20.1685979602723; Mon, 05 Jun 2023 08:40:02 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:02 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Anup Patel , Guo Ren , Atish Patra , Heiko Stuebner Subject: [PATCH -next v21 04/27] riscv: Add new csr defines related to vector extension Date: Mon, 5 Jun 2023 11:07:01 +0000 Message-Id: <20230605110724.21391-5-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu Follow the riscv vector spec to add new csr numbers. Acked-by: Guo Ren Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Reviewed-by: Palmer Dabbelt Suggested-by: Vineet Gupta Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/include/asm/csr.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index b6acb7ed115f..b98b3b6c9da2 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -24,16 +24,24 @@ #define SR_FS_CLEAN _AC(0x00004000, UL) #define SR_FS_DIRTY _AC(0x00006000, UL) +#define SR_VS _AC(0x00000600, UL) /* Vector Status */ +#define SR_VS_OFF _AC(0x00000000, UL) +#define SR_VS_INITIAL _AC(0x00000200, UL) +#define SR_VS_CLEAN _AC(0x00000400, UL) +#define SR_VS_DIRTY _AC(0x00000600, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) #define SR_XS_CLEAN _AC(0x00010000, UL) #define SR_XS_DIRTY _AC(0x00018000, UL) +#define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ + #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ #endif #ifdef CONFIG_64BIT @@ -375,6 +383,12 @@ #define CSR_MVIPH 0x319 #define CSR_MIPH 0x354 +#define CSR_VSTART 0x8 +#define CSR_VCSR 0xf +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 + #ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE From patchwork Mon Jun 5 11:07:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89178C7EE24 for ; Mon, 5 Jun 2023 15:40:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234898AbjFEPkQ (ORCPT ); Mon, 5 Jun 2023 11:40:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233845AbjFEPkJ (ORCPT ); Mon, 5 Jun 2023 11:40:09 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FF8118E for ; Mon, 5 Jun 2023 08:40:07 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1b01dac1a82so24970465ad.2 for ; Mon, 05 Jun 2023 08:40:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979607; x=1688571607; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=peA7uNBICYxq78TCCLilok9fr+B5gTYL7MG+xHpLNFU=; b=RFh4xAkvYh3f6QR+0XxnxTmnNZRh6PgSSh0DDSPDE2PjLKjQokrhAYmYM5dILHmT2u tdSPgkHZiI8CmClOVVxAULvfDeIbjr8jgO3uD4jLNGrSufutHHAziJXxKCQW8OGX7KgC svpNkOdKQImWBoYlOc3uNdgyZ/4OLsAEbwZrctVF05JaMmLTw2JLLE07biXaKWdXU9gG An2uwwe+AI9eY2IGufvCqOqVCE/LGcBcImLt0r98qPSBE0hxN3jF0/aOitmiaV+pSGuw RaoxlggCBAIczXH9A0UCHRR9xRBTQ480h6WZt9E5JZHTfdbHdYiLfUQLShQlwcIHlgYU lemw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979607; x=1688571607; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=peA7uNBICYxq78TCCLilok9fr+B5gTYL7MG+xHpLNFU=; b=aS6+zcZ2WA/lfhRSz94nw+muzlLwJ3x5DzDcatKA2UWky+p5sJ3UINTrbIu6D2fT6v Qa/i0Th2Svsvsn8rJwfyo2XX3NPJkDQWArQA789joZUidhmA58E86fehIj4hP2u4eXNW Tv5hLDzs+ITiIIykNbkrP6zRC0o3ukB9mhiMs0URFJ/2pph9ND6Y9EjR7U6issW4kzGW H0SnZoeAyh6eZZzMwURFKoyH8dGqw+3xV7+Ib7ESoBz2N8OTEWWNyA3mmBPBnwzxnu3b 97vZMUXIdLXI7qU/ueVeH0TGR6cmw1vSVnqQjlhYd7erOIMbPucILl0HxpFUJhlD2e2U 784Q== X-Gm-Message-State: AC+VfDxOI8l1i5LUiBjbQkrd9y0FDx6Auxg64UfXGRTW8UrJz/+e0bNz sOFC8+eGv5N6sAIJ4C56TwChMg== X-Google-Smtp-Source: ACHHUZ7gYODQ3SKlK35nN9OhEisobMlQaL3fKtJqvAH701pPC6rDPo6Jb5H+GX2b1PvrbT1TdvrUXQ== X-Received: by 2002:a17:902:fe01:b0:1b0:307c:e6fe with SMTP id g1-20020a170902fe0100b001b0307ce6femr3421831plj.10.1685979607093; Mon, 05 Jun 2023 08:40:07 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:06 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Vincent Chen , Conor Dooley , Masahiro Yamada , Guo Ren Subject: [PATCH -next v21 05/27] riscv: Clear vector regfile on bootup Date: Mon, 5 Jun 2023 11:07:02 +0000 Message-Id: <20230605110724.21391-6-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu clear vector registers on boot if kernel supports V. Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta Signed-off-by: Andy Chiu Acked-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4bf6c449d78b..3fd6a4bd9c3e 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -392,7 +392,7 @@ ENTRY(reset_regs) #ifdef CONFIG_FPU csrr t0, CSR_MISA andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) - beqz t0, .Lreset_regs_done + beqz t0, .Lreset_regs_done_fpu li t1, SR_FS csrs CSR_STATUS, t1 @@ -430,8 +430,31 @@ ENTRY(reset_regs) fmv.s.x f31, zero csrw fcsr, 0 /* note that the caller must clear SR_FS */ +.Lreset_regs_done_fpu: #endif /* CONFIG_FPU */ -.Lreset_regs_done: + +#ifdef CONFIG_RISCV_ISA_V + csrr t0, CSR_MISA + li t1, COMPAT_HWCAP_ISA_V + and t0, t0, t1 + beqz t0, .Lreset_regs_done_vector + + /* + * Clear vector registers and reset vcsr + * VLMAX has a defined value, VLEN is a constant, + * and this form of vsetvli is defined to set vl to VLMAX. + */ + li t1, SR_VS + csrs CSR_STATUS, t1 + csrs CSR_VCSR, x0 + vsetvli t1, x0, e8, m8, ta, ma + vmv.v.i v0, 0 + vmv.v.i v8, 0 + vmv.v.i v16, 0 + vmv.v.i v24, 0 + /* note that the caller must clear SR_VS */ +.Lreset_regs_done_vector: +#endif /* CONFIG_RISCV_ISA_V */ ret END(reset_regs) #endif /* CONFIG_RISCV_M_MODE */ From patchwork Mon Jun 5 11:07:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 898B2C7EE2C for ; Mon, 5 Jun 2023 15:40:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233258AbjFEPkb (ORCPT ); Mon, 5 Jun 2023 11:40:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234868AbjFEPkW (ORCPT ); Mon, 5 Jun 2023 11:40:22 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD1CF131 for ; Mon, 5 Jun 2023 08:40:13 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-53f9a376f3eso4371515a12.0 for ; Mon, 05 Jun 2023 08:40:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979613; x=1688571613; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=FRXZE7cUr4vJpRYfnGIy+KdEpJQsKyQubDyjJds5WmA=; b=KXDBMuXNRHN6JZLLghcXJyvyn1zh00oaVAe1p59PxzuFAYdYJ8f27/TP1uvAINptqH nlcYcAkf+nJGFg9F+LyYqP0Ymo2Lij+XAmL0HH+Cqp92M6UdeXErSfZ7PYKmP7rYsaA6 7GQoibFMEo+e9BZCqbS77OBneeYePiXGgsN12CiPPQCRazNM4xoQ/iFocSjGVEZmK4M7 tkZUw2BhKyzNhLADu9McrKQmlX9tJTB5AleLiuKcPRH3GudtLqADDazxwOcVuo1Jex4Q B2gRWXR2EXEvHqK1khlKXmReI3jvkYgACmQxyQZlHagbbk77z2fEM87K1RP76tszm8cl cXoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979613; x=1688571613; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=FRXZE7cUr4vJpRYfnGIy+KdEpJQsKyQubDyjJds5WmA=; b=PyrNaepIndIhIpKe2ZjrTdYm8pLyoVe1AJqy/D1YKGogUwgdDmNb/GlGEdbI+ykU5w knd94OzwtGPnmdeIcIoAnY03xSTGMmYvqnIUclT+Aeyj2dMHGdcejBBTmK6Ptk9UNVpH myk+vQ0M6zm7HoA1eFviQKT+Ld0C16spELMSJiFWuzalZGESBD39lpn7DNlwXExPuhGe zX01vWdYP1uv7eE8Yy/XXR5On0pFQGES4EotzWkWvkuLuKjRhTnnZkoBsaJM9Rn1rbRa L2Jf41gOVmMNTK50WtUKIgTxfLUDsPVtzw/LOlw85w/yRJ7Yv+wR7TqpknQjs9yvKECF aKbg== X-Gm-Message-State: AC+VfDw8ECMgtj1MtWqkuKAIrc5D62PNxY3cE6fGRW9ZLq/w3DcIaXzI ZyIBC4lnKdEH04qQw3bpL4krRA== X-Google-Smtp-Source: ACHHUZ4j8vLA1CQX4UCgLtGjbolr0/w7QSNG9j2AAzYc8zViCUwWht91Jm831ibcZIARgx8zaguymA== X-Received: by 2002:a17:902:d506:b0:1b1:9233:bbf5 with SMTP id b6-20020a170902d50600b001b19233bbf5mr10010498plg.57.1685979613098; Mon, 05 Jun 2023 08:40:13 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:12 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Han-Kuan Chen , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Nicolas Saenz Julienne , Jisheng Zhang , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Frederic Weisbecker , Andrew Bresticker , Heiko Stuebner , Conor Dooley , Masahiro Yamada Subject: [PATCH -next v21 06/27] riscv: Disable Vector Instructions for kernel itself Date: Mon, 5 Jun 2023 11:07:03 +0000 Message-Id: <20230605110724.21391-7-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren Disable vector instructions execution for kernel mode at its entrances. This helps find illegal uses of vector in the kernel space, which is similar to the fpu. Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Han-Kuan Chen Signed-off-by: Han-Kuan Chen Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Palmer Dabbelt --- Changelog V19: - Add description in commit msg (Heiko's suggestion on v17) --- arch/riscv/kernel/entry.S | 6 +++--- arch/riscv/kernel/head.S | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 3fbb100bc9e4..e9ae284a55c1 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -48,10 +48,10 @@ _save_context: * Disable user-mode memory access as it should only be set in the * actual user copy routines. * - * Disable the FPU to detect illegal usage of floating point in kernel - * space. + * Disable the FPU/Vector to detect illegal usage of floating point + * or vector in kernel space. */ - li t0, SR_SUM | SR_FS + li t0, SR_SUM | SR_FS_VS REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3fd6a4bd9c3e..e16bb2185d55 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -140,10 +140,10 @@ secondary_start_sbi: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 /* Set trap vector to spin forever to help debug */ @@ -234,10 +234,10 @@ pmp_done: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 #ifdef CONFIG_RISCV_BOOT_SPINWAIT From patchwork Mon Jun 5 11:07:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD19AC7EE2F for ; Mon, 5 Jun 2023 15:40:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234915AbjFEPkg (ORCPT ); Mon, 5 Jun 2023 11:40:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234917AbjFEPk0 (ORCPT ); Mon, 5 Jun 2023 11:40:26 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F91D18E for ; Mon, 5 Jun 2023 08:40:18 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1b04782fe07so25690585ad.3 for ; Mon, 05 Jun 2023 08:40:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979617; x=1688571617; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=EvrLPd1cTqQ0pEVjiT8YUKSvx/1xPgu8clZhUQSofCQ=; b=GLGpLSOO2XQGnAjD+WTSHwZSoz7d6GqWYDdRRuaFM0fOXgUKJjD/vDh+BPvkA/RgyU 685CXX6eIHuTbnIUzRxlQybayn8cRJM2+Xz+RvF9qfWKesDHBItFu9Z29l1Jp9/sEwIK NDZR5kWj6facZIXcTG8CaaattaKnUv9kDlSTnQ21Bd7TBZqx4z/9xRNAw1/CRtiX9SqL UUfDoiu02MWoCs+dBtUtAIobuD5akmfGI9NXiQfMwO9XmZ0qH1X80TlyAGpBLfHZQrBN no+/MLmmn3PKtBmXm1fF/hw1H6IzIJriTRSqWrbgGHnNtULrHKYTZE6x1zccrxa0RPGI FPmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979617; x=1688571617; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=EvrLPd1cTqQ0pEVjiT8YUKSvx/1xPgu8clZhUQSofCQ=; b=Nfcqu37eMT6ZG5UpMivAsseRrrQyh5XFS3oUWM3nxiuiEtHNt3JyCKPfJaVrds2Kjt sDwOFITKvgvQdUPiHTMjQpmNrsqYrYFB8XVIp71Ihg1VDxIMbmvHeeXbGZshM0h2GoNV 2r0Ka5aT6vaN/Cr1g60Rn5eA+Vgn/o/ebWZioQGTyZTejf9CdhwWXStVVZgO9ISO2hku GXO7bBTkqPRlrau8oC1WVfoiS2Xzl1SsmNWO7nkZBVYqjoQ5TOd63UuT0gZld6TGA7NO lK67oDVb2T+/wvz6OxGRbM4prPufFv7vygyIyCxi5okFfI42Kw9EsSQuzM6tO39NpWKk yGuA== X-Gm-Message-State: AC+VfDwPjkcBD4J8vvlP+nsqawjoGnrRc+k8V/EarPeNHhl/VTev51ig ATrhlxBOFJ6tMGVToDgoVMViOQ== X-Google-Smtp-Source: ACHHUZ4UH3+nQ7w0dxAK1qHTv+AY0CqemgAzfxycKSq/ENc3IsLO/TPxD8RwA0uyPe86zzm/LsZEXQ== X-Received: by 2002:a17:902:ea0a:b0:1b0:66b6:6ae5 with SMTP id s10-20020a170902ea0a00b001b066b66ae5mr4752327plg.61.1685979617657; Mon, 05 Jun 2023 08:40:17 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:17 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Guo Ren Subject: [PATCH -next v21 07/27] riscv: Introduce Vector enable/disable helpers Date: Mon, 5 Jun 2023 11:07:04 +0000 Message-Id: <20230605110724.21391-8-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu These are small and likely to be frequently called so implement as inline routines (vs. function call). Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/vector.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index bdbb05b70151..51bb37232943 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -11,12 +11,23 @@ #ifdef CONFIG_RISCV_ISA_V #include +#include static __always_inline bool has_vector(void) { return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); } +static __always_inline void riscv_v_enable(void) +{ + csr_set(CSR_SSTATUS, SR_VS); +} + +static __always_inline void riscv_v_disable(void) +{ + csr_clear(CSR_SSTATUS, SR_VS); +} + #else /* ! CONFIG_RISCV_ISA_V */ static __always_inline bool has_vector(void) { return false; } From patchwork Mon Jun 5 11:07:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D682EC7EE24 for ; Mon, 5 Jun 2023 15:41:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234979AbjFEPk6 (ORCPT ); Mon, 5 Jun 2023 11:40:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234911AbjFEPkg (ORCPT ); Mon, 5 Jun 2023 11:40:36 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9307A10B for ; Mon, 5 Jun 2023 08:40:29 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1b02d0942caso22484105ad.1 for ; Mon, 05 Jun 2023 08:40:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979629; x=1688571629; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=ShTLilbxMyWLUQGoTSAD12rpTJu8sGTqDWBHoo4WTRA=; b=RqN9ZmR50wIWqZyNAaUyXSKQkkoOCrNgGrYpV8HX55CJ2hj0Zgi9KgPtiP3uaGquro cabixdl5dULRIQwjV+wsruAnV7wvAec4Tyhp3uArmZxCn9oAS+49B89FTOFoY6HX6va/ a66Xobd4wMb69AqfGVSXC+R6ZpKrdMSnPiI0jXO6dCG7J39Q+dMP9crOxImwT690ZD4x 0ADYj2ltn4F3e6YfEYUUFC5y8z+/0t1B3cMMsF6I0ylwf0fkJoxC2LfGvDP4mV3GXpMJ m3PTnh6o9cpNoVjp0cDVwLe9l7iWdmx8en09CB/XItjUj0IqiuGUpff6nRuoJ2HCJ/Q5 GBHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979629; x=1688571629; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ShTLilbxMyWLUQGoTSAD12rpTJu8sGTqDWBHoo4WTRA=; b=NVuyGzgxrIlouaCv+iisZB2RY5v/NRVC2ycXMgTz43aPxUcMbouvujZ1PO9I+k+FG3 iiuUdACPN3p8frLvZCNovaz8mVi0HB/pdwSykQUm0QogrIvWKuZ1nnWXmJFvwRSpyz84 Dv2C+cgl4oR4DsUDof0O8hkxL8EacY2m1yINZbUovS7a4ySiXHSjLf3OIPLZHxElLpZF MsMxA8h4eb+e/C5o3ZZmI2FhbvlMq7NffAeR4TopZrn2LnVag5imwXonXqM6i8W0gbPh dKx7cLDSOYYR16Xlpa57KLhJerxR3hmjAf6z9iXhuCEVlM+2H6rYlVWVajG/pjZGRORX uhXA== X-Gm-Message-State: AC+VfDyXIzxiuxI/KN7qyXDNxxkwLY6KX/olzcFDIpd8yLs4CuYrnMr5 Kwyr1w10v+xhP0SSk600PT/A2A== X-Google-Smtp-Source: ACHHUZ5oy2CNE0jOxLsgkHbef63bspI+MqBmAWzHXrdzwFPqmy8wWcGTWTYvgZCNw/CRReweWkmBwA== X-Received: by 2002:a17:902:6b43:b0:1b2:2c0c:d3fa with SMTP id g3-20020a1709026b4300b001b22c0cd3famr157669plt.9.1685979629024; Mon, 05 Jun 2023 08:40:29 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:28 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Guo Ren , Conor Dooley , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Alexandre Ghiti , Li Zhengyu , Sia Jee Heng , Masahiro Yamada , Jisheng Zhang , Anup Patel , Xianting Tian , Andrew Jones , Atish Patra , Ley Foon Tan , Evan Green , Sunil V L Subject: [PATCH -next v21 08/27] riscv: Introduce riscv_v_vsize to record size of Vector context Date: Mon, 5 Jun 2023 11:07:05 +0000 Message-Id: <20230605110724.21391-9-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch is used to detect the size of CPU vector registers and use riscv_v_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in a SMP system. If a core detects VLENB that is different from the boot core, then it warns and turns off V support for user space. Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Palmer Dabbelt --- Changelog V19: - Fix grammar in WARN() (Conor) Changelog V18: - Detect inconsistent VLEN setup on an SMP system (Heiko). --- arch/riscv/include/asm/vector.h | 8 ++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ arch/riscv/kernel/smpboot.c | 7 +++++++ arch/riscv/kernel/vector.c | 36 +++++++++++++++++++++++++++++++++ 5 files changed, 54 insertions(+) create mode 100644 arch/riscv/kernel/vector.c diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 51bb37232943..df3b5caecc87 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -7,12 +7,16 @@ #define __ASM_RISCV_VECTOR_H #include +#include #ifdef CONFIG_RISCV_ISA_V #include #include +extern unsigned long riscv_v_vsize; +int riscv_v_setup_vsize(void); + static __always_inline bool has_vector(void) { return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); @@ -30,7 +34,11 @@ static __always_inline void riscv_v_disable(void) #else /* ! CONFIG_RISCV_ISA_V */ +struct pt_regs; + +static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } static __always_inline bool has_vector(void) { return false; } +#define riscv_v_vsize (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fbdccc21418a..c51f34c2756a 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o +obj-$(CONFIG_RISCV_ISA_V) += vector.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7aaf92fff64e..28032b083463 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -18,6 +18,7 @@ #include #include #include +#include #define NUM_ALPHA_EXTS ('z' - 'a' + 1) @@ -269,6 +270,7 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 445a4efee267..66011bf2b36e 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -31,6 +31,8 @@ #include #include #include +#include +#include #include "head.h" @@ -169,6 +171,11 @@ asmlinkage __visible void smp_callin(void) set_cpu_online(curr_cpuid, 1); probe_vendor_features(curr_cpuid); + if (has_vector()) { + if (riscv_v_setup_vsize()) + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; + } + /* * Remote TLB flushes are ignored while the CPU is offline, so emit * a local TLB flush right now just in case. diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c new file mode 100644 index 000000000000..120f1ce9abf9 --- /dev/null +++ b/arch/riscv/kernel/vector.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 SiFive + * Author: Andy Chiu + */ +#include + +#include +#include +#include +#include + +unsigned long riscv_v_vsize __read_mostly; +EXPORT_SYMBOL_GPL(riscv_v_vsize); + +int riscv_v_setup_vsize(void) +{ + unsigned long this_vsize; + + /* There are 32 vector registers with vlenb length. */ + riscv_v_enable(); + this_vsize = csr_read(CSR_VLENB) * 32; + riscv_v_disable(); + + if (!riscv_v_vsize) { + riscv_v_vsize = this_vsize; + return 0; + } + + if (riscv_v_vsize != this_vsize) { + WARN(1, "RISCV_ISA_V only supports one vlenb on SMP systems"); + return -EOPNOTSUPP; + } + + return 0; +} From patchwork Mon Jun 5 11:07:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A998C7EE24 for ; Mon, 5 Jun 2023 15:41:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232648AbjFEPl0 (ORCPT ); Mon, 5 Jun 2023 11:41:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234949AbjFEPkw (ORCPT ); Mon, 5 Jun 2023 11:40:52 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20964E41 for ; Mon, 5 Jun 2023 08:40:35 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-652d76be8c2so4082857b3a.3 for ; Mon, 05 Jun 2023 08:40:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979634; x=1688571634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kxEVtyq7dBTCubXHey7aFJ4tCQ5HL12TEktIsofBNGs=; b=OnNdGih9m3hBHVhxOHKWKviIPC+AaDLw5GVm27/gmkj9Y0/qKXdq6CRuV9p3Pu/3o3 n9TX2BWl8aibwUiW37/2wkSZAQ5nF8+is7qEQaKbzwu7sPGHx1odC+aw+5GaQ3wm+k0Y 8d3bzL6jn4MIivP96cHs8iuQdDRwe6AmzaIsMKy/MP9Bkkp65hreXLFYJULjSdVw+det 1EmbwbuzwInYLhcg+OQ8MgNkisAUbynPQKKdXbU7fzjaYElwhTaL7f2PAv0cDwwca0tu AlQC6elTLyTIZ+siocH8NkgOcjFenjrQin0gJB2chTG2ea5TfMEUY9wT5MPwtvuVVRGo GePQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979634; x=1688571634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kxEVtyq7dBTCubXHey7aFJ4tCQ5HL12TEktIsofBNGs=; b=S5wzRUrofzTo96tWXwxD5H6P9NXPido0JesFPIxIhVrHcGbYsMwUNYEyAEpOm7fx5+ n5Gvm/Sncpbe+6kkucXBSgRm23WnCugmLqRhTf1xnAFfdSCdrRNhUtyche/RC0lw04Sj zCLT9lMq52yFunNDM5Lm6OIfBOEJN3XSfCJMCFzns4yEX+IoyvQXsqy/qk/GiePNU2TR Q518absoOSHK1ago3dYqCWh45pd1rLjUVRj3okEHHuUf7DuQ8mH8AG6tTLq0rjrW5ZQ5 cSq8VNmZWTy1/IW0TNcKwFkc3tLZwYKtu32BzCbu+mcC7vy/BLBIpe2qQYGFZqkkros6 0Z7A== X-Gm-Message-State: AC+VfDx5+HEL2Sws4J5QK63Lb8RKIddRZY+cNxJnWff+GLUt8SCX1YqH 2EzZ3JGys8rJUylAINQW6aL2Ww== X-Google-Smtp-Source: ACHHUZ5pbxo0J0M4WCbe+KgkW+U+WnvH2OLqhT3drAD+z8zebaA48LRKA3rPjaI5NORSH9rGNHZyLw== X-Received: by 2002:a17:903:1109:b0:1a3:cd4c:8d08 with SMTP id n9-20020a170903110900b001a3cd4c8d08mr11051551plh.38.1685979634596; Mon, 05 Jun 2023 08:40:34 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:34 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Guo Ren , Conor Dooley Subject: [PATCH -next v21 09/27] riscv: Introduce struct/helpers to save/restore per-task Vector state Date: Mon, 5 Jun 2023 11:07:06 +0000 Message-Id: <20230605110724.21391-10-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu Add vector state context struct to be added later in thread_struct. And prepare low-level helper functions to save/restore vector contexts. This include Vector Regfile and CSRs holding dynamic configuration state (vstart, vl, vtype, vcsr). The Vec Register width could be implementation defined, but same for all processes, so that is saved separately. This is not yet wired into final thread_struct - will be done when __switch_to actually starts doing this in later patches. Given the variable (and potentially large) size of regfile, they are saved in dynamically allocated memory, pointed to by datap pointer in __riscv_v_ext_state. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta Signed-off-by: Andy Chiu Acked-by: Conor Dooley Reviewed-by: Guo Ren Reviewed-by: Björn Töpel Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/vector.h | 95 ++++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/ptrace.h | 17 +++++ 2 files changed, 112 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index df3b5caecc87..3c29f4eb552a 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -11,8 +11,10 @@ #ifdef CONFIG_RISCV_ISA_V +#include #include #include +#include extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); @@ -22,6 +24,26 @@ static __always_inline bool has_vector(void) return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); } +static inline void __riscv_v_vstate_clean(struct pt_regs *regs) +{ + regs->status = (regs->status & ~SR_VS) | SR_VS_CLEAN; +} + +static inline void riscv_v_vstate_off(struct pt_regs *regs) +{ + regs->status = (regs->status & ~SR_VS) | SR_VS_OFF; +} + +static inline void riscv_v_vstate_on(struct pt_regs *regs) +{ + regs->status = (regs->status & ~SR_VS) | SR_VS_INITIAL; +} + +static inline bool riscv_v_vstate_query(struct pt_regs *regs) +{ + return (regs->status & SR_VS) != 0; +} + static __always_inline void riscv_v_enable(void) { csr_set(CSR_SSTATUS, SR_VS); @@ -32,13 +54,86 @@ static __always_inline void riscv_v_disable(void) csr_clear(CSR_SSTATUS, SR_VS); } +static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *dest) +{ + asm volatile ( + "csrr %0, " __stringify(CSR_VSTART) "\n\t" + "csrr %1, " __stringify(CSR_VTYPE) "\n\t" + "csrr %2, " __stringify(CSR_VL) "\n\t" + "csrr %3, " __stringify(CSR_VCSR) "\n\t" + : "=r" (dest->vstart), "=r" (dest->vtype), "=r" (dest->vl), + "=r" (dest->vcsr) : :); +} + +static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src) +{ + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvl x0, %2, %1\n\t" + ".option pop\n\t" + "csrw " __stringify(CSR_VSTART) ", %0\n\t" + "csrw " __stringify(CSR_VCSR) ", %3\n\t" + : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl), + "r" (src->vcsr) :); +} + +static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, + void *datap) +{ + unsigned long vl; + + riscv_v_enable(); + __vstate_csr_save(save_to); + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vse8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vse8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=&r" (vl) : "r" (datap) : "memory"); + riscv_v_disable(); +} + +static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_from, + void *datap) +{ + unsigned long vl; + + riscv_v_enable(); + asm volatile ( + ".option push\n\t" + ".option arch, +v\n\t" + "vsetvli %0, x0, e8, m8, ta, ma\n\t" + "vle8.v v0, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v8, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v16, (%1)\n\t" + "add %1, %1, %0\n\t" + "vle8.v v24, (%1)\n\t" + ".option pop\n\t" + : "=&r" (vl) : "r" (datap) : "memory"); + __vstate_csr_restore(restore_from); + riscv_v_disable(); +} + #else /* ! CONFIG_RISCV_ISA_V */ struct pt_regs; static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } static __always_inline bool has_vector(void) { return false; } +static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } #define riscv_v_vsize (0) +#define riscv_v_vstate_off(regs) do {} while (0) +#define riscv_v_vstate_on(regs) do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 882547f6bd5c..586786d023c4 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -77,6 +77,23 @@ union __riscv_fp_state { struct __riscv_q_ext_state q; }; +struct __riscv_v_ext_state { + unsigned long vstart; + unsigned long vl; + unsigned long vtype; + unsigned long vcsr; + void *datap; + /* + * In signal handler, datap will be set a correct user stack offset + * and vector registers will be copied to the address of datap + * pointer. + * + * In ptrace syscall, datap will be set to zero and the vector + * registers will be copied to the address right after this + * structure. + */ +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ From patchwork Mon Jun 5 11:07:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B36ACC7EE23 for ; Mon, 5 Jun 2023 15:41:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234911AbjFEPlx (ORCPT ); Mon, 5 Jun 2023 11:41:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233728AbjFEPli (ORCPT ); Mon, 5 Jun 2023 11:41:38 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E907510FF for ; Mon, 5 Jun 2023 08:41:08 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1b0236ee816so35857045ad.1 for ; Mon, 05 Jun 2023 08:41:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979643; x=1688571643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H5ABTghwvTI+9r/qQCKwtiC6pFEmv/0ohdPEWRF58vQ=; b=LJTknzgh62SsCBHuGzktWmw6QJJSAbz3CWS0rkA7cAh1fMdPCXUD1298oD0xdojFmR fPCeO0fbj1uMVI7dOWcbQODQme6Lf/niY+qlbN4SrPriQ9CybIhRcOKLjjQgmMDDrBrE kejG0Xyl4InXJVJmxqBOjmzTNok/PHiPj5mFOnVPa9X1b9j8xNpCpJckYcuwELnGniHW zjuAB9FCb+/gXXuhDkOCQbWEdMlBCJ+Zy1CUDu/EDJYeZOp+2qrIHudfrXT1dWwT0i4Y tYO1MSdrC+hetQVXkTzdowgAs6oFq2mxvr9LbkRFCAgPb8gtqfv9A1q47pk81vcCuAtH OFmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979643; x=1688571643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H5ABTghwvTI+9r/qQCKwtiC6pFEmv/0ohdPEWRF58vQ=; b=kONWXxuVBeZL9Jrbc5EJ0yAcCUpOC5LRx7aGz3dcjFHSdnnvK5PTLBYh73cay/2Hpu UPvrXP3hWBtU4wYeDfZQiaDzorYBA0Rx+8dX6PqKfnVNYS+pPRF86N5xohUki6nrkhzl CrBMayzhurvkq8lRlVFVQ+DeCky3F34/gf9AsUP0on5iiW7XOX5pF0YziYd15LeabjI8 apIE4QXC+Y/0tqVei8emm7qkdSt3hm9OWLh6BskgYXaRW+1sil1PkDFRM9KJvwFz8h32 /WsNfx4ODQDex8HElfjiJ09CMvvrq56oTIfBA6+JQRaa4baS2XC+FRfib6VaomHzzOEX aFDA== X-Gm-Message-State: AC+VfDzlE8ogO7J0ED9C3yT/YokFBDeejTpmVbx+hSMv3PxE/G19OR0T LozuAgCFAV3lE/O4gRTWvLUmtA== X-Google-Smtp-Source: ACHHUZ7uA9bDyWuvzGvUPYr/uB402G/5hp1cVeED86CmlSqKsIuxEz5sfvvR1j388KxSjkBEpf0SuQ== X-Received: by 2002:a17:902:ec90:b0:1b1:94a8:ab2d with SMTP id x16-20020a170902ec9000b001b194a8ab2dmr9133436plg.29.1685979643627; Mon, 05 Jun 2023 08:40:43 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:43 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Nick Knight , Vincent Chen , Ruinland Tsai , Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Guo Ren , Kefeng Wang , Sunil V L , Conor Dooley , Jisheng Zhang , Peter Zijlstra Subject: [PATCH -next v21 10/27] riscv: Add task switch support for vector Date: Mon, 5 Jun 2023 11:07:07 +0000 Message-Id: <20230605110724.21391-11-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch adds task switch support for vector. It also supports all lengths of vlen. Suggested-by: Andrew Waterman Co-developed-by: Nick Knight Signed-off-by: Nick Knight Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Ruinland Tsai Signed-off-by: Ruinland Tsai Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Björn Töpel Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- Changelog v21: - move riscv_v_vstate_off(childregs); to a proper place. --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/switch_to.h | 3 +++ arch/riscv/include/asm/thread_info.h | 3 +++ arch/riscv/include/asm/vector.h | 38 ++++++++++++++++++++++++++++ arch/riscv/kernel/process.c | 19 ++++++++++++++ 5 files changed, 64 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..f0ddf691ac5e 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -39,6 +39,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + struct __riscv_v_ext_state vstate; }; /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 4b96b13dee27..a727be723c56 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -78,6 +79,8 @@ do { \ struct task_struct *__next = (next); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ + if (has_vector()) \ + __switch_to_vector(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index e0d202134b44..97e6f65ec176 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -81,6 +81,9 @@ struct thread_info { .preempt_count = INIT_PREEMPT_COUNT, \ } +void arch_release_task_struct(struct task_struct *tsk); +int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); + #endif /* !__ASSEMBLY__ */ /* diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 3c29f4eb552a..ce6a75e9cf62 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -12,6 +12,9 @@ #ifdef CONFIG_RISCV_ISA_V #include +#include +#include +#include #include #include #include @@ -124,6 +127,38 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_disable(); } +static inline void riscv_v_vstate_save(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) == SR_VS_DIRTY) { + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + + __riscv_v_vstate_save(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } +} + +static inline void riscv_v_vstate_restore(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) != SR_VS_OFF) { + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + + __riscv_v_vstate_restore(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } +} + +static inline void __switch_to_vector(struct task_struct *prev, + struct task_struct *next) +{ + struct pt_regs *regs; + + regs = task_pt_regs(prev); + riscv_v_vstate_save(prev, regs); + riscv_v_vstate_restore(next, task_pt_regs(next)); +} + #else /* ! CONFIG_RISCV_ISA_V */ struct pt_regs; @@ -132,6 +167,9 @@ static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } static __always_inline bool has_vector(void) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } #define riscv_v_vsize (0) +#define riscv_v_vstate_save(task, regs) do {} while (0) +#define riscv_v_vstate_restore(task, regs) do {} while (0) +#define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e2a060066730..78eb5ac45888 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -24,6 +24,7 @@ #include #include #include +#include register unsigned long gp_in_global __asm__("gp"); @@ -146,12 +147,28 @@ void flush_thread(void) fstate_off(current, task_pt_regs(current)); memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); #endif +#ifdef CONFIG_RISCV_ISA_V + /* Reset vector state */ + riscv_v_vstate_off(task_pt_regs(current)); + kfree(current->thread.vstate.datap); + memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); +#endif +} + +void arch_release_task_struct(struct task_struct *tsk) +{ + /* Free the vector context of datap. */ + if (has_vector()) + kfree(tsk->thread.vstate.datap); } int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { fstate_save(src, task_pt_regs(src)); *dst = *src; + /* clear entire V context, including datap for a new task */ + memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); + return 0; } @@ -176,6 +193,8 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) p->thread.s[1] = (unsigned long)args->fn_arg; } else { *childregs = *(current_pt_regs()); + /* Turn off status.VS */ + riscv_v_vstate_off(childregs); if (usp) /* User fork */ childregs->sp = usp; if (clone_flags & CLONE_SETTLS) From patchwork Mon Jun 5 11:07:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CC3BC7EE24 for ; Mon, 5 Jun 2023 15:42:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234953AbjFEPmB (ORCPT ); Mon, 5 Jun 2023 11:42:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234771AbjFEPlp (ORCPT ); Mon, 5 Jun 2023 11:41:45 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D31C111A for ; Mon, 5 Jun 2023 08:41:16 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-64d57cd373fso4321491b3a.1 for ; Mon, 05 Jun 2023 08:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979652; x=1688571652; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=gf/IwQV6P+rJliEO2LEjL1VDxZs9ZYpyuR4dzzlhnB4=; b=i54Ga+xdWMZJM14MH6Gd0Si8XH0cP2Jc+xIuUsxO4dmMpmB+bnQ3Mra/m9U9hfv5WK l/lLy5HzgCw7axFjcLI9dZvDf+T11oLaczjahy7VAUTcjSdqVrPyCJOrholZuu3r03zc zVPXrfwqT4IfbiztXWTmc7elLU/hnL6dFMO+xWYNyexkVxnHgN9QpZif3H/qH0ot4aoJ LjYF4sepTd7XsiNQ2evyAq+uG1YVdOY/MSnvyBxwURbS5Yxpi1uTPCeNr5R0IyMD1ZFZ 0f6+RQl+QofkDWifDW6W/KEWSeOqvmkPnGiewZ4iNbBOm3zix9KVFgfRAaTjw0TLHQ6m p4cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979652; x=1688571652; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=gf/IwQV6P+rJliEO2LEjL1VDxZs9ZYpyuR4dzzlhnB4=; b=axVSGlU2R+GWTKgm8xih8IQx79iqRiF+tG2lK2OCYOVttkxOwDrqkBFn4uf5u1Stjw ZRPItQ9lmM5shRUABc10BXupL6c2szy/+WHz0Z/UG87mVqDrmMJWB/YtXjE/roQUIeXQ P/+znJSapovXTBYRzL/Yj9dGsVblgxQIaNOd5ORlibi91BWzt1l2jIfient4u7/YnsIp g4FiLGUMw8nyCW9DtR4VtS/h0vkfwznkM++zZH+z3thkoh61J5jH+Y7ZTgB8JCAhe62C E67S57IbSdUrNtOcrYOvOuA5481/6fiG65h5Sqdtfd96f26KCoI/P4gAxK+xnkrhWh3z JW7A== X-Gm-Message-State: AC+VfDwiah7yRSDPCJ/0yK3wALyXtJHynU/jga2ka28/S3/Kq3o+sTii 1ebkzVQZSi7ZAUEGcjmw/ex27w== X-Google-Smtp-Source: ACHHUZ7r0oPs6EQXXzKZXuaUKlCPs/4xk82Y5oTkRXi/eyrOAJwet+3eb03JQP6d5qoYQEfLFSR0rA== X-Received: by 2002:a17:902:d50c:b0:1b0:10a1:3da9 with SMTP id b12-20020a170902d50c00b001b010a13da9mr8821833plg.32.1685979652597; Mon, 05 Jun 2023 08:40:52 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:51 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , Conor Dooley , Lad Prabhakar , Jisheng Zhang , Liao Chang , Vincent Chen , Guo Ren , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Xianting Tian , Mattias Nissler Subject: [PATCH -next v21 11/27] riscv: Allocate user's vector context in the first-use trap Date: Mon, 5 Jun 2023 11:07:08 +0000 Message-Id: <20230605110724.21391-12-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Vector unit is disabled by default for all user processes. Thus, a process will take a trap (illegal instruction) into kernel at the first time when it uses Vector. Only after then, the kernel allocates V context and starts take care of the context for that user process. Suggested-by: Richard Henderson Link: https://lore.kernel.org/r/3923eeee-e4dc-0911-40bf-84c34aee962d@linaro.org Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- Changelog v21: - Remove has_vector() and use ELF_HWCAP instead. The V bit in the hwcap, if preesents, implies has_vector() returning true. So we can drop has_vector() test here safely, because we also don't handle !V but has_vector() cases. - Change SIGKILL to SIGBUS when allocation of V-context fails. (Darius) Changelog v20: - move has_vector() into vector.c for better code readibility - check elf_hwcap in the first-use trap because it might get turned off if cores have different VLENs. Changelog v18: - Add blank lines (Heiko) - Return immediately in insn_is_vector() if an insn matches (Heiko) --- arch/riscv/include/asm/insn.h | 29 ++++++++++ arch/riscv/include/asm/vector.h | 2 + arch/riscv/kernel/traps.c | 26 ++++++++- arch/riscv/kernel/vector.c | 95 +++++++++++++++++++++++++++++++++ 4 files changed, 150 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index 8d5c84f2d5ef..4e1505cef8aa 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -137,6 +137,26 @@ #define RVG_OPCODE_JALR 0x67 #define RVG_OPCODE_JAL 0x6f #define RVG_OPCODE_SYSTEM 0x73 +#define RVG_SYSTEM_CSR_OFF 20 +#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0) + +/* parts of opcode for RVF, RVD and RVQ */ +#define RVFDQ_FL_FS_WIDTH_OFF 12 +#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0) +#define RVFDQ_FL_FS_WIDTH_W 2 +#define RVFDQ_FL_FS_WIDTH_D 3 +#define RVFDQ_LS_FS_WIDTH_Q 4 +#define RVFDQ_OPCODE_FL 0x07 +#define RVFDQ_OPCODE_FS 0x27 + +/* parts of opcode for RVV */ +#define RVV_OPCODE_VECTOR 0x57 +#define RVV_VL_VS_WIDTH_8 0 +#define RVV_VL_VS_WIDTH_16 5 +#define RVV_VL_VS_WIDTH_32 6 +#define RVV_VL_VS_WIDTH_64 7 +#define RVV_OPCODE_VL RVFDQ_OPCODE_FL +#define RVV_OPCODE_VS RVFDQ_OPCODE_FS /* parts of opcode for RVC*/ #define RVC_OPCODE_C0 0x0 @@ -304,6 +324,15 @@ static __always_inline bool riscv_insn_is_branch(u32 code) (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \ (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) +#define RVG_EXTRACT_SYSTEM_CSR(x) \ + ({typeof(x) x_ = (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); }) + +#define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \ + ({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \ + RVFDQ_FL_FS_WIDTH_MASK); }) + +#define RVV_EXRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x) + /* * Get the immediate from a J-type instruction. * diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index ce6a75e9cf62..8e56da67b5cf 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -21,6 +21,7 @@ extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); +bool riscv_v_first_use_handler(struct pt_regs *regs); static __always_inline bool has_vector(void) { @@ -165,6 +166,7 @@ struct pt_regs; static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } static __always_inline bool has_vector(void) { return false; } +static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } #define riscv_v_vsize (0) #define riscv_v_vstate_save(task, regs) do {} while (0) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8c258b78c925..05ffdcd1424e 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -26,6 +26,7 @@ #include #include #include +#include int show_unhandled_signals = 1; @@ -145,8 +146,29 @@ DO_ERROR_INFO(do_trap_insn_misaligned, SIGBUS, BUS_ADRALN, "instruction address misaligned"); DO_ERROR_INFO(do_trap_insn_fault, SIGSEGV, SEGV_ACCERR, "instruction access fault"); -DO_ERROR_INFO(do_trap_insn_illegal, - SIGILL, ILL_ILLOPC, "illegal instruction"); + +asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *regs) +{ + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + + local_irq_enable(); + + if (!riscv_v_first_use_handler(regs)) + do_trap_error(regs, SIGILL, ILL_ILLOPC, regs->epc, + "Oops - illegal instruction"); + + irqentry_exit_to_user_mode(regs); + } else { + irqentry_state_t state = irqentry_nmi_enter(regs); + + do_trap_error(regs, SIGILL, ILL_ILLOPC, regs->epc, + "Oops - illegal instruction"); + + irqentry_nmi_exit(regs, state); + } +} + DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); #ifndef CONFIG_RISCV_M_MODE diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 120f1ce9abf9..9d81d1b2a7f3 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -4,10 +4,19 @@ * Author: Andy Chiu */ #include +#include +#include +#include +#include +#include +#include +#include +#include #include #include #include +#include #include unsigned long riscv_v_vsize __read_mostly; @@ -34,3 +43,89 @@ int riscv_v_setup_vsize(void) return 0; } + +static bool insn_is_vector(u32 insn_buf) +{ + u32 opcode = insn_buf & __INSN_OPCODE_MASK; + u32 width, csr; + + /* + * All V-related instructions, including CSR operations are 4-Byte. So, + * do not handle if the instruction length is not 4-Byte. + */ + if (unlikely(GET_INSN_LENGTH(insn_buf) != 4)) + return false; + + switch (opcode) { + case RVV_OPCODE_VECTOR: + return true; + case RVV_OPCODE_VL: + case RVV_OPCODE_VS: + width = RVV_EXRACT_VL_VS_WIDTH(insn_buf); + if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 || + width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64) + return true; + + break; + case RVG_OPCODE_SYSTEM: + csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf); + if ((csr >= CSR_VSTART && csr <= CSR_VCSR) || + (csr >= CSR_VL && csr <= CSR_VLENB)) + return true; + } + + return false; +} + +static int riscv_v_thread_zalloc(void) +{ + void *datap; + + datap = kzalloc(riscv_v_vsize, GFP_KERNEL); + if (!datap) + return -ENOMEM; + + current->thread.vstate.datap = datap; + memset(¤t->thread.vstate, 0, offsetof(struct __riscv_v_ext_state, + datap)); + return 0; +} + +bool riscv_v_first_use_handler(struct pt_regs *regs) +{ + u32 __user *epc = (u32 __user *)regs->epc; + u32 insn = (u32)regs->badaddr; + + /* Do not handle if V is not supported, or disabled */ + if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V)) + return false; + + /* If V has been enabled then it is not the first-use trap */ + if (riscv_v_vstate_query(regs)) + return false; + + /* Get the instruction */ + if (!insn) { + if (__get_user(insn, epc)) + return false; + } + + /* Filter out non-V instructions */ + if (!insn_is_vector(insn)) + return false; + + /* Sanity check. datap should be null by the time of the first-use trap */ + WARN_ON(current->thread.vstate.datap); + + /* + * Now we sure that this is a V instruction. And it executes in the + * context where VS has been off. So, try to allocate the user's V + * context and resume execution. + */ + if (riscv_v_thread_zalloc()) { + force_sig(SIGBUS); + return true; + } + riscv_v_vstate_on(regs); + return true; +} From patchwork Mon Jun 5 11:07:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F424C7EE2C for ; Mon, 5 Jun 2023 15:42:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234997AbjFEPmE (ORCPT ); Mon, 5 Jun 2023 11:42:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234959AbjFEPls (ORCPT ); Mon, 5 Jun 2023 11:41:48 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33E62131 for ; Mon, 5 Jun 2023 08:41:22 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-53fe2275249so2512167a12.2 for ; Mon, 05 Jun 2023 08:41:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979659; x=1688571659; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=TK601nUo3JGOQ5o2y+/f0WKC5t8HaAAxa1cHt24xSbI=; b=R5BxkKCWIghCYwLXPtnwRI07Z3hc7iGIi/1HXhM2k8fOuhBhB8tEbXKkK9gHOj/VAN 0czr+1rxNjN+afGR1VUqprS8iWfgvLm5G0kf1Vnvyk52sbTkiiYWMinvnQidwTydJKsY gZkLFC7TmOwzpMurHMAZeyCNGaNERqoyr8aROMHd6eJqlT0zZoCabwGHcXdm7ATwgeRl vr02oRmwAnthb/7iVofuUxzVf/5sFsulL+Mnh2tlJhSsMHjgUzatwaoDF+iYDFGK18+l Tr9aclC+uDh9J7RB0VKwhu1C5w1j8d0bSm0/GUz6BmWKT+4iqRkgTSDsuqXdcfjMPJEg rotA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979659; x=1688571659; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=TK601nUo3JGOQ5o2y+/f0WKC5t8HaAAxa1cHt24xSbI=; b=HocKBd/bwe46Wf4pyF/YL3hregDYZuFyJ8i8uRew8TSzn/xdky+Gm0WVM6+iHIkYDc sUXNBzcP+ZlgBKSmeNCWC+Dcs1qsRWt/UwfvX0+xmjr/X9KlbijQ/WS4h6M5mi9t4vgf 3LEmnB1I7CcRWj+dnn2i4GoveRklOBvdzx/ZRj0z8r/Op+7QdkCO/jy2fUkqZbWb5Kdl Z1Nmm+DOAn/erWHTHJCw3luROGKC95Blv4wHRMMP0tEGEMaz+/U7IwGEQd5l8tPDxRIO WpfLKvrBCwuFhmxqIyGpdGRHwQPc22fvqmVP1zvcYjzoi54tLicX612HVEGZfuYLWSQU jAUw== X-Gm-Message-State: AC+VfDzVGX/W36ULBmsELNOG1+tad0eSyINJL0yWdI/qod/aOB4LvFp2 qtOH01hiSeu1paf3ZAyhCQWNpg== X-Google-Smtp-Source: ACHHUZ7hfG1thEtCG4vbbjy6UDKU1EfM3Ezzqk9rQTWatF9ikbEydRLDwivfsoWuJM2PMIaiFjRg8Q== X-Received: by 2002:a17:902:6a88:b0:1b0:113e:1047 with SMTP id n8-20020a1709026a8800b001b0113e1047mr2933210plk.62.1685979658667; Mon, 05 Jun 2023 08:40:58 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:40:58 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Oleg Nesterov , Eric Biederman , Kees Cook , Heiko Stuebner , Conor Dooley , "Christian Brauner (Microsoft)" , Mark Brown , Rolf Eike Beer , Janosch Frank , Qing Zhang Subject: [PATCH -next v21 12/27] riscv: Add ptrace vector support Date: Mon, 5 Jun 2023 11:07:09 +0000 Message-Id: <20230605110724.21391-13-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch adds ptrace support for riscv vector. The vector registers will be saved in datap pointer of __riscv_v_ext_state. This pointer will be set right after the __riscv_v_ext_state data structure then it will be put in ubuf for ptrace system call to get or set. It will check if the datap got from ubuf is set to the correct address or not when the ptrace system call is trying to set the vector registers. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Palmer Dabbelt --- Changelog V18: - Use sizeof(vstate->datap) instead of sizeof(void*) (Eike) --- arch/riscv/include/uapi/asm/ptrace.h | 7 +++ arch/riscv/kernel/ptrace.c | 70 ++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 78 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 586786d023c4..e8d127ec5cf7 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -94,6 +94,13 @@ struct __riscv_v_ext_state { */ }; +/* + * According to spec: The number of bits in a single vector register, + * VLEN >= ELEN, which must be a power of 2, and must be no greater than + * 2^16 = 65536bits = 8192bytes + */ +#define RISCV_MAX_VLENB (8192) + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 23c48b14a0e7..1d572cf3140f 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -7,6 +7,7 @@ * Copied from arch/tile/kernel/ptrace.c */ +#include #include #include #include @@ -24,6 +25,9 @@ enum riscv_regset { #ifdef CONFIG_FPU REGSET_F, #endif +#ifdef CONFIG_RISCV_ISA_V + REGSET_V, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -80,6 +84,61 @@ static int riscv_fpr_set(struct task_struct *target, } #endif +#ifdef CONFIG_RISCV_ISA_V +static int riscv_vr_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct __riscv_v_ext_state *vstate = &target->thread.vstate; + + if (!riscv_v_vstate_query(task_pt_regs(target))) + return -EINVAL; + + /* + * Ensure the vector registers have been saved to the memory before + * copying them to membuf. + */ + if (target == current) + riscv_v_vstate_save(current, task_pt_regs(current)); + + /* Copy vector header from vstate. */ + membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state, datap)); + membuf_zero(&to, sizeof(vstate->datap)); + + /* Copy all the vector registers from vstate. */ + return membuf_write(&to, vstate->datap, riscv_v_vsize); +} + +static int riscv_vr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret, size; + struct __riscv_v_ext_state *vstate = &target->thread.vstate; + + if (!riscv_v_vstate_query(task_pt_regs(target))) + return -EINVAL; + + /* Copy rest of the vstate except datap */ + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0, + offsetof(struct __riscv_v_ext_state, datap)); + if (unlikely(ret)) + return ret; + + /* Skip copy datap. */ + size = sizeof(vstate->datap); + count -= size; + ubuf += size; + + /* Copy all the vector registers. */ + pos = 0; + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap, + 0, riscv_v_vsize); + return ret; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -99,6 +158,17 @@ static const struct user_regset riscv_user_regset[] = { .set = riscv_fpr_set, }, #endif +#ifdef CONFIG_RISCV_ISA_V + [REGSET_V] = { + .core_note_type = NT_RISCV_VECTOR, + .align = 16, + .n = ((32 * RISCV_MAX_VLENB) + + sizeof(struct __riscv_v_ext_state)) / sizeof(__u32), + .size = sizeof(__u32), + .regset_get = riscv_vr_get, + .set = riscv_vr_set, + }, +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index ac3da855fb19..7d8d9ae36615 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -440,6 +440,7 @@ typedef struct elf64_shdr { #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */ #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ +#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */ From patchwork Mon Jun 5 11:07:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 988BEC7EE24 for ; Mon, 5 Jun 2023 15:42:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234999AbjFEPmG (ORCPT ); Mon, 5 Jun 2023 11:42:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231494AbjFEPlt (ORCPT ); Mon, 5 Jun 2023 11:41:49 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D32EE1B6 for ; Mon, 5 Jun 2023 08:41:23 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1b034ca1195so22472985ad.2 for ; Mon, 05 Jun 2023 08:41:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979663; x=1688571663; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=wN7ZHBcxzp7ZsRkqqH3xjhadPlnuKqjQR/mkhzwbhmg=; b=GJKOvUN4LO1OABHEIz+KLh16tGWqL0jZvco8d7SBse3jPaksrM0vTsIp1I1584Hsin WPcOTT6CYhA78qSu9it/RMJ5TyDp921fe+Pwf71WjFB2KX4ON3aFa6mud0MkbjEa3dve /YrUVhRILe4o82FsseKsCnT8dRQCqsGI9zWhoye4qQSkJtwT5mqKMiRQ5o8H4mqPrIZF 7m10AyO/Pz9Yr38DqFTM4C8AjMv0nyMQQ3HMe0psHbkv/9owtVRG23Sqlg2hfO9DuAXb L2vXhBiE02iZXjJbl8r5E2AwII1204o1BYoIh0axzwyKNPrPijgQ/mh5+pROId93BvFT yGSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979663; x=1688571663; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=wN7ZHBcxzp7ZsRkqqH3xjhadPlnuKqjQR/mkhzwbhmg=; b=HK+B5D3tC38ZHCg6viQt1oj8WnkTd5J29Pb/enssiLMAu0T+w9lIgi2ZG+UqfXLaEZ b3SnqZRqTyIBYBNFItxNRw8LJH1u7QOyfPGMBUbCMTYmNW06KoApCLFviOo6y3XrA1jX NpOCzQAcGUwk8M/c905i1H841DbDNTpuUT8VJuBH+suEeYdykMBGj02FGQBp8IXfv0md ho2D8IJhUUAZ6WpJvJFK7aIMnmIiUksQlmSoxuDatnPljdgAPQlNA/hOZ+rAHUZSOdad hctRoYLHsjVd41bOgOeDkKgzwvBG0Vb+noSS5awyV9Q3WoM88eJYJpPY5Bni0j8ONF3C VDyw== X-Gm-Message-State: AC+VfDyyq3Sclbe3tW75tdPzuQkDId40dSx5QV+fK1FTDv6DQoroemJM LdZR3Xcv9yuZjPuYX4fbrcBiKg== X-Google-Smtp-Source: ACHHUZ4u5Py1QSWjvfvmdacfiasEhMFCzFnQiePOem15ngafbyO0VGK06vhOFMvetnkEAH4kisK7sg== X-Received: by 2002:a17:902:e5c5:b0:1b0:75ef:ce3e with SMTP id u5-20020a170902e5c500b001b075efce3emr4177491plf.25.1685979663274; Mon, 05 Jun 2023 08:41:03 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:02 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Conor Dooley , Guo Ren , Mathis Salmen , Andrew Bresticker , Vincent Chen Subject: [PATCH -next v21 13/27] riscv: signal: check fp-reserved words unconditionally Date: Mon, 5 Jun 2023 11:07:10 +0000 Message-Id: <20230605110724.21391-14-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org In order to let kernel/user locate and identify an extension context on the existing sigframe, we are going to utilize reserved space of fp and encode the information there. And since the sigcontext has already preserved a space for fp context w or w/o CONFIG_FPU, we move those reserved words checking/setting routine back into generic code. This commit also undone an additional logical change carried by the refactor commit 007f5c3589578 ("Refactor FPU code in signal setup/return procedures"). Originally we did not restore fp context if restoring of gpr have failed. And it was fine on the other side. In such way the kernel could keep the regfiles intact, and potentially react at the failing point of restore. Signed-off-by: Andy Chiu Acked-by: Conor Dooley Acked-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/kernel/signal.c | 55 +++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 9aff9d720590..6b4a5c90bd87 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -40,26 +40,13 @@ static long restore_fp_state(struct pt_regs *regs, { long err; struct __riscv_d_ext_state __user *state = &sc_fpregs->d; - size_t i; err = __copy_from_user(¤t->thread.fstate, state, sizeof(*state)); if (unlikely(err)) return err; fstate_restore(current, regs); - - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) { - u32 value; - - err = __get_user(value, &sc_fpregs->q.reserved[i]); - if (unlikely(err)) - break; - if (value != 0) - return -EINVAL; - } - - return err; + return 0; } static long save_fp_state(struct pt_regs *regs, @@ -67,20 +54,9 @@ static long save_fp_state(struct pt_regs *regs, { long err; struct __riscv_d_ext_state __user *state = &sc_fpregs->d; - size_t i; fstate_save(current, regs); err = __copy_to_user(state, ¤t->thread.fstate, sizeof(*state)); - if (unlikely(err)) - return err; - - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) { - err = __put_user(0, &sc_fpregs->q.reserved[i]); - if (unlikely(err)) - break; - } - return err; } #else @@ -92,11 +68,30 @@ static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { long err; + size_t i; + /* sc_regs is structured the same as the start of pt_regs */ err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); + if (unlikely(err)) + return err; + /* Restore the floating-point state. */ - if (has_fpu()) - err |= restore_fp_state(regs, &sc->sc_fpregs); + if (has_fpu()) { + err = restore_fp_state(regs, &sc->sc_fpregs); + if (unlikely(err)) + return err; + } + + /* We support no other extension state at this time. */ + for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) { + u32 value; + + err = __get_user(value, &sc->sc_fpregs.q.reserved[i]); + if (unlikely(err)) + break; + if (value != 0) + return -EINVAL; + } return err; } @@ -147,11 +142,17 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, { struct sigcontext __user *sc = &frame->uc.uc_mcontext; long err; + size_t i; + /* sc_regs is structured the same as the start of pt_regs */ err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); /* Save the floating-point state. */ if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); + /* We support no other extension state at this time. */ + for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) + err |= __put_user(0, &sc->sc_fpregs.q.reserved[i]); + return err; } From patchwork Mon Jun 5 11:07:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F9B3C7EE24 for ; Mon, 5 Jun 2023 15:42:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231425AbjFEPmK (ORCPT ); Mon, 5 Jun 2023 11:42:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232049AbjFEPlx (ORCPT ); Mon, 5 Jun 2023 11:41:53 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D812118E for ; Mon, 5 Jun 2023 08:41:28 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-652a6cf1918so2138472b3a.1 for ; Mon, 05 Jun 2023 08:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979671; x=1688571671; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=MdADAAcqMqw/ern4VfZKqbSeESM813gLnUOdgVy5HP8=; b=TLX8OKQR0cWmGit2YFc+xFRNZHQrTcc72ikDSK6oQbaQZzEy/LWpolzn93ZblT2L4h becT8O71+7aKcMj/ew/Osgach0d7F2Bzd82XXeQF1Pc+72RKhsHc6LURNe0EexptyrMq hSTJ0bfjW3MPfDvpdRrGXn/5oUNwualKHlIlIoeJE6W4iBFRvK9Wd06GVCCm7dOC7QMM MrtWe7TT7Tj/LCwDOe3AphEke+2pXay7L4t7HcPoWYV9ZGSdB8h/pfdrozf4iHRlkLwE 6pigXLMZUTqWVcE07VpKe1T4my6gI4fGXha542K2FcJ7ArcHsEh83X5XoUDc7jyAhMGW 20Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979671; x=1688571671; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MdADAAcqMqw/ern4VfZKqbSeESM813gLnUOdgVy5HP8=; b=Mp+DxNP3OH1nmH4APBJuTxE6sRwR9rweTGe4fUJYJFxyUYXBinIh3NgFokoNOKEmsn oYgRa6SZHCuiaG8xXXe9peS2LV7XV1B7qAZikB2Xr5GWbHBcvEMlKMG/FrHR9Io7xHOC E3ra2sU3y8MenZIPv36KPCVQSzPooLZWKCLscepSYKv/z6+4U+aECMWDQVTfCsnJYe0p j25CCdwNxnJKk4/TRpUPbuvx7Hf68uH4oU1O3UQPgja08zYIZQoTF3IqizHPYkrKfhPY xKzYTT2omge/XZzuG1hi9TREiA/RqC2EZXoNnkDdcB8O2a5Ky25IzZ42bpE5kK44fGPE pIPw== X-Gm-Message-State: AC+VfDytUCCx2/pB/waT8rEDQPlMIy/W6oe2K/cZol9qOoAXpi1lY3eD XSiqSwmqwK760PofnuWqsz4Axg== X-Google-Smtp-Source: ACHHUZ6dyOwc4xL0P4QIob9vbSsbPZm1J9vWCofkWA7KybsErWYR+ftvUwCCNbJiKk/d9fPO4C0npw== X-Received: by 2002:a17:902:d2cf:b0:1b0:2cd0:af3b with SMTP id n15-20020a170902d2cf00b001b02cd0af3bmr4754136plc.6.1685979671221; Mon, 05 Jun 2023 08:41:11 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:10 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Conor Dooley , Alexandre Ghiti , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Rob Herring , Jisheng Zhang , Wenting Zhang , Guo Ren , Andrew Bresticker , Al Viro Subject: [PATCH -next v21 14/27] riscv: signal: Add sigcontext save/restore for vector Date: Mon, 5 Jun 2023 11:07:11 +0000 Message-Id: <20230605110724.21391-15-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch facilitates the existing fp-reserved words for placement of the first extension's context header on the user's sigframe. A context header consists of a distinct magic word and the size, including the header itself, of an extension on the stack. Then, the frame is followed by the context of that extension, and then a header + context body for another extension if exists. If there is no more extension to come, then the frame must be ended with a null context header. A special case is rv64gc, where the kernel support no extensions requiring to expose additional regfile to the user. In such case the kernel would place the null context header right after the first reserved word of __riscv_q_ext_state when saving sigframe. And the kernel would check if all reserved words are zeros when a signal handler returns. __riscv_q_ext_state---->| |<-__riscv_extra_ext_header ~ ~ .reserved[0]--->|0 |<- .reserved <-------|magic |<- .hdr | |size |_______ end of sc_fpregs | |ext-bdy| | ~ ~ +)size ------->|magic |<- another context header |size | |ext-bdy| ~ ~ |magic:0|<- null context header |size:0 | The vector registers will be saved in datap pointer. The datap pointer will be allocated dynamically when the task needs in kernel space. On the other hand, datap pointer on the sigframe will be set right after the __riscv_v_ext_state data structure. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Suggested-by: Vineet Gupta Suggested-by: Richard Henderson Co-developed-by: Andy Chiu Signed-off-by: Andy Chiu Acked-by: Conor Dooley Acked-by: Heiko Stuebner Tested-by: Heiko Stuebner --- Changelog V19: - Fix a conflict in signal.c due to commit 8d736482749f ("riscv: add icache flush for nommu sigreturn trampoline") --- arch/riscv/include/uapi/asm/ptrace.h | 15 ++ arch/riscv/include/uapi/asm/sigcontext.h | 16 ++- arch/riscv/kernel/setup.c | 3 + arch/riscv/kernel/signal.c | 174 +++++++++++++++++++++-- 4 files changed, 193 insertions(+), 15 deletions(-) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index e8d127ec5cf7..e17c550986a6 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -71,6 +71,21 @@ struct __riscv_q_ext_state { __u32 reserved[3]; }; +struct __riscv_ctx_hdr { + __u32 magic; + __u32 size; +}; + +struct __riscv_extra_ext_header { + __u32 __padding[129] __attribute__((aligned(16))); + /* + * Reserved for expansion of sigcontext structure. Currently zeroed + * upon signal, and must be zero upon sigreturn. + */ + __u32 reserved; + struct __riscv_ctx_hdr hdr; +}; + union __riscv_fp_state { struct __riscv_f_ext_state f; struct __riscv_d_ext_state d; diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h index 84f2dfcfdbce..8b8a8541673a 100644 --- a/arch/riscv/include/uapi/asm/sigcontext.h +++ b/arch/riscv/include/uapi/asm/sigcontext.h @@ -8,6 +8,17 @@ #include +/* The Magic number for signal context frame header. */ +#define RISCV_V_MAGIC 0x53465457 +#define END_MAGIC 0x0 + +/* The size of END signal context header. */ +#define END_HDR_SIZE 0x0 + +struct __sc_riscv_v_state { + struct __riscv_v_ext_state v_state; +} __attribute__((aligned(16))); + /* * Signal context structure * @@ -16,7 +27,10 @@ */ struct sigcontext { struct user_regs_struct sc_regs; - union __riscv_fp_state sc_fpregs; + union { + union __riscv_fp_state sc_fpregs; + struct __riscv_extra_ext_header sc_extdesc; + }; }; #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */ diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 36b026057503..60ebe757ef20 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -262,6 +262,8 @@ static void __init parse_dtb(void) #endif } +extern void __init init_rt_signal_env(void); + void __init setup_arch(char **cmdline_p) { parse_dtb(); @@ -295,6 +297,7 @@ void __init setup_arch(char **cmdline_p) riscv_init_cbo_blocksizes(); riscv_fill_hwcap(); + init_rt_signal_env(); apply_boot_alternatives(); if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 6b4a5c90bd87..c46f3dc039bb 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -19,10 +19,12 @@ #include #include #include +#include #include #include extern u32 __user_rt_sigreturn[2]; +static size_t riscv_v_sc_size __ro_after_init; #define DEBUG_SIG 0 @@ -64,12 +66,87 @@ static long save_fp_state(struct pt_regs *regs, #define restore_fp_state(task, regs) (0) #endif +#ifdef CONFIG_RISCV_ISA_V + +static long save_v_state(struct pt_regs *regs, void __user **sc_vec) +{ + struct __riscv_ctx_hdr __user *hdr; + struct __sc_riscv_v_state __user *state; + void __user *datap; + long err; + + hdr = *sc_vec; + /* Place state to the user's signal context space after the hdr */ + state = (struct __sc_riscv_v_state __user *)(hdr + 1); + /* Point datap right after the end of __sc_riscv_v_state */ + datap = state + 1; + + /* datap is designed to be 16 byte aligned for better performance */ + WARN_ON(unlikely(!IS_ALIGNED((unsigned long)datap, 16))); + + riscv_v_vstate_save(current, regs); + /* Copy everything of vstate but datap. */ + err = __copy_to_user(&state->v_state, ¤t->thread.vstate, + offsetof(struct __riscv_v_ext_state, datap)); + /* Copy the pointer datap itself. */ + err |= __put_user(datap, &state->v_state.datap); + /* Copy the whole vector content to user space datap. */ + err |= __copy_to_user(datap, current->thread.vstate.datap, riscv_v_vsize); + /* Copy magic to the user space after saving all vector conetext */ + err |= __put_user(RISCV_V_MAGIC, &hdr->magic); + err |= __put_user(riscv_v_sc_size, &hdr->size); + if (unlikely(err)) + return err; + + /* Only progress the sv_vec if everything has done successfully */ + *sc_vec += riscv_v_sc_size; + return 0; +} + +/* + * Restore Vector extension context from the user's signal frame. This function + * assumes a valid extension header. So magic and size checking must be done by + * the caller. + */ +static long __restore_v_state(struct pt_regs *regs, void __user *sc_vec) +{ + long err; + struct __sc_riscv_v_state __user *state = sc_vec; + void __user *datap; + + /* Copy everything of __sc_riscv_v_state except datap. */ + err = __copy_from_user(¤t->thread.vstate, &state->v_state, + offsetof(struct __riscv_v_ext_state, datap)); + if (unlikely(err)) + return err; + + /* Copy the pointer datap itself. */ + err = __get_user(datap, &state->v_state.datap); + if (unlikely(err)) + return err; + /* + * Copy the whole vector content from user space datap. Use + * copy_from_user to prevent information leak. + */ + err = copy_from_user(current->thread.vstate.datap, datap, riscv_v_vsize); + if (unlikely(err)) + return err; + + riscv_v_vstate_restore(current, regs); + + return err; +} +#else +#define save_v_state(task, regs) (0) +#define __restore_v_state(task, regs) (0) +#endif + static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { + void __user *sc_ext_ptr = &sc->sc_extdesc.hdr; + __u32 rsvd; long err; - size_t i; - /* sc_regs is structured the same as the start of pt_regs */ err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); if (unlikely(err)) @@ -82,32 +159,81 @@ static long restore_sigcontext(struct pt_regs *regs, return err; } - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) { - u32 value; + /* Check the reserved word before extensions parsing */ + err = __get_user(rsvd, &sc->sc_extdesc.reserved); + if (unlikely(err)) + return err; + if (unlikely(rsvd)) + return -EINVAL; + + while (!err) { + __u32 magic, size; + struct __riscv_ctx_hdr __user *head = sc_ext_ptr; - err = __get_user(value, &sc->sc_fpregs.q.reserved[i]); + err |= __get_user(magic, &head->magic); + err |= __get_user(size, &head->size); if (unlikely(err)) + return err; + + sc_ext_ptr += sizeof(*head); + switch (magic) { + case END_MAGIC: + if (size != END_HDR_SIZE) + return -EINVAL; + + return 0; + case RISCV_V_MAGIC: + if (!has_vector() || !riscv_v_vstate_query(regs) || + size != riscv_v_sc_size) + return -EINVAL; + + err = __restore_v_state(regs, sc_ext_ptr); break; - if (value != 0) + default: return -EINVAL; + } + sc_ext_ptr = (void __user *)head + size; } return err; } +static size_t get_rt_frame_size(void) +{ + struct rt_sigframe __user *frame; + size_t frame_size; + size_t total_context_size = 0; + + frame_size = sizeof(*frame); + + if (has_vector() && riscv_v_vstate_query(task_pt_regs(current))) + total_context_size += riscv_v_sc_size; + /* + * Preserved a __riscv_ctx_hdr for END signal context header if an + * extension uses __riscv_extra_ext_header + */ + if (total_context_size) + total_context_size += sizeof(struct __riscv_ctx_hdr); + + frame_size += total_context_size; + + frame_size = round_up(frame_size, 16); + return frame_size; +} + SYSCALL_DEFINE0(rt_sigreturn) { struct pt_regs *regs = current_pt_regs(); struct rt_sigframe __user *frame; struct task_struct *task; sigset_t set; + size_t frame_size = get_rt_frame_size(); /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; frame = (struct rt_sigframe __user *)regs->sp; - if (!access_ok(frame, sizeof(*frame))) + if (!access_ok(frame, frame_size)) goto badframe; if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) @@ -141,17 +267,22 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, struct pt_regs *regs) { struct sigcontext __user *sc = &frame->uc.uc_mcontext; + struct __riscv_ctx_hdr __user *sc_ext_ptr = &sc->sc_extdesc.hdr; long err; - size_t i; /* sc_regs is structured the same as the start of pt_regs */ err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); /* Save the floating-point state. */ if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) - err |= __put_user(0, &sc->sc_fpregs.q.reserved[i]); + /* Save the vector state. */ + if (has_vector() && riscv_v_vstate_query(regs)) + err |= save_v_state(regs, (void __user **)&sc_ext_ptr); + /* Write zero to fp-reserved space and check it on restore_sigcontext */ + err |= __put_user(0, &sc->sc_extdesc.reserved); + /* And put END __riscv_ctx_hdr at the end. */ + err |= __put_user(END_MAGIC, &sc_ext_ptr->magic); + err |= __put_user(END_HDR_SIZE, &sc_ext_ptr->size); return err; } @@ -176,6 +307,13 @@ static inline void __user *get_sigframe(struct ksignal *ksig, /* Align the stack frame. */ sp &= ~0xfUL; + /* + * Fail if the size of the altstack is not large enough for the + * sigframe construction. + */ + if (current->sas_ss_size && sp < current->sas_ss_sp) + return (void __user __force *)-1UL; + return (void __user *)sp; } @@ -185,9 +323,10 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct rt_sigframe __user *frame; long err = 0; unsigned long __maybe_unused addr; + size_t frame_size = get_rt_frame_size(); - frame = get_sigframe(ksig, regs, sizeof(*frame)); - if (!access_ok(frame, sizeof(*frame))) + frame = get_sigframe(ksig, regs, frame_size); + if (!access_ok(frame, frame_size)) return -EFAULT; err |= copy_siginfo_to_user(&frame->info, &ksig->info); @@ -320,3 +459,10 @@ void arch_do_signal_or_restart(struct pt_regs *regs) */ restore_saved_sigmask(); } + +void init_rt_signal_env(void); +void __init init_rt_signal_env(void) +{ + riscv_v_sc_size = sizeof(struct __riscv_ctx_hdr) + + sizeof(struct __sc_riscv_v_state) + riscv_v_vsize; +} From patchwork Mon Jun 5 11:07:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BE49C7EE23 for ; Mon, 5 Jun 2023 15:42:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235006AbjFEPmN (ORCPT ); Mon, 5 Jun 2023 11:42:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234933AbjFEPl5 (ORCPT ); Mon, 5 Jun 2023 11:41:57 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A2AB1981 for ; Mon, 5 Jun 2023 08:41:33 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1b011cffef2so45845585ad.3 for ; Mon, 05 Jun 2023 08:41:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979679; x=1688571679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MpPHieyVlo9+c3IVReFx0FCE99hnAu9eLlwHEwust2g=; b=ASbUni3uP4QBlGKnA1jDgKxw1LgqQLuh8uABwBOBgPAxn74EU+91YKZFGhbM0N1K7H zSLUEfV+4MQ+PO4AX0M32yA7pU4veQReW+1M91ci/MFm7EmuNw1gAtvQ7oSEMvw/2EbR 0WW/9sav1Dtt+zH615PqAFfB6jyT8ViqkmiEBnlUUU34V7tqQiyPSDUoQeCX7iy1dXdf +uLr/e1KUAx0KHhkc1LXCcI8+YQQ50HO+tnPYSNa/9cy4dOvJ+QEp3U+SwaJROZ+e6ZL PblvsYeRYuhE7w2zg8uKQEgGyr6NnWGdKjnQ2VXxi0RwtMlkWMekOOZaPNvugof8aBc6 K2dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979679; x=1688571679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MpPHieyVlo9+c3IVReFx0FCE99hnAu9eLlwHEwust2g=; b=AMv1lYeGxu6GuMFy4iLl78qqtTYpVEBAutZNYB9O+uizNzl1GZR1XJ2ZJO218dMLz9 kmsvLUd0/1x9LeNMbMeBR+n4hPY4w0YjONTqHRfaIwLWkfDdEHmxcXBwZl+pdpHBl0iz aXD2VYlZZb9T2zifpxecR4i4/BWVdwFhI1a9sb7CcQ/5y+NEparIi0Pgj0t6SY6gqJh6 7ZHCiw1lOnenFKHnUBCyc/4EiQIsycuOI6f9vQwGqcTW6KeFpUlccPLdFsdlyXk4r0NY NJSyzOR6YMWYM/B6E/Y9cfMLVjsQ6OOEapU4KNSN7cyQlw3TzjT6frKF20oxPYerkPi3 bOtQ== X-Gm-Message-State: AC+VfDxFX3hNHEWVoArteLaU5CDct6gD3qi63nUleJS2qz6inf1aQMhY JcoUrE+lmGcVBdidNpfSFQIj8w== X-Google-Smtp-Source: ACHHUZ5i3fvT6T1qemxpcIaS16TmjcZrIINJwytHecFRYPQau81EV/BhCKqVg+3ZMNtrc9oH82kduA== X-Received: by 2002:a17:902:d712:b0:1af:d724:63ed with SMTP id w18-20020a170902d71200b001afd72463edmr7074424ply.42.1685979679176; Mon, 05 Jun 2023 08:41:19 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:18 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Eric Biederman , Kees Cook , Paul Walmsley , Albert Ou , Conor Dooley , Heiko Stuebner , Zong Li , Guo Ren , Kefeng Wang , Sunil V L , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Al Viro , Andrew Bresticker Subject: [PATCH -next v21 15/27] riscv: signal: Report signal frame size to userspace via auxv Date: Mon, 5 Jun 2023 11:07:12 +0000 Message-Id: <20230605110724.21391-16-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Vincent Chen The vector register belongs to the signal context. They need to be stored and restored as entering and leaving the signal handler. According to the V-extension specification, the maximum length of the vector registers can be 2^16. Hence, if userspace refers to the MINSIGSTKSZ to create a sigframe, it may not be enough. To resolve this problem, this patch refers to the commit 94b07c1f8c39c ("arm64: signal: Report signal frame size to userspace via auxv") to enable userspace to know the minimum required sigframe size through the auxiliary vector and use it to allocate enough memory for signal context. Note that auxv always reports size of the sigframe as if V exists for all starting processes, whenever the kernel has CONFIG_RISCV_ISA_V. The reason is that users usually reference this value to allocate an alternative signal stack, and the user may use V anytime. So the user must reserve a space for V-context in sigframe in case that the signal handler invokes after the kernel allocating V. Signed-off-by: Greentime Hu Signed-off-by: Vincent Chen Signed-off-by: Andy Chiu Acked-by: Conor Dooley Reviewed-by: Björn Töpel Reviewed-by: Guo Ren Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- Changelog V19: - Fix a conflict in signal.c due to commit 8d736482749f ("riscv: add icache flush for nommu sigreturn trampoline") --- arch/riscv/include/asm/elf.h | 9 +++++++++ arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/uapi/asm/auxvec.h | 1 + arch/riscv/kernel/signal.c | 20 +++++++++++++++----- 4 files changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index 30e7d2455960..ca23c4f6c440 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -105,6 +105,15 @@ do { \ get_cache_size(3, CACHE_TYPE_UNIFIED)); \ NEW_AUX_ENT(AT_L3_CACHEGEOMETRY, \ get_cache_geometry(3, CACHE_TYPE_UNIFIED)); \ + /* \ + * Should always be nonzero unless there's a kernel bug. \ + * If we haven't determined a sensible value to give to \ + * userspace, omit the entry: \ + */ \ + if (likely(signal_minsigstksz)) \ + NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \ + else \ + NEW_AUX_ENT(AT_IGNORE, 0); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index f0ddf691ac5e..38ded8c5f207 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PROCESSOR_H #include +#include #include @@ -81,6 +82,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); +extern unsigned long signal_minsigstksz __ro_after_init; #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h index fb187a33ce58..10aaa83db89e 100644 --- a/arch/riscv/include/uapi/asm/auxvec.h +++ b/arch/riscv/include/uapi/asm/auxvec.h @@ -35,5 +35,6 @@ /* entries in ARCH_DLINFO */ #define AT_VECTOR_SIZE_ARCH 9 +#define AT_MINSIGSTKSZ 51 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index c46f3dc039bb..f117641c1c49 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -23,6 +23,8 @@ #include #include +unsigned long signal_minsigstksz __ro_after_init; + extern u32 __user_rt_sigreturn[2]; static size_t riscv_v_sc_size __ro_after_init; @@ -197,7 +199,7 @@ static long restore_sigcontext(struct pt_regs *regs, return err; } -static size_t get_rt_frame_size(void) +static size_t get_rt_frame_size(bool cal_all) { struct rt_sigframe __user *frame; size_t frame_size; @@ -205,8 +207,10 @@ static size_t get_rt_frame_size(void) frame_size = sizeof(*frame); - if (has_vector() && riscv_v_vstate_query(task_pt_regs(current))) - total_context_size += riscv_v_sc_size; + if (has_vector()) { + if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) + total_context_size += riscv_v_sc_size; + } /* * Preserved a __riscv_ctx_hdr for END signal context header if an * extension uses __riscv_extra_ext_header @@ -226,7 +230,7 @@ SYSCALL_DEFINE0(rt_sigreturn) struct rt_sigframe __user *frame; struct task_struct *task; sigset_t set; - size_t frame_size = get_rt_frame_size(); + size_t frame_size = get_rt_frame_size(false); /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; @@ -323,7 +327,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct rt_sigframe __user *frame; long err = 0; unsigned long __maybe_unused addr; - size_t frame_size = get_rt_frame_size(); + size_t frame_size = get_rt_frame_size(false); frame = get_sigframe(ksig, regs, frame_size); if (!access_ok(frame, frame_size)) @@ -465,4 +469,10 @@ void __init init_rt_signal_env(void) { riscv_v_sc_size = sizeof(struct __riscv_ctx_hdr) + sizeof(struct __sc_riscv_v_state) + riscv_v_vsize; + /* + * Determine the stack space required for guaranteed signal delivery. + * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry + * in the auxiliary array at process startup. + */ + signal_minsigstksz = get_rt_frame_size(true); } From patchwork Mon Jun 5 11:07:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05F9CC7EE23 for ; Mon, 5 Jun 2023 15:42:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234893AbjFEPmS (ORCPT ); Mon, 5 Jun 2023 11:42:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234900AbjFEPmC (ORCPT ); Mon, 5 Jun 2023 11:42:02 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0888610C7 for ; Mon, 5 Jun 2023 08:41:37 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1b024e29657so22410615ad.3 for ; Mon, 05 Jun 2023 08:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979683; x=1688571683; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=le6WsiFFpntTNhwR6ZdThyFuzfVMTXPYkTAyRr8nwRI=; b=d+VxNOOQAYl7No/bE0Eojd1GYi+MRhT2Pby2jWoSFXSqUG8BgURwze0nShY/toqzYx C/WtCyxZA8GCoZnSCw7mO36blaG/NDggsPeg04KH2aJoaDhPkXVbw9Oz8f/H5Qh1x990 taBoEsUSxj94ml9ML0MwfSzKodLhVwBsLOWyslkDYUSh4VosvqwIltYtzDzD0pnFvn/i hGLMy0SKjDc7WllfsI/57BAJwE0zqYQPa+9VLrBSLjj02U1OUHyHUE2xw172H9W49dJj GLB7YZNAaWZ2R/F8NDODJUWaVu8V5dhYQ+LxFxQi512Vtxs/a/R2XiF7GzRrFS2Qng9h N5Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979683; x=1688571683; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=le6WsiFFpntTNhwR6ZdThyFuzfVMTXPYkTAyRr8nwRI=; b=KbdKpQC6O5DQBIyV3oLMiJFfv73NAIA2HHJ3JHuD4RoNeNChi0xoffxNU8QL3kUTwX crjrXQY9NetZ5mOAqoPc0E1F6TAGsiCkat6/L1gvWYhwJIrs8S6RQ6oyFjCYAcyTKW26 wMHbaHvwV8HpeVtJojhOwl1fIToUGqYw0eqCgNNKzuoMVBf6ermKUtEe/6N5Yr88R8sZ pP330tvT0Dc1vaMiF1zgDWOPCZa4ZSGUG6/7Ls0k93w0KKsXg0lWri3RCukpSGkXT2iY 6ReklvV52mM7cqUCGrKYUNiimWLn11fX51573AvBlIuTTMuYkAjkCBz3O9b2gODuy0rS C4rA== X-Gm-Message-State: AC+VfDz87w8UMHFqWDLoLtceo5Mss79WyepnEmZJl7F+rA8r6nZCLM0Q UwGdCOBSL/U7Sbzb9U+u9xfHOA== X-Google-Smtp-Source: ACHHUZ7q7e7Tg1BdWpbPDPd+Pjd+pgjDAOZ9wkARLO/Bd52hIUUFEEnGT7DcWONAockW3n4coc2/bw== X-Received: by 2002:a17:903:4293:b0:1b0:26f0:4c8e with SMTP id ju19-20020a170903429300b001b026f04c8emr2643302plb.69.1685979683648; Mon, 05 Jun 2023 08:41:23 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:23 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Conor Dooley , Guo Ren , Vincent Chen , Mathis Salmen , Andrew Bresticker Subject: [PATCH -next v21 16/27] riscv: signal: validate altstack to reflect Vector Date: Mon, 5 Jun 2023 11:07:13 +0000 Message-Id: <20230605110724.21391-17-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some extensions, such as Vector, dynamically change footprint on a signal frame, so MINSIGSTKSZ is no longer accurate. For example, an RV64V implementation with vlen = 512 may occupy 2K + 40 + 12 Bytes of a signal frame with the upcoming support. And processes that do not execute any vector instructions do not need to reserve the extra sigframe. So we need a way to guard the allocation size of the sigframe at process runtime according to current status of V. Thus, provide the function sigaltstack_size_valid() to validate its size based on current allocation status of supported extensions. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/kernel/signal.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index f117641c1c49..180d951d3624 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -476,3 +476,10 @@ void __init init_rt_signal_env(void) */ signal_minsigstksz = get_rt_frame_size(true); } + +#ifdef CONFIG_DYNAMIC_SIGFRAME +bool sigaltstack_size_valid(size_t ss_size) +{ + return ss_size > get_rt_frame_size(false); +} +#endif /* CONFIG_DYNAMIC_SIGFRAME */ From patchwork Mon Jun 5 11:07:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FCB1C7EE24 for ; Mon, 5 Jun 2023 15:42:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234982AbjFEPm2 (ORCPT ); Mon, 5 Jun 2023 11:42:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234488AbjFEPmL (ORCPT ); Mon, 5 Jun 2023 11:42:11 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C03A10D9 for ; Mon, 5 Jun 2023 08:41:45 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1b0218c979cso27695505ad.3 for ; Mon, 05 Jun 2023 08:41:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979688; x=1688571688; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=hWB54ZotS7Y2ZgKJV1SIpYTu+cs8XvC1qHz0MxJpXfU=; b=Esj/ZZTYqJr+m/47wLqn93yxPwilBSQY9DZqScr26rPWrlszyo6YSz16bTtNt8IDQK rX0CxTg9bK3R9Qk/VuehmCC5zVee+eLUGkAJF61FKYOnytHvt3SBeemp0CRwVmQK1oQ3 b9bOhGGn4/41IMJdyrtSQoos5VRkZAQwaRQzBwI5zb/8G1IsDyElvhyqDzw4NtQwMwe6 aNK3SFueWP1QPs0Fvtk0FJ2lpqeYHk0TkPRGofeGAJw8pPaP4dCx20Yq3dqc3GLBpoK2 qAkLvljs3175yB6x8x3erHnn3v++fOizgwIEyWSLWgPk4l3lRZthOAl2VhPpxA+z4daQ IeeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979688; x=1688571688; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=hWB54ZotS7Y2ZgKJV1SIpYTu+cs8XvC1qHz0MxJpXfU=; b=NIA/8cd0K5IMTtQLdkThxoEWliTtkvdbiMM8dFAi+Ult+sppXYoQmzgTxLrRDyB99Y nn281Mj5ly4abBXHOKBEEG4Db6Os8wxselWcdzkCBgZINjL0a4y/2UdzplX4+MZfY4n5 dZj2rF2cLpSS7XyI+6G4cF1hJzA0DNfymcNnyaDDwpCV9IDC9KQIYBqWVNs+B3hUJFsW wQRmEnLrCdGdYfm5X7PO1ftRTEl1Q41c8c0KvAYTnpC4+mQtzzwJnoNtTbiAfMsunCd+ 8wd9JhLI+uJUhmhgEbw06aaNnWWKuaWtQ3ywLtsvskfS0SRkJf45yTpKzDsqEJ5MRcrW +srw== X-Gm-Message-State: AC+VfDxhB0tBxVaO8ldA7EUbfckM1o/rRApfsYdvoelxuRGadUr/6QAc Ba+lnesnegBQssM2rYJ/2Sxlew== X-Google-Smtp-Source: ACHHUZ6N216FXg2e2/kWGqQVnVobdh9PysHIotin+oygwyrc5QZdbmX55BlhvwNZar0WBJIE4THX9w== X-Received: by 2002:a17:902:e742:b0:1b2:2305:17a0 with SMTP id p2-20020a170902e74200b001b2230517a0mr1113845plf.32.1685979688000; Mon, 05 Jun 2023 08:41:28 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:27 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, ShihPo Hung , Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Guo Ren , Masahiro Yamada Subject: [PATCH -next v21 17/27] riscv: prevent stack corruption by reserving task_pt_regs(p) early Date: Mon, 5 Jun 2023 11:07:14 +0000 Message-Id: <20230605110724.21391-18-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu Early function calls, such as setup_vm(), relocate_enable_mmu(), soc_early_init() etc, are free to operate on stack. However, PT_SIZE_ON_STACK bytes at the head of the kernel stack are purposedly reserved for the placement of per-task register context pointed by task_pt_regs(p). Those functions may corrupt task_pt_regs if we overlap the $sp with it. In fact, we had accidentally corrupted sstatus.VS in some tests, treating the kernel to save V context before V was actually allocated, resulting in a kernel panic. Thus, we should skip PT_SIZE_ON_STACK for $sp before making C function calls from the top-level assembly. Co-developed-by: ShihPo Hung Signed-off-by: ShihPo Hung Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/kernel/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index e16bb2185d55..11c3b94c4534 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -301,6 +301,7 @@ clear_bss_done: la tp, init_task la sp, init_thread_union + THREAD_SIZE XIP_FIXUP_OFFSET sp + addi sp, sp, -PT_SIZE_ON_STACK #ifdef CONFIG_BUILTIN_DTB la a0, __dtb_start XIP_FIXUP_OFFSET a0 @@ -318,6 +319,7 @@ clear_bss_done: /* Restore C environment */ la tp, init_task la sp, init_thread_union + THREAD_SIZE + addi sp, sp, -PT_SIZE_ON_STACK #ifdef CONFIG_KASAN call kasan_early_init From patchwork Mon Jun 5 11:07:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5159C7EE2C for ; Mon, 5 Jun 2023 15:42:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235018AbjFEPm3 (ORCPT ); Mon, 5 Jun 2023 11:42:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233313AbjFEPmM (ORCPT ); Mon, 5 Jun 2023 11:42:12 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A13910E7 for ; Mon, 5 Jun 2023 08:41:46 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-650bacd6250so2632991b3a.2 for ; Mon, 05 Jun 2023 08:41:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979691; x=1688571691; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=2CmyEkggETxM6j+XfIPwTDc2gU78hVyVqaTRQMELVN4=; b=iCFGyw/jcSbZ7dkgZNFFY73VpPKL7Q1jzPShY52xxnw02H0ROZZFhfGGq3FqayLf/9 ly/kcUznEUd13mFhS/4fFO0qsVJw0y7zessKqUQZU5NYl6XJcbETE9k3+VI3bfzauzN7 KOEhJZQBlfqFkkj7kiD5/x7M9Zp7OcrRMiOPXiOKMidQEl0myq3nIzfLZJE265Cwp48D DDq5QMhhZdBRrQS9dtk77EVtO4TVDZnUl5Qad7SUHDInY2r3au1wJLjBQilARUexc6fi kIVKgoAMwyvK5anHoyXJrR4fWgwo9fP3Yc4FflfywJfMtK2rosH5S/oUSimheAPTH8mQ SzYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979691; x=1688571691; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2CmyEkggETxM6j+XfIPwTDc2gU78hVyVqaTRQMELVN4=; b=TROFcGJfZXpIxR4q6y4DOFKnx+RdPKJaShkKPmiv+Pj3Mjew7oMuY8TLC9oZoXZSgL OqLykP9XsP2rtzbKyaHIJaZaCuNJ2pFQqpry69j7FlnqVm/4CVeEoYR1ARjI1eIv8Zb4 fRF7tBbMNb19oVykYs2OJfkOzLqBk7/r5tBTUksQLc68+wbHl692tp+Crb9qPkPck4H3 T/nUeJQqMHDdiUEov8qodbtu7+t6zhei+e0+Lp3uaDkTXKwPNuEAst/sL4aB8bPhSKDw 2cete2A3ke6VwHp0es1aJBc8xSx1nRW0/hDkCPXQvCozjD0o4yeGItoTYp1PGwK3wLre V9gg== X-Gm-Message-State: AC+VfDwTlEy1VnVIX4w3FaFbzZwpW2HR1crHUFcgR5ShOyiQNChIrqXs Y7wJV/iDqhuO+SaojHZBJZ3BRA== X-Google-Smtp-Source: ACHHUZ4zcDskmXzgjybyy5dRFrqQcD6alz9N7UbXNzqeE3JhCcVu+yZ7RCDNiKVpRYqrwdECITUOcQ== X-Received: by 2002:a17:902:7045:b0:1ae:8b4b:327d with SMTP id h5-20020a170902704500b001ae8b4b327dmr3443354plt.42.1685979691044; Mon, 05 Jun 2023 08:41:31 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:30 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou Subject: [PATCH -next v21 18/27] riscv: kvm: Add V extension to KVM ISA Date: Mon, 5 Jun 2023 11:07:15 +0000 Message-Id: <20230605110724.21391-19-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Vincent Chen Add V extension to KVM isa extension list to enable supporting of V extension on VCPUs. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Anup Patel Acked-by: Anup Patel Reviewed-by: Heiko Stuebner --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index f92790c9481a..8feb57c4c2e8 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -121,6 +121,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZICBOZ, KVM_RISCV_ISA_EXT_ZBB, KVM_RISCV_ISA_EXT_SSAIA, + KVM_RISCV_ISA_EXT_V, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 8bd9f2a8a0b9..f3282ff371ca 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -57,6 +57,7 @@ static const unsigned long kvm_isa_ext_arr[] = { [KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h, [KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i, [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, + [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), From patchwork Mon Jun 5 11:07:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D140C7EE23 for ; Mon, 5 Jun 2023 15:42:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235022AbjFEPme (ORCPT ); Mon, 5 Jun 2023 11:42:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234988AbjFEPmQ (ORCPT ); Mon, 5 Jun 2023 11:42:16 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9DA4E55 for ; Mon, 5 Jun 2023 08:41:51 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-655d1fc8ad8so1025090b3a.1 for ; Mon, 05 Jun 2023 08:41:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979695; x=1688571695; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=zzVQEtVE9GUiE8tfgntIQRd4M5KNUPh8Pcnqg79C1jo=; b=B45UlbrxcY1ZLVhLo0myCimEAnm365MHIqBTv14hVyfrsiTXC/+dYUUCwy9dlKDah9 8vLvVJewRJh7CPHE9+GVm27886IN/PVmCzmjuq2f5Je7Krz7OSUfAmRnFtdg6PD8QSOb 53ttiHCl4srUefAKdKB3l71t7Ozq/Foz6OzgGAgJOD6kIT5JpVuWQkYVVq+mNYUO7UD/ +NOAdjOW8EIsSAEKp0RQrGyuaHEaB19ldCBr6iXl0MMZpVp9X/Gm/VLQKNRzzmahzIxf j1d/EfCiJmJm7hqa2qYPqbyIfkmafDAYGEBuUez68v+V9uYqYXkIgx4P9ogfcCRQUMPq Ca0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979695; x=1688571695; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=zzVQEtVE9GUiE8tfgntIQRd4M5KNUPh8Pcnqg79C1jo=; b=kuint63MgxuvsciKdKFKVpBeTuBsR5NrB5AUvDPmA2wgL2B4fjpgzaB2vtyE95Dxge Htk0dxidZBV5/g0RQdYWyRUoy+JsYZ3MA6aq1ePUPaUMbLYt78XHTKUeSO90rWvM7qU2 U26l6Nm1Yzfce5FjnkgL3tGAx+V94eXrRDFqq01YvtJqkznUkr6V3Vs4oo1Z/J/kJlZ6 TnEKvNBGA6f+2JBLjXjK7/gAZJ19sLUroOrwSzJeMsjJx40jWytwPOUuOzK7x+Q/sT0K WolY27jVzZvGJwHI1119nC3XON/F+K4xsaRG0AikgRdQkf4qScP1yOeRwIGGwHq07p2K 5RRg== X-Gm-Message-State: AC+VfDxi4fsdD55MuHcA+jlQjUMWJKqILApW5SOM4HoPg9K6cSog0gm/ 4lHty/7sM0pLUDSaSlNn3kIJWg== X-Google-Smtp-Source: ACHHUZ6GB1XumMFoVx01X4mEKj4DaHD2fYtPRoAmiRt4NzgID5YLHw4O0l/iOefeWznyOQr79AE/sQ== X-Received: by 2002:a17:902:c94a:b0:1b1:a4b8:4f23 with SMTP id i10-20020a170902c94a00b001b1a4b84f23mr3927072pla.24.1685979695586; Mon, 05 Jun 2023 08:41:35 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:34 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou Subject: [PATCH -next v21 19/27] riscv: KVM: Add vector lazy save/restore support Date: Mon, 5 Jun 2023 11:07:16 +0000 Message-Id: <20230605110724.21391-20-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Vincent Chen This patch adds vector context save/restore for guest VCPUs. To reduce the impact on KVM performance, the implementation imitates the FP context switch mechanism to lazily store and restore the vector context only when the kernel enters/exits the in-kernel run loop and not during the KVM world switch. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Anup Patel Acked-by: Anup Patel --- Changelog V19: - remap V extension registers as type 9 in uapi/asm/kvm.h --- arch/riscv/include/asm/kvm_host.h | 2 + arch/riscv/include/asm/kvm_vcpu_vector.h | 82 ++++++++++ arch/riscv/include/uapi/asm/kvm.h | 7 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 22 +++ arch/riscv/kvm/vcpu_vector.c | 186 +++++++++++++++++++++++ 6 files changed, 300 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_vcpu_vector.h create mode 100644 arch/riscv/kvm/vcpu_vector.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index ee0acccb1d3b..bd47a1dc2ff8 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -145,6 +146,7 @@ struct kvm_cpu_context { unsigned long sstatus; unsigned long hstatus; union __riscv_fp_state fp; + struct __riscv_v_ext_state vector; }; struct kvm_vcpu_csr { diff --git a/arch/riscv/include/asm/kvm_vcpu_vector.h b/arch/riscv/include/asm/kvm_vcpu_vector.h new file mode 100644 index 000000000000..ff994fdd6d0d --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_vector.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 SiFive + * + * Authors: + * Vincent Chen + * Greentime Hu + */ + +#ifndef __KVM_VCPU_RISCV_VECTOR_H +#define __KVM_VCPU_RISCV_VECTOR_H + +#include + +#ifdef CONFIG_RISCV_ISA_V +#include +#include + +static __always_inline void __kvm_riscv_vector_save(struct kvm_cpu_context *context) +{ + __riscv_v_vstate_save(&context->vector, context->vector.datap); +} + +static __always_inline void __kvm_riscv_vector_restore(struct kvm_cpu_context *context) +{ + __riscv_v_vstate_restore(&context->vector, context->vector.datap); +} + +void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx, + unsigned long *isa); +void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx, + unsigned long *isa); +void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx); +void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx); +int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu, + struct kvm_cpu_context *cntx); +void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu); +#else + +struct kvm_cpu_context; + +static inline void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) +{ +} + +static inline void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx, + unsigned long *isa) +{ +} + +static inline void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx, + unsigned long *isa) +{ +} + +static inline void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx) +{ +} + +static inline void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx) +{ +} + +static inline int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu, + struct kvm_cpu_context *cntx) +{ + return 0; +} + +static inline void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu) +{ +} +#endif + +int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype); +int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype); +#endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 8feb57c4c2e8..855c047e86d4 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -204,6 +204,13 @@ enum KVM_RISCV_SBI_EXT_ID { #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) +/* V extension registers are mapped as type 9 */ +#define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ + (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_VECTOR_REG(n) \ + ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 8031b8912a0d..7b4c21f9aa6a 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -17,6 +17,7 @@ kvm-y += mmu.o kvm-y += vcpu.o kvm-y += vcpu_exit.o kvm-y += vcpu_fp.o +kvm-y += vcpu_vector.o kvm-y += vcpu_insn.o kvm-y += vcpu_switch.o kvm-y += vcpu_sbi.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index f3282ff371ca..e5e045852e6a 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { KVM_GENERIC_VCPU_STATS(), @@ -139,6 +141,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) kvm_riscv_vcpu_fp_reset(vcpu); + kvm_riscv_vcpu_vector_reset(vcpu); + kvm_riscv_vcpu_timer_reset(vcpu); kvm_riscv_vcpu_aia_reset(vcpu); @@ -199,6 +203,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) cntx->hstatus |= HSTATUS_SPVP; cntx->hstatus |= HSTATUS_SPV; + if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx)) + return -ENOMEM; + /* By default, make CY, TM, and IR counters accessible in VU mode */ reset_csr->scounteren = 0x7; @@ -242,6 +249,9 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) /* Free unused pages pre-allocated for G-stage page table mappings */ kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); + + /* Free vector context space for host and guest kernel */ + kvm_riscv_vcpu_free_vector_context(vcpu); } int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) @@ -680,6 +690,9 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); case KVM_REG_RISCV_SBI_EXT: return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg); + case KVM_REG_RISCV_VECTOR: + return kvm_riscv_vcpu_set_reg_vector(vcpu, reg, + KVM_REG_RISCV_VECTOR); default: break; } @@ -709,6 +722,9 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg); case KVM_REG_RISCV_SBI_EXT: return kvm_riscv_vcpu_get_reg_sbi_ext(vcpu, reg); + case KVM_REG_RISCV_VECTOR: + return kvm_riscv_vcpu_get_reg_vector(vcpu, reg, + KVM_REG_RISCV_VECTOR); default: break; } @@ -1003,6 +1019,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, vcpu->arch.isa); + kvm_riscv_vcpu_host_vector_save(&vcpu->arch.host_context); + kvm_riscv_vcpu_guest_vector_restore(&vcpu->arch.guest_context, + vcpu->arch.isa); kvm_riscv_vcpu_aia_load(vcpu, cpu); @@ -1022,6 +1041,9 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); kvm_riscv_vcpu_timer_save(vcpu); + kvm_riscv_vcpu_guest_vector_save(&vcpu->arch.guest_context, + vcpu->arch.isa); + kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context); csr->vsstatus = csr_read(CSR_VSSTATUS); csr->vsie = csr_read(CSR_VSIE); diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c new file mode 100644 index 000000000000..edd2eecbddc2 --- /dev/null +++ b/arch/riscv/kvm/vcpu_vector.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 SiFive + * + * Authors: + * Vincent Chen + * Greentime Hu + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_RISCV_ISA_V +void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) +{ + unsigned long *isa = vcpu->arch.isa; + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + + cntx->sstatus &= ~SR_VS; + if (riscv_isa_extension_available(isa, v)) { + cntx->sstatus |= SR_VS_INITIAL; + WARN_ON(!cntx->vector.datap); + memset(cntx->vector.datap, 0, riscv_v_vsize); + } else { + cntx->sstatus |= SR_VS_OFF; + } +} + +static void kvm_riscv_vcpu_vector_clean(struct kvm_cpu_context *cntx) +{ + cntx->sstatus &= ~SR_VS; + cntx->sstatus |= SR_VS_CLEAN; +} + +void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx, + unsigned long *isa) +{ + if ((cntx->sstatus & SR_VS) == SR_VS_DIRTY) { + if (riscv_isa_extension_available(isa, v)) + __kvm_riscv_vector_save(cntx); + kvm_riscv_vcpu_vector_clean(cntx); + } +} + +void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx, + unsigned long *isa) +{ + if ((cntx->sstatus & SR_VS) != SR_VS_OFF) { + if (riscv_isa_extension_available(isa, v)) + __kvm_riscv_vector_restore(cntx); + kvm_riscv_vcpu_vector_clean(cntx); + } +} + +void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx) +{ + /* No need to check host sstatus as it can be modified outside */ + if (riscv_isa_extension_available(NULL, v)) + __kvm_riscv_vector_save(cntx); +} + +void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx) +{ + if (riscv_isa_extension_available(NULL, v)) + __kvm_riscv_vector_restore(cntx); +} + +int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu, + struct kvm_cpu_context *cntx) +{ + cntx->vector.datap = kmalloc(riscv_v_vsize, GFP_KERNEL); + if (!cntx->vector.datap) + return -ENOMEM; + + vcpu->arch.host_context.vector.datap = kzalloc(riscv_v_vsize, GFP_KERNEL); + if (!vcpu->arch.host_context.vector.datap) + return -ENOMEM; + + return 0; +} + +void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu) +{ + kfree(vcpu->arch.guest_reset_context.vector.datap); + kfree(vcpu->arch.host_context.vector.datap); +} +#endif + +static void *kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + size_t reg_size) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + void *reg_val; + size_t vlenb = riscv_v_vsize / 32; + + if (reg_num < KVM_REG_RISCV_VECTOR_REG(0)) { + if (reg_size != sizeof(unsigned long)) + return NULL; + switch (reg_num) { + case KVM_REG_RISCV_VECTOR_CSR_REG(vstart): + reg_val = &cntx->vector.vstart; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vl): + reg_val = &cntx->vector.vl; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vtype): + reg_val = &cntx->vector.vtype; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): + reg_val = &cntx->vector.vcsr; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(datap): + default: + return NULL; + } + } else if (reg_num <= KVM_REG_RISCV_VECTOR_REG(31)) { + if (reg_size != vlenb) + return NULL; + reg_val = cntx->vector.datap + + (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; + } else { + return NULL; + } + + return reg_val; +} + +int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + unsigned long *isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val = NULL; + size_t reg_size = KVM_REG_SIZE(reg->id); + + if (rtype == KVM_REG_RISCV_VECTOR && + riscv_isa_extension_available(isa, v)) { + reg_val = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size); + } + + if (!reg_val) + return -EINVAL; + + if (copy_to_user(uaddr, reg_val, reg_size)) + return -EFAULT; + + return 0; +} + +int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + unsigned long *isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val = NULL; + size_t reg_size = KVM_REG_SIZE(reg->id); + + if (rtype == KVM_REG_RISCV_VECTOR && + riscv_isa_extension_available(isa, v)) { + reg_val = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size); + } + + if (!reg_val) + return -EINVAL; + + if (copy_from_user(reg_val, uaddr, reg_size)) + return -EFAULT; + + return 0; +} From patchwork Mon Jun 5 11:07:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F1DDC7EE24 for ; Mon, 5 Jun 2023 15:42:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234995AbjFEPmf (ORCPT ); Mon, 5 Jun 2023 11:42:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235008AbjFEPmT (ORCPT ); Mon, 5 Jun 2023 11:42:19 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19778E63 for ; Mon, 5 Jun 2023 08:41:53 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1b026657a6fso43036915ad.0 for ; Mon, 05 Jun 2023 08:41:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979702; x=1688571702; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=vWfWpcMCj1+Fb0BnBKmql7KJ370X51psXYGnDJmV9XE=; b=aa2XcqtZLW5iqnaCW4Qqr1H+Tzlig3YdL5foi2KV8ac0ghkespqXccDGXXKNl67dzp ntoXqcpEbUNXvG5jwzxqIS5KwFz8xhHNWI/SGHmvcSQ2teKRNuv/u+rgbNtYZ36omA6S 0gqzwlRCz9zWjL1DPbymwwynFbAGzjHY5NEUVVXmd8WETn/AzMuXGLvdBcqDSf9KZ1j6 v+X+RAJpugMnSnGeorxLAmIlpnxsjubdP5Udp40y6rMZhN9bi60e6YQ2sdLGuMjdvoXz TMfX2v3MjkZ4zJh15+lPq3UDK3JH4uglzBSdGlRDu9xCy0w27inNr0rnqfpXqvQamCjY JT9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979702; x=1688571702; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=vWfWpcMCj1+Fb0BnBKmql7KJ370X51psXYGnDJmV9XE=; b=EbqfIQ7yz/0swH5oNy0VwAsDjsYtpP4g5xTnTNsCbwNLbyOuexyHtCnEXqwrjvmW4P OLrN09WKPJ1ZThvV6ENBjUg3YFeULu/BnyhNpX8O+bROELdD8oX1Rmveo1QaerNv+86v bMTi9IqcgY0MpBWh/bc5OhwME1rwvF8Q58MnApkT9Mg5jMpWGn7TJ+69+6/ELRV5emBq urEBg+fRMfcLmffMUIQHCG0WOFaN+ihe9A5R9ONPBdRVrQo5035cT+RerUuZUwv9OBWQ lxShnzvINNO9ZL22uiqTrvHaA54V7tpDtowmACNlY71bafi/Ogm35UNitu/ire2kia8M Wl/A== X-Gm-Message-State: AC+VfDz4FIrm6/pBtiePFrn31u7uEYrSXuZjNIPlMU32UXGZXxKHbkjE Bp72bTKM7xIJlS0f82TuS70DxQ== X-Google-Smtp-Source: ACHHUZ5ALSUm1i1u3l9MlL1FkN2klEz94jSTED1PaH9Zd5Uees8rVfXo4MbbiVQ0JqYoJeYPnONJ1g== X-Received: by 2002:a17:903:24c:b0:1ad:f138:b2f6 with SMTP id j12-20020a170903024c00b001adf138b2f6mr8809583plh.16.1685979702314; Mon, 05 Jun 2023 08:41:42 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:41 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Eric Biederman , Kees Cook , Paul Walmsley , Albert Ou , Conor Dooley , Heiko Stuebner , Vincent Chen , Andrew Jones , Anup Patel , Jisheng Zhang , Guo Ren Subject: [PATCH -next v21 20/27] riscv: hwcap: change ELF_HWCAP to a function Date: Mon, 5 Jun 2023 11:07:17 +0000 Message-Id: <20230605110724.21391-21-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Using a function is flexible to represent ELF_HWCAP. So the kernel may encode hwcap reflecting supported hardware features just at the moment of the start of each program. This will be helpful when we introduce prctl/sysctl interface to control per-process availability of Vector extension in following patches. Programs started with V disabled should see V masked off in theirs ELF_HWCAP. Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- arch/riscv/include/asm/elf.h | 2 +- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 5 +++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index ca23c4f6c440..c24280774caf 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -66,7 +66,7 @@ extern bool compat_elf_check_arch(Elf32_Ehdr *hdr); * via a bitmap that coorespends to each single-letter ISA extension. This is * essentially defunct, but will remain for compatibility with userspace. */ -#define ELF_HWCAP (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)) +#define ELF_HWCAP riscv_get_elf_hwcap() extern unsigned long elf_hwcap; /* diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 574385930ba7..e6c288ac4581 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -61,6 +61,8 @@ #include +unsigned long riscv_get_elf_hwcap(void); + struct riscv_isa_ext_data { /* Name of the extension displayed to userspace via /proc/cpuinfo */ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 28032b083463..29c0680652a0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -293,6 +293,11 @@ void __init riscv_fill_hwcap(void) pr_info("riscv: ELF capabilities %s\n", print_str); } +unsigned long riscv_get_elf_hwcap(void) +{ + return (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); +} + #ifdef CONFIG_RISCV_ALTERNATIVE /* * Alternative patch sites consider 48 bits when determining when to patch From patchwork Mon Jun 5 11:07:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65F42C7EE24 for ; Mon, 5 Jun 2023 15:42:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234974AbjFEPmi (ORCPT ); Mon, 5 Jun 2023 11:42:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234920AbjFEPmW (ORCPT ); Mon, 5 Jun 2023 11:42:22 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56BDC10FB for ; Mon, 5 Jun 2023 08:41:59 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-653fcd58880so1421077b3a.0 for ; Mon, 05 Jun 2023 08:41:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979715; x=1688571715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c9bujJ7N1UFjifnLB5UKivr77scgVbFfCLxMXVtnvRk=; b=RNEwRUGeyVtDJkZ4XDefPZDmAd3JluYqniGwyF2/7I6IIBndBe1rJ6MpEseAE4yFWR awqM37LzP4xW4F6WPLVWOphMJ4tcQvbYHdknw7xx5pF4VD0Fo5KnmZejApf6YdPGZ+RG /mlHl9S68wXrvUQ5tUnn2RdKeHRvXtudh5G+ttd155GTAWXFrrUgMAfhaYKBD84/YXH2 BplKQFytXe6BzwAfnBXCcBSg9wagOCYPO41WmDEarebujcu0SgwLhTSRglWK/vJ1gCnE 2JjJ5gwZKzeNiZgQLnl9Jf8x/fTtkLrjD1husoPqzgsKFa1PWA2GoULGrXgxKzr6zBaH +/8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979715; x=1688571715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c9bujJ7N1UFjifnLB5UKivr77scgVbFfCLxMXVtnvRk=; b=UN8ul+IcmME4I2YmAgWMllclVkwazz3B/Oa4xDq1BfwTvhGReED/f8aB3N68YUDBXo i7rYta7uytgbmRfN8vuhxc2pgo0qLPl+Dl27agf3QdH1b9f+6ONy+9orZ+Ab3K+A5MLa m4ZP+x7eL0s2z9q30rwLeFmBaUFNe8kEgA51BRxxlyS3lujmkieMDxLy74wFMs2XQiNa RjGRBRSfXJ0Sc8lZCVc7qGrif4DzH/eNJ1W64U4q5cwG4vi4a/pYCzDzlYaPZ6Qsp4Lu wZbvf4fR0chvg+U4Cnsujxlk0NfBsvZgbTEAVUAN9Td5Dp+xik1CoWf/KYVAxYs3JQHr VRNA== X-Gm-Message-State: AC+VfDzu2JAwJ/3eOvzuf8+5hEt7pL/7Ijw9C8NX85zKjbJ9qp6DU9UO ClcWtNO1A/4nw+JVxacqljsn7A== X-Google-Smtp-Source: ACHHUZ5WzGqVJ/jAXvFY7sfjpnI9ESq5k6PdlASqY0y6wiA/69ciZyWliPxAeAFdqHn5yRJtLErltA== X-Received: by 2002:a17:902:be17:b0:1b0:7c3c:31ed with SMTP id r23-20020a170902be1700b001b07c3c31edmr3306578pls.25.1685979714903; Mon, 05 Jun 2023 08:41:54 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:54 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Vincent Chen , Heiko Stuebner , Sunil V L , Kefeng Wang , Conor Dooley , Andrew Jones , Jisheng Zhang , Peter Zijlstra , Andrew Morton , Catalin Marinas , David Hildenbrand , Josh Triplett , Joey Gouly , Stefan Roesch , Jordy Zomer , "Jason A. Donenfeld" , Ondrej Mosnacek Subject: [PATCH -next v21 21/27] riscv: Add prctl controls for userspace vector management Date: Mon, 5 Jun 2023 11:07:18 +0000 Message-Id: <20230605110724.21391-22-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This patch add two riscv-specific prctls, to allow usespace control the use of vector unit: * PR_RISCV_V_SET_CONTROL: control the permission to use Vector at next, or all following execve for a thread. Turning off a thread's Vector live is not possible since libraries may have registered ifunc that may execute Vector instructions. * PR_RISCV_V_GET_CONTROL: get the same permission setting for the current thread, and the setting for following execve(s). Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Reviewed-by: Vincent Chen --- Changelog v21: - Remove the check in riscv_v_first_use_handler() because it is checked in ELF_HWCAP. - Mask off COMPAT_HWCAP_ISA_V in ELF_HWCAP when the user process is not allowed to use it. - properly define RISCV_V_{GET,SET}_CONTROL and remove unecessary #else clause. (Björn) Changelog v20: - address build issue when KVM is compile as a module (Heiko) - s/RISCV_V_DISABLE/RISCV_ISA_V_DEFAULT_ENABLE/ (Conor) - change function names to have better scoping - check has_vector() before accessing vstate_ctrl - use proper return type for prctl calls (long instead of uint) --- arch/riscv/include/asm/processor.h | 10 +++ arch/riscv/include/asm/vector.h | 4 + arch/riscv/kernel/cpufeature.c | 9 ++- arch/riscv/kernel/process.c | 1 + arch/riscv/kernel/vector.c | 114 +++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu.c | 2 + include/uapi/linux/prctl.h | 11 +++ kernel/sys.c | 12 +++ 8 files changed, 162 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 38ded8c5f207..e82af1097e26 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -40,6 +40,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + unsigned long vstate_ctrl; struct __riscv_v_ext_state vstate; }; @@ -83,6 +84,15 @@ extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); extern unsigned long signal_minsigstksz __ro_after_init; + +#ifdef CONFIG_RISCV_ISA_V +/* Userspace interface for PR_RISCV_V_{SET,GET}_VS prctl()s: */ +#define RISCV_V_SET_CONTROL(arg) riscv_v_vstate_ctrl_set_current(arg) +#define RISCV_V_GET_CONTROL() riscv_v_vstate_ctrl_get_current() +extern long riscv_v_vstate_ctrl_set_current(unsigned long arg); +extern long riscv_v_vstate_ctrl_get_current(void); +#endif /* CONFIG_RISCV_ISA_V */ + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 8e56da67b5cf..04c0b07bf6cd 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -160,6 +160,9 @@ static inline void __switch_to_vector(struct task_struct *prev, riscv_v_vstate_restore(next, task_pt_regs(next)); } +void riscv_v_vstate_ctrl_init(struct task_struct *tsk); +bool riscv_v_vstate_ctrl_user_allowed(void); + #else /* ! CONFIG_RISCV_ISA_V */ struct pt_regs; @@ -168,6 +171,7 @@ static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } static __always_inline bool has_vector(void) { return false; } static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } +static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } #define riscv_v_vsize (0) #define riscv_v_vstate_save(task, regs) do {} while (0) #define riscv_v_vstate_restore(task, regs) do {} while (0) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 29c0680652a0..8ae43e40fffc 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -295,7 +295,14 @@ void __init riscv_fill_hwcap(void) unsigned long riscv_get_elf_hwcap(void) { - return (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); + unsigned long hwcap; + + hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); + + if (!riscv_v_vstate_ctrl_user_allowed()) + hwcap &= ~COMPAT_HWCAP_ISA_V; + + return hwcap; } #ifdef CONFIG_RISCV_ALTERNATIVE diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 78eb5ac45888..e32d737e039f 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -149,6 +149,7 @@ void flush_thread(void) #endif #ifdef CONFIG_RISCV_ISA_V /* Reset vector state */ + riscv_v_vstate_ctrl_init(current); riscv_v_vstate_off(task_pt_regs(current)); kfree(current->thread.vstate.datap); memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 9d81d1b2a7f3..a7dec9230164 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -19,6 +20,8 @@ #include #include +static bool riscv_v_implicit_uacc = IS_ENABLED(CONFIG_RISCV_ISA_V_DEFAULT_ENABLE); + unsigned long riscv_v_vsize __read_mostly; EXPORT_SYMBOL_GPL(riscv_v_vsize); @@ -91,6 +94,43 @@ static int riscv_v_thread_zalloc(void) return 0; } +#define VSTATE_CTRL_GET_CUR(x) ((x) & PR_RISCV_V_VSTATE_CTRL_CUR_MASK) +#define VSTATE_CTRL_GET_NEXT(x) (((x) & PR_RISCV_V_VSTATE_CTRL_NEXT_MASK) >> 2) +#define VSTATE_CTRL_MAKE_NEXT(x) (((x) << 2) & PR_RISCV_V_VSTATE_CTRL_NEXT_MASK) +#define VSTATE_CTRL_GET_INHERIT(x) (!!((x) & PR_RISCV_V_VSTATE_CTRL_INHERIT)) +static inline int riscv_v_ctrl_get_cur(struct task_struct *tsk) +{ + return VSTATE_CTRL_GET_CUR(tsk->thread.vstate_ctrl); +} + +static inline int riscv_v_ctrl_get_next(struct task_struct *tsk) +{ + return VSTATE_CTRL_GET_NEXT(tsk->thread.vstate_ctrl); +} + +static inline bool riscv_v_ctrl_test_inherit(struct task_struct *tsk) +{ + return VSTATE_CTRL_GET_INHERIT(tsk->thread.vstate_ctrl); +} + +static inline void riscv_v_ctrl_set(struct task_struct *tsk, int cur, int nxt, + bool inherit) +{ + unsigned long ctrl; + + ctrl = cur & PR_RISCV_V_VSTATE_CTRL_CUR_MASK; + ctrl |= VSTATE_CTRL_MAKE_NEXT(nxt); + if (inherit) + ctrl |= PR_RISCV_V_VSTATE_CTRL_INHERIT; + tsk->thread.vstate_ctrl = ctrl; +} + +bool riscv_v_vstate_ctrl_user_allowed(void) +{ + return riscv_v_ctrl_get_cur(current) == PR_RISCV_V_VSTATE_CTRL_ON; +} +EXPORT_SYMBOL_GPL(riscv_v_vstate_ctrl_user_allowed); + bool riscv_v_first_use_handler(struct pt_regs *regs) { u32 __user *epc = (u32 __user *)regs->epc; @@ -129,3 +169,77 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) riscv_v_vstate_on(regs); return true; } + +void riscv_v_vstate_ctrl_init(struct task_struct *tsk) +{ + bool inherit; + int cur, next; + + if (!has_vector()) + return; + + next = riscv_v_ctrl_get_next(tsk); + if (!next) { + if (riscv_v_implicit_uacc) + cur = PR_RISCV_V_VSTATE_CTRL_ON; + else + cur = PR_RISCV_V_VSTATE_CTRL_OFF; + } else { + cur = next; + } + /* Clear next mask if inherit-bit is not set */ + inherit = riscv_v_ctrl_test_inherit(tsk); + if (!inherit) + next = PR_RISCV_V_VSTATE_CTRL_DEFAULT; + + riscv_v_ctrl_set(tsk, cur, next, inherit); +} + +long riscv_v_vstate_ctrl_get_current(void) +{ + if (!has_vector()) + return -EINVAL; + + return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; +} + +long riscv_v_vstate_ctrl_set_current(unsigned long arg) +{ + bool inherit; + int cur, next; + + if (!has_vector()) + return -EINVAL; + + if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) + return -EINVAL; + + cur = VSTATE_CTRL_GET_CUR(arg); + switch (cur) { + case PR_RISCV_V_VSTATE_CTRL_OFF: + /* Do not allow user to turn off V if current is not off */ + if (riscv_v_ctrl_get_cur(current) != PR_RISCV_V_VSTATE_CTRL_OFF) + return -EPERM; + + break; + case PR_RISCV_V_VSTATE_CTRL_ON: + break; + case PR_RISCV_V_VSTATE_CTRL_DEFAULT: + cur = riscv_v_ctrl_get_cur(current); + break; + default: + return -EINVAL; + } + + next = VSTATE_CTRL_GET_NEXT(arg); + inherit = VSTATE_CTRL_GET_INHERIT(arg); + switch (next) { + case PR_RISCV_V_VSTATE_CTRL_DEFAULT: + case PR_RISCV_V_VSTATE_CTRL_OFF: + case PR_RISCV_V_VSTATE_CTRL_ON: + riscv_v_ctrl_set(current, cur, next, inherit); + return 0; + } + + return -EINVAL; +} diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e5e045852e6a..de24127e7e93 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -88,6 +88,8 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) switch (ext) { case KVM_RISCV_ISA_EXT_H: return false; + case KVM_RISCV_ISA_EXT_V: + return riscv_v_vstate_ctrl_user_allowed(); default: break; } diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index f23d9a16507f..3c36aeade991 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -294,4 +294,15 @@ struct prctl_mm_map { #define PR_SET_MEMORY_MERGE 67 #define PR_GET_MEMORY_MERGE 68 + +#define PR_RISCV_V_SET_CONTROL 69 +#define PR_RISCV_V_GET_CONTROL 70 +# define PR_RISCV_V_VSTATE_CTRL_DEFAULT 0 +# define PR_RISCV_V_VSTATE_CTRL_OFF 1 +# define PR_RISCV_V_VSTATE_CTRL_ON 2 +# define PR_RISCV_V_VSTATE_CTRL_INHERIT (1 << 4) +# define PR_RISCV_V_VSTATE_CTRL_CUR_MASK 0x3 +# define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc +# define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index 339fee3eff6a..05f838929e72 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -140,6 +140,12 @@ #ifndef GET_TAGGED_ADDR_CTRL # define GET_TAGGED_ADDR_CTRL() (-EINVAL) #endif +#ifndef RISCV_V_SET_CONTROL +# define RISCV_V_SET_CONTROL(a) (-EINVAL) +#endif +#ifndef RISCV_V_GET_CONTROL +# define RISCV_V_GET_CONTROL() (-EINVAL) +#endif /* * this is where the system-wide overflow UID and GID are defined, for @@ -2708,6 +2714,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, arg2, unsigned long, arg3, error = !!test_bit(MMF_VM_MERGE_ANY, &me->mm->flags); break; #endif + case PR_RISCV_V_SET_CONTROL: + error = RISCV_V_SET_CONTROL(arg2); + break; + case PR_RISCV_V_GET_CONTROL: + error = RISCV_V_GET_CONTROL(); + break; default: error = -EINVAL; break; From patchwork Mon Jun 5 11:07:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3FD9C7EE2D for ; Mon, 5 Jun 2023 15:42:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234910AbjFEPmj (ORCPT ); Mon, 5 Jun 2023 11:42:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235003AbjFEPmY (ORCPT ); Mon, 5 Jun 2023 11:42:24 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22474FF for ; Mon, 5 Jun 2023 08:42:03 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1b01d912924so46013955ad.1 for ; Mon, 05 Jun 2023 08:42:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979720; x=1688571720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BBfW759GkKFTzUJgKoX8uA384VuYsPAE0vmOulKke4E=; b=GsQQh15wVmlQHwcRg9bvdxbzEsIGOVvPRMdnOxcyy4n1fhB5ont6tYc4awzRi/gt3O iUjoTaMkIWsWK3dH28thritzx0yAslkk+BN2vdV4D6204M0SFaEXtwQIAPi1NkVGUlgZ C0YxsDT87raETp6RcOovcG213qgc6eXcPP4GnOrMXNocbyxafgrBSR/q1SMnnFWWHjx/ nbbaTY7phpfSP2g2ij0o/oT2WEwFNAkw8pO3JDBmiWyqybqBGlk1B8dPl+fWDDXVYY6K H1+vfHwTaM+2A4/c/5UQZiCygzg6nJBGzkMLLYF8eci8uvftIgKmacSvOb9nuweRi/FQ qiVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979720; x=1688571720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BBfW759GkKFTzUJgKoX8uA384VuYsPAE0vmOulKke4E=; b=lh4HRvKnH3HdfpmDreGXhO3JyOapw9Pl/sDpZGa4wKkdbYQC0kYuVw6cmPV/rGMVi9 GWMzPmgeie2osPyC2OeKPgGSZXTeZGuoab2jWV339RTPQcwChkQoBiY7qtgE/jglJpde FIhK3tCmNMVX8A00IqJ7suRlmA5KDUfY/VyDO84q00dyrsED9bE896syTLNTiNEx0qhL uG+t5DUm6kSAip5wraV7/+jawMzVkBdzjpn+DOI0K6rSDrYGcCTwVERNw8eHD7lIp457 PpYNx1UK+Ge/8B/fdUA2Dgan+Zu29Z2+p0gv1qzaBl9cQFjBaOpHV3moga8j+LPXOANP QbQQ== X-Gm-Message-State: AC+VfDwuJ+vbjLhuxHp+8QYhxhxfycAccBnB2fWL9VoeUBthrn/0IN9/ lCsopPz99yO7JKHUW/I1W4mrhg== X-Google-Smtp-Source: ACHHUZ7rKTugKoVEziJV+gkC7XJI8FhQ4EESaFrT4CkW2ElkLsjNLgehEW4rqgWAicr6PBGWCEKbdQ== X-Received: by 2002:a17:902:ecc2:b0:1b0:42d1:ecd0 with SMTP id a2-20020a170902ecc200b001b042d1ecd0mr8656899plh.66.1685979719813; Mon, 05 Jun 2023 08:41:59 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:41:59 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Vincent Chen , Heiko Stuebner , Guo Ren Subject: [PATCH -next v21 22/27] riscv: Add sysctl to set the default vector rule for new processes Date: Mon, 5 Jun 2023 11:07:19 +0000 Message-Id: <20230605110724.21391-23-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To support Vector extension, the series exports variable-length vector registers on the signal frame. However, this potentially breaks abi if processing vector registers is required in the signal handler for old binaries. For example, there is such need if user-level context switch is triggerred via signals[1]. For this reason, it is best to leave a decision to distro maintainers, where the enablement of userspace Vector for new launching programs can be controlled. Developers may also need the switch to experiment with. The parameter is configurable through sysctl interface so a distro may turn off Vector early at init script if the break really happens in the wild. The switch will only take effects on new execve() calls once set. This will not effect existing processes that do not call execve(), nor processes which has been set with a non-default vstate_ctrl by making explicit PR_RISCV_V_SET_CONTROL prctl() calls. Link: https://lore.kernel.org/all/87cz4048rp.fsf@all.your.base.are.belong.to.us/ Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Reviewed-by: Vincent Chen Reviewed-by: Björn Töpel --- Changelog v20: - Use READ_ONCE to access riscv_v_implicit_uacc (Björn) --- arch/riscv/kernel/vector.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index a7dec9230164..f9c8e19ab301 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -180,7 +180,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) next = riscv_v_ctrl_get_next(tsk); if (!next) { - if (riscv_v_implicit_uacc) + if (READ_ONCE(riscv_v_implicit_uacc)) cur = PR_RISCV_V_VSTATE_CTRL_ON; else cur = PR_RISCV_V_VSTATE_CTRL_OFF; @@ -243,3 +243,34 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) return -EINVAL; } + +#ifdef CONFIG_SYSCTL + +static struct ctl_table riscv_v_default_vstate_table[] = { + { + .procname = "riscv_v_default_allow", + .data = &riscv_v_implicit_uacc, + .maxlen = sizeof(riscv_v_implicit_uacc), + .mode = 0644, + .proc_handler = proc_dobool, + }, + { } +}; + +static int __init riscv_v_sysctl_init(void) +{ + if (has_vector()) + if (!register_sysctl("abi", riscv_v_default_vstate_table)) + return -EINVAL; + return 0; +} + +#else /* ! CONFIG_SYSCTL */ +static int __init riscv_v_sysctl_init(void) { return 0; } +#endif /* ! CONFIG_SYSCTL */ + +static int riscv_v_init(void) +{ + return riscv_v_sysctl_init(); +} +core_initcall(riscv_v_init); From patchwork Mon Jun 5 11:07:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFA17C7EE2F for ; Mon, 5 Jun 2023 15:42:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235008AbjFEPml (ORCPT ); Mon, 5 Jun 2023 11:42:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234975AbjFEPm0 (ORCPT ); Mon, 5 Jun 2023 11:42:26 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C1E01B4 for ; Mon, 5 Jun 2023 08:42:04 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1b041ccea75so25803645ad.2 for ; Mon, 05 Jun 2023 08:42:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979723; x=1688571723; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=otAeXCQ9wHQgYb9XVLjxDELtJAEuURMD8rtVKOhLCTY=; b=GICIV0NT3It7ucO3UJ2gZ3jwWoXXmy+OwT1H5NbInsfp5nA4wkafaRhlHFTstvSRBh HrgwpW4h5xWhdHU5ITjegRyaHLqfW/L89qevzwb/bAUBVlOWqU/GD9cTUDJw+9R0DgPD ZNa/KLi6O4dbI/4ZDzUkMkfn4AfssCHHZJ5Pm0FE7BbjdNhDoxhx+H7EdiUDcz9LSAWr byidMK6H48ZqoRk44q3djMvlCoVRFxk+nACOTzIASAunp7MtsAYRVcijCCZK1YtiHUlK 24/fRBlKkn6Tztjd2kjYHpbXuK6mIt/MK7OyBI9bq1b05GLmBZ8siaMHqDSlmWIZ5sL4 dDzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979723; x=1688571723; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=otAeXCQ9wHQgYb9XVLjxDELtJAEuURMD8rtVKOhLCTY=; b=Wf7v6QrIJv0vxOUbBzTDdvxnu7ZSm3jChyhVI0sy0cN1DgRiQkWY41rYZVlAY0xLKQ X8tIXqaOdnNJih0jqFf+dJKnwhUxBIZrHeM4kSzvagKuuA7lUpyDmdjs4IzxshxhTE0+ 2oImmwp+pJIFSHkwwK6BTf5eDtl4YRLbWeEeQqLwCL0yVC+xBp5ib2o97wMicVJ9Lazj VPRqDNtK6EKPjjzcvMb/Nd4ZoTmIWurwz6VSs/geFQEdRFFhZr3ikZWPodlP7N3/GxsU a+oL48EHunpTkQ63cqCFSWp4BRd7jaYryxqcyPe7LM/ZhjoodY0D5QOYyMuIRyuBw45l Ydeg== X-Gm-Message-State: AC+VfDyx9UWSTRQxBBnFw7lpWeSWVZwvyt1ACcHeVhH6DYhvtmuRk/nl ZGL/wEnflGJYvpY8/Sm3ASlLFA== X-Google-Smtp-Source: ACHHUZ43cS6OalvTGtWBOXIW7qcclVUVLOPKWYSft4n7VdSMybpc1v45G04KlhkE9QfwM2PE1BpY6A== X-Received: by 2002:a17:902:7008:b0:1ab:eee:c5d7 with SMTP id y8-20020a170902700800b001ab0eeec5d7mr4014641plk.48.1685979723069; Mon, 05 Jun 2023 08:42:03 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:42:02 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Nathan Chancellor , Nick Desaulniers , Tom Rix Subject: [PATCH -next v21 23/27] riscv: detect assembler support for .option arch Date: Mon, 5 Jun 2023 11:07:20 +0000 Message-Id: <20230605110724.21391-24-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Some extensions use .option arch directive to selectively enable certain extensions in parts of its assembly code. For example, Zbb uses it to inform assmebler to emit bit manipulation instructions. However, supporting of this directive only exist on GNU assembler and has not landed on clang at the moment, making TOOLCHAIN_HAS_ZBB depend on AS_IS_GNU. While it is still under review at https://reviews.llvm.org/D123515, the upcoming Vector patch also requires this feature in assembler. Thus, provide Kconfig AS_HAS_OPTION_ARCH to detect such feature. Then TOOLCHAIN_HAS_XXX will be turned on automatically when the feature land. Suggested-by: Nathan Chancellor Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley Reviewed-by: Nathan Chancellor Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/Kconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 348c0fa1fc8c..1019b519d590 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -262,6 +262,12 @@ config RISCV_DMA_NONCOHERENT config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) +config AS_HAS_OPTION_ARCH + # https://reviews.llvm.org/D123515 + def_bool y + depends on $(as-instr, .option arch$(comma) +m) + depends on !$(as-instr, .option arch$(comma) -i) + source "arch/riscv/Kconfig.socs" source "arch/riscv/Kconfig.errata" @@ -466,7 +472,7 @@ config TOOLCHAIN_HAS_ZBB depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb) depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900 - depends on AS_IS_GNU + depends on AS_HAS_OPTION_ARCH config RISCV_ISA_ZBB bool "Zbb extension support for bit manipulation instructions" From patchwork Mon Jun 5 11:07:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D748FC7EE23 for ; Mon, 5 Jun 2023 15:42:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235025AbjFEPmo (ORCPT ); Mon, 5 Jun 2023 11:42:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233845AbjFEPm2 (ORCPT ); Mon, 5 Jun 2023 11:42:28 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88937E6D for ; Mon, 5 Jun 2023 08:42:07 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1b00ecabdf2so45898145ad.2 for ; Mon, 05 Jun 2023 08:42:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979726; x=1688571726; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=3oGenUq2RmcAiga8rk96QsXqWKk89kTrI2+LG1B6lNo=; b=hQZT1Syqd3WtW8aZx2yL/w89kYn6X8sgyQjCm8QWqksNUZOcoovtC3D3JKxG7IrK70 DacMox7pscej6plzIkxm9QISF6CSw5o8B2RYzAnKgNBhFIim/pAoZO8+kz1jfvDA7t+2 ToQdoWsTEdq+EFz6n5LTWOQPGGw266O1UreTXy/f8aC3wvaBXq4qFXRrGcXZqQif615L MqkMD+a23PbI87CKTXHgEOzqNfq56zWReyp/iXOhjOizh7jXOlpi+ph3+aIVoH6ft+vz vHAfHvXIO9R3XIxFnGR3cU/u2qPOmkdie7B218Ah+q7l/PSSML/BTKH6NpWTk4DO8tm0 Quaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979726; x=1688571726; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=3oGenUq2RmcAiga8rk96QsXqWKk89kTrI2+LG1B6lNo=; b=BXgEHWQxMPkE0Cp4AZwWsgwHAqBeufyiOnywKoqHgGlIQQF36T+MZsX3eOqr0mkDvy LGFgT2v4bvAlzCz8ngHqgzh0HQoQrsITOTRNwX5KvLeTDyYBIZ8C1j5mcCpWy0qcf/WQ WJKsu5hiNgsLqPout7+rlOP168hahIfIda/RbcEr5ppenxMor5S2nv24OscR9bVRRmH3 YzWTPN65E9na8oIJ+IP9jJBqoe4KJsiFkP9SeCvdo7A/oevNj8EdMrFZRILqdAKNUIaj 75fM21pUqNudStZgLRBWTWCMH7gKvNjoCYwIDY38x5ahs9JHFP7TslChLprDtsZdz9wz 0zLw== X-Gm-Message-State: AC+VfDyG9NmrApSM7SoHDTS6wsKbqjZu1T0fraJZW3ldn/dlePFuMGWu 3r/YCmhGNSxkRWoUe7Kv1PfxdQ== X-Google-Smtp-Source: ACHHUZ6/3qltkidsVKYwQs6O3CFhkrECdKQdl6va7midlwG7wplu8QV7xOfVwrVED1s5/OkG1YraQA== X-Received: by 2002:a17:902:ea04:b0:1a9:b8c3:c2c2 with SMTP id s4-20020a170902ea0400b001a9b8c3c2c2mr9570619plg.37.1685979725981; Mon, 05 Jun 2023 08:42:05 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.42.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:42:05 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou Subject: [PATCH -next v21 24/27] riscv: Enable Vector code to be built Date: Mon, 5 Jun 2023 11:07:21 +0000 Message-Id: <20230605110724.21391-25-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren This patch adds configs for building Vector code. First it detects the reqired toolchain support for building the code. Then it provides an option setting whether Vector is implicitly enabled to userspace. Signed-off-by: Guo Ren Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu Co-developed-by: Andy Chiu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- Changelog v20: - s/RISCV_V_DISABLE/RISCV_ISA_V_DEFAULT_ENABLE/ for better understanding (Conor) - Update commit message (Conor) Changelog V19: - Add RISCV_V_DISABLE to set compile-time default. --- arch/riscv/Kconfig | 31 +++++++++++++++++++++++++++++++ arch/riscv/Makefile | 6 +++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1019b519d590..f3ba0a8b085e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -466,6 +466,37 @@ config RISCV_ISA_SVPBMT If you don't know what to do here, say Y. +config TOOLCHAIN_HAS_V + bool + default y + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv) + depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800 + depends on AS_HAS_OPTION_ARCH + +config RISCV_ISA_V + bool "VECTOR extension support" + depends on TOOLCHAIN_HAS_V + depends on FPU + select DYNAMIC_SIGFRAME + default y + help + Say N here if you want to disable all vector related procedure + in the kernel. + + If you don't know what to do here, say Y. + +config RISCV_ISA_V_DEFAULT_ENABLE + bool "Enable userspace Vector by default" + depends on RISCV_ISA_V + default y + help + Say Y here if you want to enable Vector in userspace by default. + Otherwise, userspace has to make explicit prctl() call to enable + Vector, or enable it via the sysctl interface. + + If you don't know what to do here, say Y. + config TOOLCHAIN_HAS_ZBB bool default y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0fb256bf8270..6ec6d52a4180 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -60,6 +60,7 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC KBUILD_CFLAGS += -Wa,-misa-spec=2.2 @@ -71,7 +72,10 @@ endif # Check if the toolchain supports Zihintpause extension riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause -KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) +# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by +# matching non-v and non-multi-letter extensions out with the filter ([^v_]*) +KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/') + KBUILD_AFLAGS += -march=$(riscv-march-y) KBUILD_CFLAGS += -mno-save-restore From patchwork Mon Jun 5 11:07:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1515C7EE23 for ; Mon, 5 Jun 2023 15:43:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235024AbjFEPnE (ORCPT ); Mon, 5 Jun 2023 11:43:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234908AbjFEPmf (ORCPT ); Mon, 5 Jun 2023 11:42:35 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC2CCE78 for ; Mon, 5 Jun 2023 08:42:14 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1b011cffe7fso22518415ad.1 for ; Mon, 05 Jun 2023 08:42:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979734; x=1688571734; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LQpOfl8clKnd1O4gu74PSUiT4R3rCnMiThuoNKoAYLc=; b=dGIoYaTIu/Go0aZBEJDRNP5bu0ysEvnifzxjUTmQ7mGdMzkbzkinDQqDiPgMIKsSeq Ym8QRUeTI5rCwPZwfSEOHk/wxdk8DFHr1eHQnbcksySVaY6hz03rTPeuaDXtZpvK++pX oFu5BlBhLvkuBcR16vlbpSoHbf0Fthcw1u8Q9rRKwp8vPdW14gNni4kpC2No1tkBQUv4 vvMydl8riJBK26l7+we9Nyunz+D6OxLs38UInhGoJCYtIlnBaS5gVcX8YfyCsJOkgsSy O44vtV1RrSqGaBvNoR+pZnTMYLobVs2CRbUU9WxtEVmSuD4ChyeQQA/f+K4OyIsR5c7R Kvxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979734; x=1688571734; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LQpOfl8clKnd1O4gu74PSUiT4R3rCnMiThuoNKoAYLc=; b=UMaQDmlTHFIUZI94FyO2Yds+N7iv5trB4JToh2dGEtnqxM/wjIG6ZOxoxYwW5nLZtT +q5MK29Iw2NtuSW+k6pdG1nogf3JPqieBk9rGE6VrWHU3b7LhGDBlskU+F6GErqp6kKe pWMhCAP41PoR32vHQztz0uPo6mrvJanQXXam43Z/9+OOudnznByh4XHciMNftFSOOSxp 8/giQZKCNdLDHuEXMmWGpAZQ5TW67MexI5FQjsDHQSZKKjdZdGTiKRbJM8ksG2SVg7uz AdOgWz6gEABWTlId2fWY0+e4S/C0U0iCpdaHQdmlf0f9HDpX+ActVi9NqOwUQ58k2QTR 93JQ== X-Gm-Message-State: AC+VfDyqslAwiQdN8VsuirRHCqgdfB414aVP0kf9khoJMe95rBb++ZBB Mna7a6/Hkhb6GN67Uj2de1+RRg== X-Google-Smtp-Source: ACHHUZ4HarBlrt7w5wC3w0gMuu62+7K9H3G8hOHQlJBusTnGINtatoDEV8k+cJjf2CL5U7wLG/4/dQ== X-Received: by 2002:a17:903:1108:b0:1b0:4883:2e03 with SMTP id n8-20020a170903110800b001b048832e03mr4028898plh.40.1685979733979; Mon, 05 Jun 2023 08:42:13 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:42:13 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Bagas Sanjaya , Jonathan Corbet , Paul Walmsley , Albert Ou , Heiko Stuebner , Conor Dooley , Evan Green , Vincent Chen Subject: [PATCH -next v21 25/27] riscv: Add documentation for Vector Date: Mon, 5 Jun 2023 11:07:22 +0000 Message-Id: <20230605110724.21391-26-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This patch add a brief documentation of the userspace interface in regard to the RISC-V Vector extension. Signed-off-by: Andy Chiu Reviewed-by: Greentime Hu Reviewed-by: Vincent Chen Co-developed-by: Bagas Sanjaya Signed-off-by: Bagas Sanjaya --- Changelog v21: - add usage guideline into doc (Rémi) Changelog v20: - Drop bit-field repressentation and typos (Björn) - Fix document styling (Bagas) --- Documentation/riscv/index.rst | 1 + Documentation/riscv/vector.rst | 132 +++++++++++++++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/riscv/vector.rst diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 175a91db0200..95cf9c1e1da1 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -10,6 +10,7 @@ RISC-V architecture hwprobe patch-acceptance uabi + vector features diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst new file mode 100644 index 000000000000..48f189d79e41 --- /dev/null +++ b/Documentation/riscv/vector.rst @@ -0,0 +1,132 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================= +Vector Extension Support for RISC-V Linux +========================================= + +This document briefly outlines the interface provided to userspace by Linux in +order to support the use of the RISC-V Vector Extension. + +1. prctl() Interface +--------------------- + +Two new prctl() calls are added to allow programs to manage the enablement +status for the use of Vector in userspace. The intended usage guideline for +these interfaces is to give init systems a way to modify the availability of V +for processes running under its domain. Calling thess interfaces is not +recommended in libraries routines because libraries should not override policies +configured from the parant process. Also, users must noted that these interfaces +are not portable to non-Linux, nor non-RISC-V environments, so it is discourage +to use in a portable code. To get the availability of V in an ELF program, +please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the +auxiliary vector. + +* prctl(PR_RISCV_V_SET_CONTROL, unsigned long arg) + + Sets the Vector enablement status of the calling thread, where the control + argument consists of two 2-bit enablement statuses and a bit for inheritance + mode. Other threads of the calling process are unaffected. + + Enablement status is a tri-state value each occupying 2-bit of space in + the control argument: + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default + enablement status on execve(). The system-wide default setting can be + controlled via sysctl interface (see sysctl section below). + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the + thread. + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector + instructions under such condition will trap and casuse the termination of the thread. + + arg: The control argument is a 5-bit value consisting of 3 parts, and + accessed by 3 masks respectively. + + The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK, + PR_RISCV_V_VSTATE_CTRL_NEXT_MASK, and PR_RISCV_V_VSTATE_CTRL_INHERIT + represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the + enablement status of current thread, and the setting at bit[3:2] takes place + at next execve(). bit[4] defines the inheritance mode of the setting in + bit[3:2]. + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the + Vector enablement status for the calling thread. The calling thread is + not able to turn off Vector once it has been enabled. The prctl() call + fails with EPERM if the value in this mask is PR_RISCV_V_VSTATE_CTRL_OFF + but the current enablement status is not off. Setting + PR_RISCV_V_VSTATE_CTRL_DEFAULT here takes no effect but to set back + the original enablement status. + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the + Vector enablement setting for the calling thread at the next execve() + system call. If PR_RISCV_V_VSTATE_CTRL_DEFAULT is used in this mask, + then the enablement status will be decided by the system-wide + enablement status when execve() happen. + + * :c:macro:`PR_RISCV_V_VSTATE_CTRL_INHERIT`: bit[4]: the inheritance + mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit + is set then the following execve() will not clear the setting in both + PR_RISCV_V_VSTATE_CTRL_NEXT_MASK and PR_RISCV_V_VSTATE_CTRL_INHERIT. + This setting persists across changes in the system-wide default value. + + Return value: + * 0 on success; + * EINVAL: Vector not supported, invalid enablement status for current or + next mask; + * EPERM: Turning off Vector in PR_RISCV_V_VSTATE_CTRL_CUR_MASK if Vector + was enabled for the calling thread. + + On success: + * A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place + immediately. The enablement status specified in + PR_RISCV_V_VSTATE_CTRL_NEXT_MASK happens at the next execve() call, or + all following execve() calls if PR_RISCV_V_VSTATE_CTRL_INHERIT bit is + set. + * Every successful call overwrites a previous setting for the calling + thread. + +* prctl(PR_RISCV_V_GET_CONTROL) + + Gets the same Vector enablement status for the calling thread. Setting for + next execve() call and the inheritance bit are all OR-ed together. + + Note that ELF programs are able to get the availability of V for itself by + reading :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the + auxiliary vector. + + Return value: + * a nonnegative value on success; + * EINVAL: Vector not supported. + +2. System runtime configuration (sysctl) +----------------------------------------- + +To mitigate the ABI impact of expansion of the signal stack, a +policy mechanism is provided to the administrators, distro maintainers, and +developers to control the default Vector enablement status for userspace +processes in form of sysctl knob: + +* /proc/sys/abi/riscv_v_default_allow + + Writing the text representation of 0 or 1 to this file sets the default + system enablement status for new starting userspace programs. Valid values + are: + + * 0: Do not allow Vector code to be executed as the default for new processes. + * 1: Allow Vector code to be executed as the default for new processes. + + Reading this file returns the current system default enablement status. + + At every execve() call, a new enablement status of the new process is set to + the system default, unless: + + * PR_RISCV_V_VSTATE_CTRL_INHERIT is set for the calling process, and the + setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not + PR_RISCV_V_VSTATE_CTRL_DEFAULT. Or, + + * The setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not + PR_RISCV_V_VSTATE_CTRL_DEFAULT. + + Modifying the system default enablement status does not affect the enablement + status of any existing process of thread that do not make an execve() call. From patchwork Mon Jun 5 11:07:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 710C4C7EE2C for ; Mon, 5 Jun 2023 15:43:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235077AbjFEPnY (ORCPT ); Mon, 5 Jun 2023 11:43:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234998AbjFEPnK (ORCPT ); Mon, 5 Jun 2023 11:43:10 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A35571A7 for ; Mon, 5 Jun 2023 08:42:39 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-53fdae76f3aso4524044a12.0 for ; Mon, 05 Jun 2023 08:42:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979747; x=1688571747; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=DUVXHBR1wkNxT0wOTAVxttFccgUOF7kcLoBjUYXBqWs=; b=iYzrKAyeKuEm07UL9iOX/P9TElyo9gEXsx9KFr2y/P6B0ksio7e3N/hxpR69XX1y3F iA1NqMcqNP86TnOUBqi1rYKedlBO7hZfMbJgAOtHuvpGe8pXKTmVmtX+Du/gQii3AnGS 4eHJlfd4r/8BD0zZDK9LU+IdCAsr4sDQyD4ayXLRrnx9tvHAqnZJS91D7nC2u3VqjzQ1 a5TeEMQIam86j005QHMOY0bBtcY2Blsj9iXMtfrI8b87ym9YjZ6jYsGZbeW+zDg4KN8+ luSfXeWOh4pThCfzbTyYsW47r55U1Zj9t8Nj8lvBy+yZ/ArO66MrDGVPX3nzM73A7vnK agKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979747; x=1688571747; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=DUVXHBR1wkNxT0wOTAVxttFccgUOF7kcLoBjUYXBqWs=; b=jl57TRetmBZtdDADHtmGwWMJ2hvOng8l7ALl6uRCLzoRDpteMFruP4ATFjUlaWEIhp 0DAR1RbMJGpTGbVN5Qacv1uyJuL+XbnWPIjlU03oCeTm0UYexbNp35QcNiA0s7DAXpcO My5Ira6x5AAj8sb5s3ilIseRLqMOJ+jmMbKO9nskjJp0r7ikM4hm0KHgAgTs4eoDWqDE 4DFbcMMEeIR3AlqLTsE5kDs7pOIhnwQ6ae9MtNuU5syFiP4mZD7Y9PHIvtH9cu9Z7zCo +snvq4MS9z/KK5ux2JoklTEt53EAXTSuJeNrqbUkNjZ1HoYIw0rCz67yonxy/8/ADkfX oT4A== X-Gm-Message-State: AC+VfDxsrsOZb2ZdNUpy8rcoihcRiYT41mW9JD/E58V32BWx1RJYxzKn H8PgzxIqXRUkdBDGm/+4/TvutQ== X-Google-Smtp-Source: ACHHUZ7zCGurL4a5HfUR4eL/XV4OHJ9jritWJ9+n74OmXQycqF4CMCgOy7gN52SgrzrywOwXHsjArg== X-Received: by 2002:a17:902:860c:b0:1b0:1036:608c with SMTP id f12-20020a170902860c00b001b01036608cmr7394453plo.25.1685979747022; Mon, 05 Jun 2023 08:42:27 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.42.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:42:26 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Shuah Khan , Paul Walmsley , Albert Ou , Evan Green Subject: [PATCH -next v21 26/27] selftests: Test RISC-V Vector prctl interface Date: Mon, 5 Jun 2023 11:07:23 +0000 Message-Id: <20230605110724.21391-27-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This add a test for prctl interface that controls the use of userspace Vector. Signed-off-by: Andy Chiu --- tools/testing/selftests/riscv/Makefile | 2 +- .../testing/selftests/riscv/vector/.gitignore | 2 + tools/testing/selftests/riscv/vector/Makefile | 15 ++ .../riscv/vector/vstate_exec_nolibc.c | 111 ++++++++++ .../selftests/riscv/vector/vstate_prctl.c | 189 ++++++++++++++++++ 5 files changed, 318 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/riscv/vector/.gitignore create mode 100644 tools/testing/selftests/riscv/vector/Makefile create mode 100644 tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c create mode 100644 tools/testing/selftests/riscv/vector/vstate_prctl.c diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftests/riscv/Makefile index 32a72902d045..9dd629cc86aa 100644 --- a/tools/testing/selftests/riscv/Makefile +++ b/tools/testing/selftests/riscv/Makefile @@ -5,7 +5,7 @@ ARCH ?= $(shell uname -m 2>/dev/null || echo not) ifneq (,$(filter $(ARCH),riscv)) -RISCV_SUBTARGETS ?= hwprobe +RISCV_SUBTARGETS ?= hwprobe vector else RISCV_SUBTARGETS := endif diff --git a/tools/testing/selftests/riscv/vector/.gitignore b/tools/testing/selftests/riscv/vector/.gitignore new file mode 100644 index 000000000000..4f2b4e8a3b08 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/.gitignore @@ -0,0 +1,2 @@ +vstate_exec_nolibc +vstate_prctl diff --git a/tools/testing/selftests/riscv/vector/Makefile b/tools/testing/selftests/riscv/vector/Makefile new file mode 100644 index 000000000000..cd6e80bf995d --- /dev/null +++ b/tools/testing/selftests/riscv/vector/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2021 ARM Limited +# Originally tools/testing/arm64/abi/Makefile + +TEST_GEN_PROGS := vstate_prctl +TEST_GEN_PROGS_EXTENDED := vstate_exec_nolibc + +include ../../lib.mk + +$(OUTPUT)/vstate_prctl: vstate_prctl.c ../hwprobe/sys_hwprobe.S + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ + +$(OUTPUT)/vstate_exec_nolibc: vstate_exec_nolibc.c + $(CC) -nostdlib -static -include ../../../../include/nolibc/nolibc.h \ + -Wall $(CFLAGS) $(LDFLAGS) $^ -o $@ -lgcc diff --git a/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c b/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c new file mode 100644 index 000000000000..5cbc392944a6 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/vstate_exec_nolibc.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +#define THIS_PROGRAM "./vstate_exec_nolibc" + +int main(int argc, char **argv) +{ + int rc, pid, status, test_inherit = 0; + long ctrl, ctrl_c; + char *exec_argv[2], *exec_envp[2]; + + if (argc > 1) + test_inherit = 1; + + ctrl = my_syscall1(__NR_prctl, PR_RISCV_V_GET_CONTROL); + if (ctrl < 0) { + puts("PR_RISCV_V_GET_CONTROL is not supported\n"); + return ctrl; + } + + if (test_inherit) { + pid = fork(); + if (pid == -1) { + puts("fork failed\n"); + exit(-1); + } + + /* child */ + if (!pid) { + exec_argv[0] = THIS_PROGRAM; + exec_argv[1] = NULL; + exec_envp[0] = NULL; + exec_envp[1] = NULL; + /* launch the program again to check inherit */ + rc = execve(THIS_PROGRAM, exec_argv, exec_envp); + if (rc) { + puts("child execve failed\n"); + exit(-1); + } + } + + } else { + pid = fork(); + if (pid == -1) { + puts("fork failed\n"); + exit(-1); + } + + if (!pid) { + rc = my_syscall1(__NR_prctl, PR_RISCV_V_GET_CONTROL); + if (rc != ctrl) { + puts("child's vstate_ctrl not equal to parent's\n"); + exit(-1); + } + asm volatile (".option push\n\t" + ".option arch, +v\n\t" + "vsetvli x0, x0, e32, m8, ta, ma\n\t" + ".option pop\n\t" + ); + exit(ctrl); + } + } + + rc = waitpid(-1, &status, 0); + + if (WIFEXITED(status) && WEXITSTATUS(status) == -1) { + puts("child exited abnormally\n"); + exit(-1); + } + + if (WIFSIGNALED(status)) { + if (WTERMSIG(status) != SIGILL) { + puts("child was terminated by unexpected signal\n"); + exit(-1); + } + + if ((ctrl & PR_RISCV_V_VSTATE_CTRL_CUR_MASK) != PR_RISCV_V_VSTATE_CTRL_OFF) { + puts("child signaled by illegal V access but vstate_ctrl is not off\n"); + exit(-1); + } + + /* child terminated, and its vstate_ctrl is off */ + exit(ctrl); + } + + ctrl_c = WEXITSTATUS(status); + if (test_inherit) { + if (ctrl & PR_RISCV_V_VSTATE_CTRL_INHERIT) { + if (!(ctrl_c & PR_RISCV_V_VSTATE_CTRL_INHERIT)) { + puts("parent has inherit bit, but child has not\n"); + exit(-1); + } + } + rc = (ctrl & PR_RISCV_V_VSTATE_CTRL_NEXT_MASK) >> 2; + if (rc != PR_RISCV_V_VSTATE_CTRL_DEFAULT) { + if (rc != (ctrl_c & PR_RISCV_V_VSTATE_CTRL_CUR_MASK)) { + puts("parent's next setting does not equal to child's\n"); + exit(-1); + } + + if (!(ctrl & PR_RISCV_V_VSTATE_CTRL_INHERIT)) { + if ((ctrl_c & PR_RISCV_V_VSTATE_CTRL_NEXT_MASK) != + PR_RISCV_V_VSTATE_CTRL_DEFAULT) { + puts("must clear child's next vstate_ctrl if !inherit\n"); + exit(-1); + } + } + } + } + return ctrl; +} diff --git a/tools/testing/selftests/riscv/vector/vstate_prctl.c b/tools/testing/selftests/riscv/vector/vstate_prctl.c new file mode 100644 index 000000000000..b348b475be57 --- /dev/null +++ b/tools/testing/selftests/riscv/vector/vstate_prctl.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +#include "../../kselftest.h" + +/* + * Rather than relying on having a new enough libc to define this, just do it + * ourselves. This way we don't need to be coupled to a new-enough libc to + * contain the call. + */ +long riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, + size_t cpu_count, unsigned long *cpus, unsigned int flags); + +#define NEXT_PROGRAM "./vstate_exec_nolibc" +static int launch_test(int test_inherit) +{ + char *exec_argv[3], *exec_envp[1]; + int rc, pid, status; + + pid = fork(); + if (pid < 0) { + ksft_test_result_fail("fork failed %d", pid); + return -1; + } + + if (!pid) { + exec_argv[0] = NEXT_PROGRAM; + exec_argv[1] = test_inherit != 0 ? "x" : NULL; + exec_argv[2] = NULL; + exec_envp[0] = NULL; + /* launch the program again to check inherit */ + rc = execve(NEXT_PROGRAM, exec_argv, exec_envp); + if (rc) { + perror("execve"); + ksft_test_result_fail("child execve failed %d\n", rc); + exit(-1); + } + } + + rc = waitpid(-1, &status, 0); + if (rc < 0) { + ksft_test_result_fail("waitpid failed\n"); + return -3; + } + + if ((WIFEXITED(status) && WEXITSTATUS(status) == -1) || + WIFSIGNALED(status)) { + ksft_test_result_fail("child exited abnormally\n"); + return -4; + } + + return WEXITSTATUS(status); +} + +int test_and_compare_child(long provided, long expected, int inherit) +{ + int rc; + + rc = prctl(PR_RISCV_V_SET_CONTROL, provided); + if (rc != 0) { + ksft_test_result_fail("prctl with provided arg %lx failed with code %d\n", + provided, rc); + return -1; + } + rc = launch_test(inherit); + if (rc != expected) { + ksft_test_result_fail("Test failed, check %d != %d\n", rc, + expected); + return -2; + } + return 0; +} + +#define PR_RISCV_V_VSTATE_CTRL_CUR_SHIFT 0 +#define PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT 2 + +int main(void) +{ + struct riscv_hwprobe pair; + long flag, expected; + long rc; + + pair.key = RISCV_HWPROBE_KEY_IMA_EXT_0; + rc = riscv_hwprobe(&pair, 1, 0, NULL, 0); + if (rc < 0) { + ksft_test_result_fail("hwprobe() failed with %d\n", rc); + return -1; + } + + if (pair.key != RISCV_HWPROBE_KEY_IMA_EXT_0) { + ksft_test_result_fail("hwprobe cannot probe RISCV_HWPROBE_KEY_IMA_EXT_0\n"); + return -2; + } + + if (!(pair.value & RISCV_HWPROBE_IMA_V)) { + rc = prctl(PR_RISCV_V_GET_CONTROL); + if (rc != -1 || errno != EINVAL) { + ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without V\n"); + return -3; + } + + rc = prctl(PR_RISCV_V_SET_CONTROL, PR_RISCV_V_VSTATE_CTRL_ON); + if (rc != -1 || errno != EINVAL) { + ksft_test_result_fail("GET_CONTROL should fail on kernel/hw without V\n"); + return -4; + } + + ksft_test_result_skip("Vector not supported\n"); + return 0; + } + + flag = PR_RISCV_V_VSTATE_CTRL_ON; + rc = prctl(PR_RISCV_V_SET_CONTROL, flag); + if (rc != 0) { + ksft_test_result_fail("Enabling V for current should always success\n"); + return -5; + } + + flag = PR_RISCV_V_VSTATE_CTRL_OFF; + rc = prctl(PR_RISCV_V_SET_CONTROL, flag); + if (rc != -1 || errno != EPERM) { + ksft_test_result_fail("Disabling current's V alive must fail with EPERM(%d)\n", + errno); + return -5; + } + + /* Turn on next's vector explicitly and test */ + flag = PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + if (test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_ON, 0)) + return -6; + + /* Turn off next's vector explicitly and test */ + flag = PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + if (test_and_compare_child(flag, PR_RISCV_V_VSTATE_CTRL_OFF, 0)) + return -7; + + /* Turn on next's vector explicitly and test inherit */ + flag = PR_RISCV_V_VSTATE_CTRL_ON << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + flag |= PR_RISCV_V_VSTATE_CTRL_INHERIT; + expected = flag | PR_RISCV_V_VSTATE_CTRL_ON; + if (test_and_compare_child(flag, expected, 0)) + return -8; + + if (test_and_compare_child(flag, expected, 1)) + return -9; + + /* Turn off next's vector explicitly and test inherit */ + flag = PR_RISCV_V_VSTATE_CTRL_OFF << PR_RISCV_V_VSTATE_CTRL_NEXT_SHIFT; + flag |= PR_RISCV_V_VSTATE_CTRL_INHERIT; + expected = flag | PR_RISCV_V_VSTATE_CTRL_OFF; + if (test_and_compare_child(flag, expected, 0)) + return -10; + + if (test_and_compare_child(flag, expected, 1)) + return -11; + + /* arguments should fail with EINVAL */ + rc = prctl(PR_RISCV_V_SET_CONTROL, 0xff0); + if (rc != -1 || errno != EINVAL) { + ksft_test_result_fail("Undefined control argument should return EINVAL\n"); + return -12; + } + + rc = prctl(PR_RISCV_V_SET_CONTROL, 0x3); + if (rc != -1 || errno != EINVAL) { + ksft_test_result_fail("Undefined control argument should return EINVAL\n"); + return -12; + } + + rc = prctl(PR_RISCV_V_SET_CONTROL, 0xc); + if (rc != -1 || errno != EINVAL) { + ksft_test_result_fail("Undefined control argument should return EINVAL\n"); + return -12; + } + + rc = prctl(PR_RISCV_V_SET_CONTROL, 0xc); + if (rc != -1 || errno != EINVAL) { + ksft_test_result_fail("Undefined control argument should return EINVAL\n"); + return -12; + } + + ksft_test_result_pass("tests for riscv_v_vstate_ctrl pass\n"); + ksft_exit_pass(); + return 0; +} From patchwork Mon Jun 5 11:07:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13267686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EE4BC7EE23 for ; Mon, 5 Jun 2023 15:43:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232856AbjFEPnh (ORCPT ); Mon, 5 Jun 2023 11:43:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234103AbjFEPnW (ORCPT ); Mon, 5 Jun 2023 11:43:22 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5C87E4C for ; Mon, 5 Jun 2023 08:42:58 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1b010338d82so22642675ad.0 for ; Mon, 05 Jun 2023 08:42:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1685979752; x=1688571752; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=GbKkWHcrIgmeU53Vku19x3Zfwadjf8vHA4LYRH5wmCY=; b=Fs+iSAQ26EuErgnKPEjcmBTy4eNZK9hqe+pb0SH0SZWFh8DPByC8+H1iiEbnYkIaKh eZjtX0qRh82RKh+ELSEojK5e65RuZ0CKZTsesRGER5bDwHdsZn051qdpkMQbSvgH+f59 pcAIgMJLnxHQifCdBojIgeb7wpbLT+18TMbA2qZGD7LkeChlgrW4fpJehmY/CyeeDWaF QAsCNdIhOot2rzOPWyzSZfZLr7ja6J8mMLthqvKqwQw/79XsaMm+7rtegqT4KkjBskVm iuRfRTQtIgDPQM0BQPedH2seS974wyDc5B0HR6WzXy9Le4CX2cWubTgxhtCLHC4NFibP gFYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685979752; x=1688571752; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=GbKkWHcrIgmeU53Vku19x3Zfwadjf8vHA4LYRH5wmCY=; b=kXaoRF+GUEnAgeK5jzqL/3xVfFud9kkrFHXZn/SCaVEjfRG4MDiiP1/Wld30FI3Y8W mYpsewdHDGpSIeg8J4uBrNLEqTQSAh3uEnAiNyBD0JU8J9U2JI1UWxsQUYThHa+wvrNE 5PM9+DhhE09B8hQhSjf0cDH+i1JToxo6IRWsCYTz5ckQlVn2rPnbKPW360vIaZQhsaOt EZVmDtM+CM4ZPKJWUXWMAWPq2Vc8SxhSeu7ZiGH8YWuhnqL1LuKPmIJQZvgGmPRUEwkZ hhtzxBf+gROKyM8ws4wv/UpGb7/v3AJdWLyFu4m17AST+MShVLxzlCQ7wRqrGUQpTRIs Qh1A== X-Gm-Message-State: AC+VfDzJzO7CmDxlaR9Rs7XCY4hz4daiEbfM8nD1vTYSDA/xaam7e/yo JT+dAc988otW+2zFh+aDJGyDhA== X-Google-Smtp-Source: ACHHUZ7S3X2JsL5hHF0bKLSbGHCJWcERbwDqGTA5uH+49EFqOOvFm/YH7BsXtElZU5mUItovy54HgA== X-Received: by 2002:a17:902:e886:b0:1b0:7c3c:31f9 with SMTP id w6-20020a170902e88600b001b07c3c31f9mr3863001plg.53.1685979752011; Mon, 05 Jun 2023 08:42:32 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jk19-20020a170903331300b001b0aec3ed59sm6725962plb.256.2023.06.05.08.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 08:42:31 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Shuah Khan , Paul Walmsley , Albert Ou Subject: [PATCH -next v21 27/27] selftests: add .gitignore file for RISC-V hwprobe Date: Mon, 5 Jun 2023 11:07:24 +0000 Message-Id: <20230605110724.21391-28-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230605110724.21391-1-andy.chiu@sifive.com> References: <20230605110724.21391-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The executable file "hwprobe" should be ignored by git, adding it to fix that. Signed-off-by: Andy Chiu --- tools/testing/selftests/riscv/hwprobe/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 tools/testing/selftests/riscv/hwprobe/.gitignore diff --git a/tools/testing/selftests/riscv/hwprobe/.gitignore b/tools/testing/selftests/riscv/hwprobe/.gitignore new file mode 100644 index 000000000000..8113dc3bdd03 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/.gitignore @@ -0,0 +1 @@ +hwprobe