From patchwork Mon Jun 5 17:08:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13267811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65BDDC7EE2E for ; Mon, 5 Jun 2023 17:08:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.543815.849092 (Exim 4.92) (envelope-from ) id 1q6Dgw-0001ho-26; Mon, 05 Jun 2023 17:08:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 543815.849092; Mon, 05 Jun 2023 17:08:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q6Dgv-0001hh-V6; Mon, 05 Jun 2023 17:08:25 +0000 Received: by outflank-mailman (input) for mailman id 543815; Mon, 05 Jun 2023 17:08:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q6Dgu-0001hL-2i for xen-devel@lists.xenproject.org; Mon, 05 Jun 2023 17:08:24 +0000 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [2a00:1450:4864:20::32b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 939009e2-03c3-11ee-b232-6b7b168915f2; Mon, 05 Jun 2023 19:08:22 +0200 (CEST) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f6d38a140bso36894145e9.1 for ; Mon, 05 Jun 2023 10:08:22 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id b3-20020a5d4d83000000b0030c4d8930b1sm10247405wru.91.2023.06.05.10.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 10:08:21 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 939009e2-03c3-11ee-b232-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1685984902; x=1688576902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UaRbw/sqJoSJWbfETm9zRVkdTLn2hj3BA9S5N+S7y90=; b=i+Vl4p4zvEH/nYqsQIp8xv5oLP6H29zp+zFEwqb9LWf3wM5TI7Fq25pCPB5jOzFixf /SUgNBf9Wdfm20KzwhaL/rvehq6RDofIBR7GA0DZ0I4e1bxBYCzzuKFbbp/8bv/QtQG7 dWLbqC4n7NC+sqMfz1fVFvJmh7dT7ggkQYlJU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685984902; x=1688576902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UaRbw/sqJoSJWbfETm9zRVkdTLn2hj3BA9S5N+S7y90=; b=Pd8kgCJaBzmAe5aI3VlLWkPOt+KT0TCgkzou8SBdsLFbco7pZC1Uvs32nFd69ul8ei NSMvlxQgoKUUbryVQ0MqNRKejKHapbAi4dUE/7cVM7WCCZ4Icp0uFxsvL6wMG/JJYXAB wRJLUnrPW2WjWcocVP6XHRw4UZhX4ZNKwlW8bq+TIeQCDW4r6tZ40FANmS/RsEutLd6l tX7qUD97bgxHyRPt7LYE+JHE1WIhwrYIq3HqciokJCEnQkN80A6LD6IRsrFV5x9wEMnr wJ/jw/iNV/lNSNNL8weTn4lBcyzxrJkaRy5hSsBVbT28E7rsEIrxbuUdHgVjf4Q4OMmB qeYw== X-Gm-Message-State: AC+VfDzrGqtiYP1qhMHVs8JK6p/qoy1I5/lgTokXQ6kwDnKANyNWMDcH oZcb1EAGM163IVhybY66A9jQDL5KhE3Op14C7PE= X-Google-Smtp-Source: ACHHUZ7lLvcV1tRW3PDGf4rz/a2dJpVlzf+rnHz2smfdTCd5C2zUSEENAFx0V0GDy4VePu79+/jLTA== X-Received: by 2002:a7b:cd89:0:b0:3f7:3634:e21b with SMTP id y9-20020a7bcd89000000b003f73634e21bmr4580813wmj.2.1685984901953; Mon, 05 Jun 2023 10:08:21 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 1/4] x86/microcode: Remove Intel's family check on early_microcode_init() Date: Mon, 5 Jun 2023 18:08:14 +0100 Message-Id: <20230605170817.9913-2-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605170817.9913-1-alejandro.vallejo@cloud.com> References: <20230605170817.9913-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Intel only suuports 64bits on families 6 and 15, so we can always assume microcode loading facilities are present and skip the check. Signed-off-by: Alejandro Vallejo --- v2: * New addition --- xen/arch/x86/cpu/microcode/core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index c1033f3bc2..29ff38f35c 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -854,8 +854,14 @@ int __init early_microcode_init(unsigned long *module_map, break; case X86_VENDOR_INTEL: - if ( c->x86 >= 6 ) - ucode_ops = intel_ucode_ops; + /* + * Intel introduced microcode loading with family 6. Because we + * don't support compiling Xen for 32bit machines we're guaranteed + * that at this point we're either in family 15 (Pentium 4) or 6 + * (everything since then), so microcode facilities are always + * present. + */ + ucode_ops = intel_ucode_ops; break; } From patchwork Mon Jun 5 17:08:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13267810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D69E1C7EE23 for ; Mon, 5 Jun 2023 17:08:43 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.543816.849097 (Exim 4.92) (envelope-from ) id 1q6Dgw-0001kV-AN; Mon, 05 Jun 2023 17:08:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 543816.849097; Mon, 05 Jun 2023 17:08:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q6Dgw-0001jY-5T; Mon, 05 Jun 2023 17:08:26 +0000 Received: by outflank-mailman (input) for mailman id 543816; Mon, 05 Jun 2023 17:08:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q6Dgu-0001hL-OX for xen-devel@lists.xenproject.org; Mon, 05 Jun 2023 17:08:24 +0000 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [2a00:1450:4864:20::42d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 93f918b1-03c3-11ee-b232-6b7b168915f2; Mon, 05 Jun 2023 19:08:23 +0200 (CEST) Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-30ad99fa586so5082388f8f.2 for ; Mon, 05 Jun 2023 10:08:23 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id b3-20020a5d4d83000000b0030c4d8930b1sm10247405wru.91.2023.06.05.10.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 10:08:22 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 93f918b1-03c3-11ee-b232-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1685984902; x=1688576902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B7fxp0WbBbMKypEvumAuysCY0BLPaaSmYzs2KisIH00=; b=bX0ieJYw9ilCPO+NbFfqK7wmgNzrSz8WqwisW2uzz/F58LwomsoRUNxVU/i/WGqfaQ lZDdLqJq6dZF10AgGibJjPShDGdlH5pAKtuVCSzQwzB0WMfobdEzZrNvvqejBeWbzWVN aQjOl1ZJpdzNSM+ARk8icJpA5JN6s04TimjUU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685984902; x=1688576902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B7fxp0WbBbMKypEvumAuysCY0BLPaaSmYzs2KisIH00=; b=HmV6YC1GXWatxpowOlgwWod4++AiJXc58twQGaN3lq37VYV9tHbgcltSODtAPea9Ym 8wvzPfhFhNmuw05JFrjZ5t2aQmyns1/5FWX4UTxST8PGfpV5cT7LRnBFEBBWCQ5npJ1u aIQUNMsN1wAjbBVcp7+qiDtaM57ztw4tzeEPJiXuoEsAdwwS/sECG63coJkeN144TzQf v4I1Z7EHlzXkdt63LRARYGaZOiQSm91UwwuW/fmWtW+XSppS8DfSPN/PwYG7iYHm1H+X pydjfkz7mMEivqk7SpK8/KbCKa3BWdHINOGxubKGbDMKjkMhm3ZFNaS61L09zngzt/xO SpvA== X-Gm-Message-State: AC+VfDwrB05YE1ubZAHJAAPBzkcfsJ5l9bn2WSW4CbRfQbp6WmYh1QlG LxVk2NozCg/on8TNVmsN0dOiSHihA1ru29/36Wo= X-Google-Smtp-Source: ACHHUZ6yjFhHjZcRl5U8qb7QH1Jqd7Os8ifx204lVxQq/+5cXpNuDf1O+km9wHvsj/hChpQ2U9HCYw== X-Received: by 2002:a05:6000:44:b0:306:4162:ebbe with SMTP id k4-20020a056000004400b003064162ebbemr6411420wrx.49.1685984902557; Mon, 05 Jun 2023 10:08:22 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 2/4] x86: Read MSR_ARCH_CAPS after early_microcode_init() Date: Mon, 5 Jun 2023 18:08:15 +0100 Message-Id: <20230605170817.9913-3-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605170817.9913-1-alejandro.vallejo@cloud.com> References: <20230605170817.9913-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 tsx_init() has some ad-hoc code to read MSR_ARCH_CAPS if present. In order to suuport DIS_MCU_UPDATE we need access to it earlier, so this patch moves early read to the tail of early_microcode_init(), after the early microcode update. The read of the 7d0 CPUID leaf is left in a helper because it's reused in a later patch. No functional change. Signed-off-by: Alejandro Vallejo --- I suspect there was an oversight in tsx_init() by which boot_cpu_data.cpuid_level was never read? The first read I can see is in identify_cpu(), which happens after tsx_init(). v2: * New addition --- xen/arch/x86/cpu/microcode/core.c | 21 +++++++++++++++++++++ xen/arch/x86/tsx.c | 15 +++------------ 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 29ff38f35c..892bcec901 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -840,6 +840,15 @@ static int __init early_microcode_update_cpu(void) return microcode_update_cpu(patch); } +static void __init early_read_cpuid_7d0(void) +{ + boot_cpu_data.cpuid_level = cpuid_eax(0); + + if ( boot_cpu_data.cpuid_level >= 7 ) + boot_cpu_data.x86_capability[FEATURESET_7d0] + = cpuid_count_edx(7, 0); +} + int __init early_microcode_init(unsigned long *module_map, const struct multiboot_info *mbi) { @@ -878,5 +887,17 @@ int __init early_microcode_init(unsigned long *module_map, if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); + early_read_cpuid_7d0(); + + /* + * tsx_init() needs MSR_ARCH_CAPS, but it runs before identify_cpu() + * populates boot_cpu_data, so we read it here to centralize early + * CPUID/MSR reads in the same place. + */ + if ( cpu_has_arch_caps ) + rdmsr(MSR_ARCH_CAPABILITIES, + boot_cpu_data.x86_capability[FEATURESET_m10Al], + boot_cpu_data.x86_capability[FEATURESET_m10Ah]); + return rc; } diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 80c6f4cedd..0501e181bf 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -39,9 +39,9 @@ void tsx_init(void) static bool __read_mostly once; /* - * This function is first called between microcode being loaded, and CPUID - * being scanned generally. Read into boot_cpu_data.x86_capability[] for - * the cpu_has_* bits we care about using here. + * While MSRs/CPUID haven't yet been scanned, MSR_ARCH_CAPABILITIES + * and leaf 7d0 have already been read if present after early microcode + * loading time. So we can assume _those_ are present. */ if ( unlikely(!once) ) { @@ -49,15 +49,6 @@ void tsx_init(void) once = true; - if ( boot_cpu_data.cpuid_level >= 7 ) - boot_cpu_data.x86_capability[FEATURESET_7d0] - = cpuid_count_edx(7, 0); - - if ( cpu_has_arch_caps ) - rdmsr(MSR_ARCH_CAPABILITIES, - boot_cpu_data.x86_capability[FEATURESET_m10Al], - boot_cpu_data.x86_capability[FEATURESET_m10Ah]); - has_rtm_always_abort = cpu_has_rtm_always_abort; if ( cpu_has_tsx_ctrl && cpu_has_srbds_ctrl ) From patchwork Mon Jun 5 17:08:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13267809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBC6EC7EE2D for ; Mon, 5 Jun 2023 17:08:43 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.543818.849108 (Exim 4.92) (envelope-from ) id 1q6Dgw-0001yS-U0; Mon, 05 Jun 2023 17:08:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 543818.849108; Mon, 05 Jun 2023 17:08:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q6Dgw-0001vQ-Ob; Mon, 05 Jun 2023 17:08:26 +0000 Received: by outflank-mailman (input) for mailman id 543818; Mon, 05 Jun 2023 17:08:25 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q6Dgv-0001hK-Jj for xen-devel@lists.xenproject.org; Mon, 05 Jun 2023 17:08:25 +0000 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [2a00:1450:4864:20::331]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 945e8a35-03c3-11ee-8611-37d641c3527e; Mon, 05 Jun 2023 19:08:23 +0200 (CEST) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f70fc4682aso44516565e9.1 for ; Mon, 05 Jun 2023 10:08:23 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id b3-20020a5d4d83000000b0030c4d8930b1sm10247405wru.91.2023.06.05.10.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 10:08:22 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 945e8a35-03c3-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1685984903; x=1688576903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AQ0i8Te1opYVMDeoQr+YKauj4QQYILajO6V4WWhluDI=; b=AijknLkAw44KoXyWtWTqPOsvWTUeCgC7yDC7DbCsgHQz9BlJiEr2hVaVzvBy+qe9lT ek7JourSTY0vpLo85i752gOXghl8nqswKcR/qGpevLS0eZQTBa/74cnskV6I7fedT9AV cQE4lWvvgxUeUiccmC+gwbp9pU6KZmj+sWCW8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685984903; x=1688576903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AQ0i8Te1opYVMDeoQr+YKauj4QQYILajO6V4WWhluDI=; b=Y0rtgHgRvtjQHOH67jETDM75LZzirLygIWmhNNzc6qqSSreOP1H8/vfRhL8EKtk2e2 vNZP7V2Uf6jRAUxgp9JEu0vfBCN/7rbDvIyUdj3vxvlLshSpwYKuRACEn7w3W72v4a/v 4CzJp3k4PEJFucUy2AVtpyTm82AMVcE4r7TVS3Nx0bRSfgZmZncyGmuSL3M2vsMh05l8 NHARJTi2Xn1dKvnj+qmAPZ0YcqHJi0/lZv4PCwuOAgFAGRtHA8O9tRl3/Vr9fhqwy6TO Y9qCelwJ5KACCv0H0F8XOa5j1umkGJI1OAICMZUTTEmrtLa93fkvinfN4TVTRQ3YLFPh guUg== X-Gm-Message-State: AC+VfDwk1z1sA/PFKNaUUtZ+ucghM5QhFubY5r3gtjIxeFOwOELszTcJ ujC1P0DZ4fYFs5kkCCTRonDwl8engt+jXzLhPQ0= X-Google-Smtp-Source: ACHHUZ7u1sk2+R+asIIG0fkfef+a11cKVB0k6wJX3/SpkDo/ZSUS+7nRmWIapgoPCzcCH2bOcbZjgA== X-Received: by 2002:a05:600c:282:b0:3f7:3526:d96f with SMTP id 2-20020a05600c028200b003f73526d96fmr4020879wmk.27.1685984903394; Mon, 05 Jun 2023 10:08:23 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 3/4] x86/microcode: Ignore microcode loading interface for revision = -1 Date: Mon, 5 Jun 2023 18:08:16 +0100 Message-Id: <20230605170817.9913-4-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605170817.9913-1-alejandro.vallejo@cloud.com> References: <20230605170817.9913-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Some hypervisors report ~0 as the microcode revision to mean "don't issue microcode updates". Ignore the microcode loading interface in that case. Signed-off-by: Alejandro Vallejo --- v2: * New addition --- xen/arch/x86/cpu/microcode/core.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 892bcec901..4f60d96d98 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -874,6 +874,21 @@ int __init early_microcode_init(unsigned long *module_map, break; } + if ( ucode_ops.collect_cpu_info ) + ucode_ops.collect_cpu_info(); + + /* + * This is a special case for virtualized Xen. Some hypervisors + * deliberately report a microcode revision of -1 to mean that they + * will not accept microcode updates. We take the hint and ignore the + * microcode interface in that case. + */ + if ( this_cpu(cpu_sig).rev == ~0 ) + { + this_cpu(cpu_sig) = (struct cpu_signature){ 0 }; + ucode_ops = (struct microcode_ops){ 0 }; + } + if ( !ucode_ops.apply_microcode ) { printk(XENLOG_WARNING "Microcode loading not available\n"); @@ -882,8 +897,6 @@ int __init early_microcode_init(unsigned long *module_map, microcode_grab_module(module_map, mbi); - ucode_ops.collect_cpu_info(); - if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); From patchwork Mon Jun 5 17:08:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13267813 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6B34C7EE2D for ; Mon, 5 Jun 2023 17:08:47 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.543819.849132 (Exim 4.92) (envelope-from ) id 1q6Dgy-0002dA-6w; Mon, 05 Jun 2023 17:08:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 543819.849132; Mon, 05 Jun 2023 17:08:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q6Dgy-0002bX-2x; Mon, 05 Jun 2023 17:08:28 +0000 Received: by outflank-mailman (input) for mailman id 543819; Mon, 05 Jun 2023 17:08:26 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q6Dgw-0001hK-9t for xen-devel@lists.xenproject.org; Mon, 05 Jun 2023 17:08:26 +0000 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [2a00:1450:4864:20::332]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 94d0ae44-03c3-11ee-8611-37d641c3527e; Mon, 05 Jun 2023 19:08:24 +0200 (CEST) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f6da07feb2so50761045e9.0 for ; Mon, 05 Jun 2023 10:08:24 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id b3-20020a5d4d83000000b0030c4d8930b1sm10247405wru.91.2023.06.05.10.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 10:08:23 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 94d0ae44-03c3-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1685984904; x=1688576904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OOsivV2azY4WdSK6TBmAXPP6Pm2+kuO/HkiPvSCcP+E=; b=CGuBFukDMR/XfNLUieqkaIXmDgSty6jly7wVcQ/I1mVAB0/6WyIl4uOjIt/3ql1tD+ 9Hga37ejgciqASd73lxw0g+pYuvt04QY8mE1Ebv+IiyNvm7WA3z8kuz3jbsb4rTQauLm oa2aJS19yzZd3c4Lyv8I4yUOTF3+hyJrwhS9E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685984904; x=1688576904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OOsivV2azY4WdSK6TBmAXPP6Pm2+kuO/HkiPvSCcP+E=; b=hCqegiZh5tYoA+jUHoqfS++btC83rnC3uxX+1b61kVzBPiggP7tuOiCz+wE0+vTJT7 S4qDh++wiHJDIyjhcBXajCPXzLiBUjiQQD8i65yxwtUXAx5M0j11jRDt78omNGnFL6y8 +A0PSMWOfrR3HLgRruepup84qHaNfz2eC0UBOV+zmlF+0zvYXB5tnnOuqeHxrbpxZVL4 +JRjE5rqOD8LQYS284+enJsEdAtrmiQ54mNa9gNPeTtKuq+mJKTiSKzWPBtsFKh/Tlse gTPoR6bz9NCXwGfOMrcVSW6B7eJU/MqNz9nR5HY26Z9IqKPEraLkOWAj0QzM8PL3A4gg n+AQ== X-Gm-Message-State: AC+VfDyvADDCcImpU7SCYMkPL5R3JodWtevgbjdPFrTXveA6SLtZMfKd VBZJk57BB+OeT2kTkoNvKaeYkJCTbrySH4N0Wpk= X-Google-Smtp-Source: ACHHUZ79VHMcIqX7iJPOAGTiRmV38ChV2yl5EgFdR962kzuSVB4cmdJaiSi1W5ytU1STeUQ/NtrG5Q== X-Received: by 2002:a7b:c7d2:0:b0:3f4:2255:8608 with SMTP id z18-20020a7bc7d2000000b003f422558608mr9181759wmk.31.1685984904107; Mon, 05 Jun 2023 10:08:24 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 4/4] x86/microcode: Prevent attempting updates if DIS_MCU_LOAD is set Date: Mon, 5 Jun 2023 18:08:17 +0100 Message-Id: <20230605170817.9913-5-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605170817.9913-1-alejandro.vallejo@cloud.com> References: <20230605170817.9913-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 If IA32_MSR_MCU_CONTROL exists then it's possible a CPU may be unable to perform microcode updates. This is controlled through the DIS_MCU_LOAD bit and is intended for baremetal clouds where the owner may not trust the tenant to choose the microcode version in use. This patch makes sure we only expose the microcode loading interface when it can be actually used, while also allowing reads of current microcode versions. Patch summary: * Read CPUID leaf 7d0 early so DIS_MCU_LOAD can be checked. * Hide microcode loading handlers if DIS_MCU_LOAD is set except for collect_cpu_info() * Update microcode_update_one() so APs can read their microcode version even if DIS_MCU_LOAD is set. Signed-off-by: Alejandro Vallejo --- v2: * Moved check from apply time to init time. --- xen/arch/x86/cpu/microcode/core.c | 31 +++++++++++++++++++++++++-- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 5 +++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 4f60d96d98..a4c123118b 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -749,11 +749,12 @@ __initcall(microcode_init); /* Load a cached update to current cpu */ int microcode_update_one(void) { + if ( ucode_ops.collect_cpu_info ) + alternative_vcall(ucode_ops.collect_cpu_info); + if ( !ucode_ops.apply_microcode ) return -EOPNOTSUPP; - alternative_vcall(ucode_ops.collect_cpu_info); - return microcode_update_cpu(NULL); } @@ -849,12 +850,25 @@ static void __init early_read_cpuid_7d0(void) = cpuid_count_edx(7, 0); } +static bool __init this_cpu_can_install_update(void) +{ + uint64_t mcu_ctrl; + + if ( !cpu_has_mcu_ctrl ) + return true; + + rdmsrl(MSR_MCU_CONTROL, mcu_ctrl); + return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD); +} + int __init early_microcode_init(unsigned long *module_map, const struct multiboot_info *mbi) { const struct cpuinfo_x86 *c = &boot_cpu_data; int rc = 0; + early_read_cpuid_7d0(); + switch ( c->x86_vendor ) { case X86_VENDOR_AMD: @@ -871,6 +885,15 @@ int __init early_microcode_init(unsigned long *module_map, * present. */ ucode_ops = intel_ucode_ops; + + /* + * In the case where microcode updates are blocked by the + * DIS_MCU_LOAD bit we can still read the microcode version even if + * we can't change it. + */ + if ( !this_cpu_can_install_update() ) + ucode_ops = (struct microcode_ops){ .collect_cpu_info = + intel_ucode_ops.collect_cpu_info }; break; } @@ -900,6 +923,10 @@ int __init early_microcode_init(unsigned long *module_map, if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); + /* + * We just updated microcode so we must reload the boot_cpu_data bits + * we read before because they might be stale after the updata. + */ early_read_cpuid_7d0(); /* diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index ace31e3b1f..0118171d7e 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -192,6 +192,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_NO) #define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) #define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO) +#define cpu_has_mcu_ctrl boot_cpu_has(X86_FEATURE_MCU_CTRL) #define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR) /* Synthesized. */ diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 2749e433d2..5c1350b5f9 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -165,6 +165,11 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) +#define MSR_MCU_CONTROL 0x00001406 +#define MCU_CONTROL_LOCK (_AC(1, ULL) << 0) +#define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1) +#define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2) + #define MSR_UARCH_MISC_CTRL 0x00001b01 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)