From patchwork Tue Jun 6 10:56:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Huo X-Patchwork-Id: 13268953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83676C7EE2F for ; Tue, 6 Jun 2023 10:57:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=T1oNWtmwYkg4wAGcBjOZm3cNdKtJJDm44Enc4SYrO40=; b=1HYT6ZVMufqBYB LtC6KEFMEzNQohYks1fEpVaB28vrlzkZ0XNJss18/JrIGqSqJgBswPDBkumIOqqs1zob3HfW4qKCi Je0CMDF6dQNKgOMp6FNMolJzXVNAiuXpKW6yGxJ74sfbb73M7lU2eTHIg7mvBF/PW1p3AVZquXFEL ldW+Ld3tPu1EAcMR/Yr2B0ilHUWzf4VgzgMSmVJiPt3OVTsbYS4wVyz8Ot2Wf0KHq8Wm5mSYvBNep /J/03Ff6mp4BZgea7nCmbU1L+hJajZRr8Mz4Ay8RpQbwqsaGEGUhaykztEuAGJKtEDlxsZIOsYVMc x50wUKb0DdbHL0c61Inw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6UNj-001Mo7-2V; Tue, 06 Jun 2023 10:57:43 +0000 Received: from ex01.ufhost.com ([61.152.239.75]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6UNg-001Mec-2E for linux-riscv@lists.infradead.org; Tue, 06 Jun 2023 10:57:42 +0000 Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 9FE9C24E28D; Tue, 6 Jun 2023 18:56:58 +0800 (CST) Received: from EXMBX067.cuchost.com (172.16.6.67) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 6 Jun 2023 18:56:58 +0800 Received: from localhost.localdomain (183.27.98.75) by EXMBX067.cuchost.com (172.16.6.67) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 6 Jun 2023 18:56:57 +0800 From: Mason Huo To: "Rafael J. Wysocki" , Viresh Kumar , Emil Renner Berthing , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou CC: Shengyu Qu , , , , , Mason Huo Subject: [PATCH v4 1/3] riscv: dts: starfive: Enable axp15060 pmic for cpufreq Date: Tue, 6 Jun 2023 18:56:54 +0800 Message-ID: <20230606105656.124355-2-mason.huo@starfivetech.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230606105656.124355-1-mason.huo@starfivetech.com> References: <20230606105656.124355-1-mason.huo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.75] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX067.cuchost.com (172.16.6.67) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230606_035740_874733_91C9938E X-CRM114-Status: UNSURE ( 9.40 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The VisionFive 2 board has an embedded pmic axp15060, which supports the cpu DVFS through the dcdc2 regulator. This patch enables axp15060 pmic and configs the dcdc2. Signed-off-by: Mason Huo --- .../starfive/jh7110-starfive-visionfive-2.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 2a6d81609284..9714da5550d7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -114,6 +114,23 @@ &i2c5 { pinctrl-names = "default"; pinctrl-0 = <&i2c5_pins>; status = "okay"; + + axp15060: pmic@36 { + compatible = "x-powers,axp15060"; + reg = <0x36>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + + regulators { + vdd_cpu: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1540000>; + regulator-name = "vdd-cpu"; + }; + }; + }; }; &i2c6 { From patchwork Tue Jun 6 10:56:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Huo X-Patchwork-Id: 13268952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C826EC77B7A for ; Tue, 6 Jun 2023 10:57:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EKyIY2QKqstNfvBYLyCQ0dAsxyNIkJb10fAhBc7YNZA=; b=ZCiQE+EPN3rpvu LnmEdpyo9wOPkfSY6PYJU9wdFUlbpxMFwSQDsaxAjCtPy9exys6N+icSvqXq8DN4NF3Sybd2Bi9GQ xvOVknERFWWElhKK/ngROjAcCUfZu8VQwva5WtVhg+6fSIQU0kkUuVpOeb22gzT3v8xuz60qpxVSa ewPVDdzolSSQn3gX2Lj6Ng8wSGnQQNVKnI02lyz74CBqBhm5LEP+1ukWXRRGpYDsHjIVxdMDOCRu3 xOHlaspefF59gOkhoB3i9OtVGcdsutVT7IiLGk+GW/lvOaeBsr0lBUNgHRCqgmX5GCmj4/aItjH0l u7TrWwfbDrZ2fXnAf/2A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6UNh-001MnC-0U; Tue, 06 Jun 2023 10:57:41 +0000 Received: from ex01.ufhost.com ([61.152.239.75]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6UNd-001Meb-2J for linux-riscv@lists.infradead.org; Tue, 06 Jun 2023 10:57:39 +0000 Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 77B8C24E28F; Tue, 6 Jun 2023 18:56:59 +0800 (CST) Received: from EXMBX067.cuchost.com (172.16.6.67) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 6 Jun 2023 18:56:59 +0800 Received: from localhost.localdomain (183.27.98.75) by EXMBX067.cuchost.com (172.16.6.67) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 6 Jun 2023 18:56:58 +0800 From: Mason Huo To: "Rafael J. Wysocki" , Viresh Kumar , Emil Renner Berthing , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou CC: Shengyu Qu , , , , , Mason Huo Subject: [PATCH v4 2/3] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist Date: Tue, 6 Jun 2023 18:56:55 +0800 Message-ID: <20230606105656.124355-3-mason.huo@starfivetech.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230606105656.124355-1-mason.huo@starfivetech.com> References: <20230606105656.124355-1-mason.huo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.75] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX067.cuchost.com (172.16.6.67) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230606_035737_898718_D5106BAC X-CRM114-Status: GOOD ( 10.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the compatible strings for supporting the generic cpufreq driver on the StarFive JH7110 SoC. Signed-off-by: Mason Huo --- drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 338cf6cc6596..14aa8281c7f4 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -85,6 +85,8 @@ static const struct of_device_id allowlist[] __initconst = { { .compatible = "st-ericsson,u9500", }, { .compatible = "st-ericsson,u9540", }, + { .compatible = "starfive,jh7110", }, + { .compatible = "ti,omap2", }, { .compatible = "ti,omap4", }, { .compatible = "ti,omap5", }, From patchwork Tue Jun 6 10:56:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Huo X-Patchwork-Id: 13268954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12527C7EE24 for ; Tue, 6 Jun 2023 10:57:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZrGmTA2ivCj1QK3/xmQV2wWxX/7/CKHsYKyuT4/3/RA=; b=OJNMFYW3C2B+KS m1Gpu6gwlA6XWSj506slkwfefEnN4SkcHSy5LhDcvpYSrbBkpehQ000MbcWraCTLLOpZQ2cefvv0R F/nDenLz9in9RPxcmuzrnD7A4xB9j/D3A6VxghUR/7XF++U72IiOfeZv3YZVrxw93lh4YQyn27olw g41qp/7ew5pLg8xZ1ea0wVLvy8XH7DTZeospgyzOuObDaXLQcrZS+zAZ4aMC9IqZOCeyayMsomQVG 7kYlh7c9KPRpX5FCl8eP11eMBBZA/AS51dA1X5ZaS5rjvfqqBXHzME3+znVcisuRjJkOXnTYmUsIF h9R8Qr+PS3fkH4r683sg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6UNp-001Mt9-1l; Tue, 06 Jun 2023 10:57:49 +0000 Received: from fd01.gateway.ufhost.com ([61.152.239.71]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6UNn-001Mf9-06 for linux-riscv@lists.infradead.org; Tue, 06 Jun 2023 10:57:48 +0000 Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 41B3781DC; Tue, 6 Jun 2023 18:57:00 +0800 (CST) Received: from EXMBX067.cuchost.com (172.16.6.67) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 6 Jun 2023 18:57:00 +0800 Received: from localhost.localdomain (183.27.98.75) by EXMBX067.cuchost.com (172.16.6.67) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 6 Jun 2023 18:56:59 +0800 From: Mason Huo To: "Rafael J. Wysocki" , Viresh Kumar , Emil Renner Berthing , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou CC: Shengyu Qu , , , , , Mason Huo Subject: [PATCH v4 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC Date: Tue, 6 Jun 2023 18:56:56 +0800 Message-ID: <20230606105656.124355-4-mason.huo@starfivetech.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230606105656.124355-1-mason.huo@starfivetech.com> References: <20230606105656.124355-1-mason.huo@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.75] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX067.cuchost.com (172.16.6.67) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230606_035747_651004_3AD3CF17 X-CRM114-Status: UNSURE ( 9.07 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. It supports up to 4 cpu frequency loads. Signed-off-by: Mason Huo --- .../jh7110-starfive-visionfive-2.dtsi | 16 +++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 9714da5550d7..fa0061eb33a7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -230,3 +230,19 @@ &uart0 { pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&U74_1 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_2 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_3 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_4 { + cpu-supply = <&vdd_cpu>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..7eef88d2cedb 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -53,6 +53,9 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -79,6 +82,9 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,6 +111,9 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -131,6 +140,9 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -164,6 +176,27 @@ core4 { }; }; + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin";