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Tue, 6 Jun 2023 23:53:12 -0700 Received: from xhdnavam40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Wed, 7 Jun 2023 01:53:08 -0500 From: Piyush Mehta To: , , , , , , CC: , , , , , Piyush Mehta Subject: [PATCH 1/2] dt-bindings: reset: convert the xlnx,zynqmp-reset.txt to yaml Date: Wed, 7 Jun 2023 12:21:20 +0530 Message-ID: <20230607065121.2265076-2-piyush.mehta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607065121.2265076-1-piyush.mehta@amd.com> References: <20230607065121.2265076-1-piyush.mehta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT043:EE_|PH0PR12MB8008:EE_ X-MS-Office365-Filtering-Correlation-Id: be23147f-86c8-4ebd-d53e-08db6723de83 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mSA4lO83EChucL7gMwjH9vu2KbRfKoOVMW0eqKhTGTpRwD+bZmwY+zRb60XPvgvJqFTWN3Pq6ogpp+kACk9XW56lzAs07YY5N4PY0dknesjzfbUEN44OzQ7ktFwKXCBH9wIzdUOW2lkyEaUBTf4avYxHhwETXuCZiWagPfnkevHj3+hknJdKKJHI771H5LMTTFC/0ZOtCYVR9RvYG9A7ougcyRBBnbsVtDidG/DKf5yzxicKC+NPmpIAmT8H+CObSp7t7xw2ihJCiM5e/8I5vIDIPD4BzpAWJ9f0o57w51MTdB1HDGcQLlZBanHee3X+0Xeta781yvZ/MsRA05npOEyRsldr9ZKhWCFsCNk1tUvU4tTLCaePkg+8GdNhgiOQ6pwXvq9l15wyU0YesDpVdvuGwfyZOWsHmSeevlsO5YOrZ3ynXw4iTD1nWAPjm9vwxmrnMSw8uOVmPGnEHD2wue1iKmPhhKNpdyKCJm/87K9ZdMNNagxnps+W9ViW/f+rISCiXjuv/8Y852hk7rnrgVPn1IBP9qXwj24frWHpbUBHuI05jibHumIq3PkfGeE2P/Z30FUaRi6wn61/F2A5YL6mYCJEeURgaCbGTdu7C2YAgDRx578VTwbH3fW5I4wf0zHbzW1v0E+mQIkQWX0R4xa9VQpE4xjWcBqHBVY6jKY2nYjN9kGlthvtvpiMq66RnFd4FMy+VGp4XO/QUSc2pTeCMsQ3FQ5foZr2fSAiI65ywUWKEFWeYq1KchkDf89+Jgu/N9enZhe28aMLH+b2nmXZYcihPEbltqlQry/UmtTiHgv/59p7BVZTxlUlZWAA X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(346002)(39860400002)(396003)(136003)(451199021)(36840700001)(40470700004)(46966006)(186003)(478600001)(1076003)(26005)(83380400001)(336012)(426003)(36860700001)(6666004)(2616005)(47076005)(966005)(40460700003)(40480700001)(316002)(8676002)(86362001)(82310400005)(41300700001)(8936002)(70586007)(81166007)(36756003)(356005)(82740400003)(4326008)(44832011)(5660300002)(2906002)(54906003)(110136005)(70206006)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2023 06:53:15.6349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be23147f-86c8-4ebd-d53e-08db6723de83 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8008 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Convert the binding to DT schema format. It also updates the reset-controller description. Signed-off-by: Piyush Mehta --- Note: The 1/2 patch introduced a warning related to the dt binding check, which was subsequently fixed in the 2/2 patch. This warning is a conversion warning due to a dependency on firmware dt binding. Warning: DTC_CHK Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.example.dtb /scratch/piyushm/torvalds/linux/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.example.dtb: zynqmp-firmware: 'reset-controller' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: /scratch/piyushm/torvalds/linux/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml Please suggest to me, if it's fine to make a single patch instead of the separate patch 1/2 and 2/2. --- .../bindings/reset/xlnx,zynqmp-reset.txt | 55 --------------- .../bindings/reset/xlnx,zynqmp-reset.yaml | 67 +++++++++++++++++++ 2 files changed, 67 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt deleted file mode 100644 index ed836868dbf1..000000000000 --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt +++ /dev/null @@ -1,55 +0,0 @@ --------------------------------------------------------------------------- - = Zynq UltraScale+ MPSoC and Versal reset driver binding = --------------------------------------------------------------------------- -The Zynq UltraScale+ MPSoC and Versal has several different resets. - -See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information -about zynqmp resets. - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required Properties: -- compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform - "xlnx,versal-reset" for Versal platform -- #reset-cells: Specifies the number of cells needed to encode reset - line, should be 1 - -------- -Example -------- - -firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - - zynqmp_reset: reset-controller { - compatible = "xlnx,zynqmp-reset"; - #reset-cells = <1>; - }; - }; -}; - -Specifying reset lines connected to IP modules -============================================== - -Device nodes that need access to reset lines should -specify them as a reset phandle in their corresponding node as -specified in reset.txt. - -For list of all valid reset indices for Zynq UltraScale+ MPSoC see - -For list of all valid reset indices for Versal see - - -Example: - -serdes: zynqmp_phy@fd400000 { - ... - - resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - reset-names = "sata_rst"; - - ... -}; diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml new file mode 100644 index 000000000000..df207ca22990 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zynq UltraScale+ MPSoC and Versal reset binding + +maintainers: + - Piyush Mehta + +description: | + The Zynq UltraScale+ MPSoC and Versal has several different resets. + + The PS reset subsystem is responsible for handling the external reset + input to the device and that all internal reset requirements are met + for the system (as a whole) and for the functional units. + + Please also refer to reset.txt in this directory for common reset + controller binding usage. Device nodes that need access to reset + lines should specify them as a reset phandle in their corresponding + node as specified in reset.txt. + + For list of all valid reset indices for Zynq UltraScale+ MPSoC + + + For list of all valid reset indices for Versal + + +properties: + compatible: + enum: + - xlnx,zynqmp-reset + - xlnx,versal-reset + + "#reset-cells": + const: 1 + +required: + - compatible + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; + }; + }; + + /* Specifying sata reset control of devices */ + sata { + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; + reset-names = "sata_rst"; + }; + +... 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Wed, 7 Jun 2023 01:53:26 -0500 From: Piyush Mehta To: , , , , , , CC: , , , , , Piyush Mehta Subject: [PATCH 2/2] dt-bindings: firmware: add reset-controller property Date: Wed, 7 Jun 2023 12:21:21 +0530 Message-ID: <20230607065121.2265076-3-piyush.mehta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607065121.2265076-1-piyush.mehta@amd.com> References: <20230607065121.2265076-1-piyush.mehta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT108:EE_|PH7PR12MB7329:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d30bee3-0551-4aa6-0150-08db6723e9c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eZhjb+k4m8ALHWeLAne3+EPNPdtdZ1VDvn49p3QxE9PUKbLbaSiH9rFrdTVB6N7jBy0bC81l2lUPDWRat3wsLaa8faz2z6UMpf0up5kFNzFWLP30gtj14h8LVk2Lbgs7bH/VEncHwyh//zpsw0lpYF/itoB1uHj2W8jmkdFTLuZxsDQvRn1xafNsclznbET+KdFNVXw42hQEjSwooKRIP+wVX19RXWjwRwWzWjIWO4MFsepMAHOqkLUiuhpUuzyXMKKN5RcPIgyGolccSFr+PVrt1wAD5cl9ijbunkbZ0h7ySkafZLunRYX+73JlPh/LkaTqr75DhEIjly5eWtW84Kk/U4jTm3WXNZbgAVTxnCcLe0piuahwSjb19Zuy/bOzcMHtzc8ayjtgV0WgQ9W8BZEmWG1lHlAFY94nY7UGC5R2q9S8sYUO75zwby+LRY5J+mmVlGWSMqRaSgf+0Dq3GNIhXzNDZZGGIUmIM5cslY7N9sPIWDEeE6uYq8m7aphHQcHCE5BdL+oBj7e+VQ+9U6kQpfEhIbgjNjK4mi0zJOMlWJkpzVCr+Gq7WyK+amlSa9Ga18c0pD+mUxiZ2VKtQQyPj75wJPFlY4XTC1nSUrRhkrxJOPL8eQi0NEaDZ/zVCaRXx5drvikZ3RJ/eNZJk9EaSsX5QHtmmvRt05MzXLwiKMbNQl6/trnHFHpe1oFtSlWS4YeqqA9IkMsHwrJAuv8H5GrG7lYbv7eHKgufBZ79oYM2DOTd6TfsTkOuW+KIFuAlL3ylJdZ5AGpbSL1F6lIQXAM3ZrmqMDarTsrjh0Y= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(376002)(136003)(346002)(396003)(451199021)(40470700004)(46966006)(36840700001)(86362001)(40460700003)(2906002)(110136005)(54906003)(41300700001)(8936002)(82310400005)(8676002)(5660300002)(82740400003)(356005)(36756003)(44832011)(316002)(4326008)(81166007)(70206006)(70586007)(40480700001)(6666004)(478600001)(36860700001)(186003)(83380400001)(47076005)(336012)(2616005)(426003)(26005)(1076003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2023 06:53:34.5366 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d30bee3-0551-4aa6-0150-08db6723e9c8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7329 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The reset controller is responsible for managing both device-level resets and individual PMC (Power Management Controller) block resets. To facilitate this functionality reset-controller property is added to the firmware device tree binding. Signed-off-by: Piyush Mehta --- .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index f14f7b454f07..04d875a535d3 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -59,6 +59,12 @@ properties: controller. type: object + reset-controller: + $ref: /schemas/reset/xlnx,zynqmp-reset.yaml# + description: The reset-controller has the ability to reset lines connected + to different blocks and peripherals in the SoC. + type: object + required: - compatible @@ -84,6 +90,11 @@ examples: clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>; clock-names = "ref", "alt_ref", "pl_alt_ref"; }; + + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; }; ...