From patchwork Wed Jun 7 20:28:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13271242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5C85C83005 for ; Wed, 7 Jun 2023 20:28:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=p4gDQoCN7eaaouDl+rOQf1zaLI3DtmSU8f6VxuOOXNw=; b=DHnrbJc1Gxv7me X470lom550Iahlxz61u3Bf+8NY7Bw8gIJ+GHas8RTkOKcgJOFVrQtyMLtfRw5roN1GGEOHqYtgsK7 Q/e5ej8Gv9PhisNsdJTnSupHUM7mpK9m1/acPUPIauFt4CO92J4e3nKsoKkwhzdtGzGTz1+3A4W/+ LgcV8mEPlHfoXF8AW+g2AYv9XNXvH10RFXZfkE7AKBdqa0KL91vWPCp+TflFSElpZq8k7RCRqecAK 1n3JLZc1YZMzM7jnSR9HfGc9o0uuSf1V/sTob6+0M4Sat++sXhyLtn6cQNK/kGiCxOsWEcQEZ1exj XTyzH5hIQ3D7nTV8KRdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6zlw-0077kg-2P; Wed, 07 Jun 2023 20:28:48 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6zlu-0077jz-0i for linux-riscv@lists.infradead.org; Wed, 07 Jun 2023 20:28:47 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CAB4F644BD; Wed, 7 Jun 2023 20:28:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0CE06C4339B; Wed, 7 Jun 2023 20:28:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1686169725; bh=0fKSDDjz3zPe0eu/yaZ/RlLyOC+XlCz4Pw01ZOSAsvE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rTu8mvzuSW/lmWrT1Anj81+LAJjN/CDIiX6Iv1M47X5+VVlJBeHlCWROlicz/RuN7 3ASMq4Rj9WVTLa7lcMeFJX2wDF/GLOKUrBNP8xJYEBQK/WbRstI7dUPiCMWozWqg9j urCR6w0hjUXOt2s8y45BIYUmdiVcIMsoQdivfrPsFZUAxtXnOPzKyjZO5Htzbp0MHZ fYB+fqUniMSdV5UeTjQKfY5lazyz0GglXp6D5lmUpOHvqtnErNLY0LRNxuZ8FjCf/I EP8I/nY7ospA0nEGaqjzzBH/R5vqQaJlzjPtmmcrLJg9Y6lfan/OkIKMGPRlLu3vax ijka5yjkZCKPA== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v3 1/7] RISC-V: simplify register width check in ISA string parsing Date: Wed, 7 Jun 2023 21:28:25 +0100 Message-Id: <20230607-splatter-bacterium-a75bb9f0d0b7@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud> References: <20230607-audacity-overhaul-82bb867a825f@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1686; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=wwT8xONix5hYlJl/8OtHK8R3MNUcN/a19lAVTTeA5Lc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkNLzI2ltWpT67dLMN27qTrbmWVi7eSNnTzXt7wSSNkw zon1Sl1HaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIzVaGv/Jl7fv+mNydtTGN 49CNzU7HRScdVel+Fr2naLXN6modGW6Gf+YF+7T3bWS1eLH4bEdbirvr5PImtSAb5XIBla3r2tK f8AAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_132846_305223_DA152693 X-CRM114-Status: GOOD ( 14.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , conor@kernel.org, Yangyu Chen , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Saving off the `isa` pointer to a temp variable, followed by checking if it has been incremented is a bit of an odd pattern. Perhaps it was done to avoid a funky looking if statement mixed with the ifdeffery. Now that we use IS_ENABLED() here just return from the parser as soon as we detect a mismatch between the string and the currently running kernel. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley Reviewed-by: Sunil V L --- arch/riscv/kernel/cpufeature.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e3324d661fb9..c8635211fc18 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -126,7 +126,6 @@ void __init riscv_fill_hwcap(void) for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); - const char *temp; if (acpi_disabled) { node = of_cpu_device_node_get(cpu); @@ -149,14 +148,14 @@ void __init riscv_fill_hwcap(void) } } - temp = isa; - if (IS_ENABLED(CONFIG_32BIT) && !strncasecmp(isa, "rv32", 4)) - isa += 4; - else if (IS_ENABLED(CONFIG_64BIT) && !strncasecmp(isa, "rv64", 4)) - isa += 4; - /* The riscv,isa DT property must start with rv64 or rv32 */ - if (temp == isa) + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4)) continue; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4)) + continue; + + isa += 4; + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext = isa++; From patchwork Wed Jun 7 20:28:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13271243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 445E3C7EE23 for ; Wed, 7 Jun 2023 20:28:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 7 Jun 2023 20:28:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A6713C433D2; Wed, 7 Jun 2023 20:28:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1686169727; bh=lXhMAVAHnw/Oo1O+4NojcGUuF4uMH1LW3zpYfd5lKDs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uoXyyCqpJp5OkmELmBgzRSOxxvdTXS7/jRfQ9GagZdnJx2dSYcdYduVTiuavkjFh9 bUHtEm3712JoWHKzgaxMB//ZWWlMZGYs9kY7KpUN81x3gYX4Lxtsk3gPRH4Wn4wCH7 5pWSKmp/ngpvqof3HVMWvN68xtkfZxNiFyIcYBrgY0ZS8lrhydYgXw5sReJoqauj9a fGoBjtq9OeTcZmrts8zhi4/E9VXGATlgnZY+txv4j40EA77L/pR3eo7qH/ntMQstrt BTIv1AN3Dr9zIkC/hu7zjVS/dHpLBWsnMNa+KAJsTJ46YwdEYg1Z7xfhLoebtLbnpo pe26kdsS3qPkg== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v3 2/7] RISC-V: split early & late of_node to hartid mapping Date: Wed, 7 Jun 2023 21:28:26 +0100 Message-Id: <20230607-glade-pastel-d8cbd9d9f3c6@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud> References: <20230607-audacity-overhaul-82bb867a825f@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3295; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=QiCH3jp+i6O49v44UqeRlbwmpTwYeRZiPHSENjDshIs=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkNLzIT826wPWL9nWe2gWO6o8Y0jpLXrjfuMTxqn3k5+ WZ/hSZ7RykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACYypZjhr8BNFeapTg+511i8 XnnhZG2ijqTEWuvK49yKnAv/ztn49QQjwwNG8S5GV6cor+lqu88tvD5V8lPOF/vyho8WrNnC1dN bmQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_132848_981631_5AEE6A3E X-CRM114-Status: GOOD ( 16.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , conor@kernel.org, Yangyu Chen , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Some back and forth with Drew [1] about riscv_fill_hwcap() resulted in the realisation that it is not very useful to parse the DT & perform validation of riscv,isa every time we would like to get the id for a hart. Although it is no longer called in riscv_fill_hwcap(), riscv_of_processor_hartid() is called in several other places. Notably in setup_smp() it forms part of the logic for filling the mask of possible CPUs. Since a possible CPU must have passed this basic validation of riscv,isa, a repeat validation is not required. Rename riscv_of_processor_id() to riscv_early_of_processor_id(), which will be called from setup_smp() & introduce a new riscv_of_processor_id() which makes use of the pre-populated mask of possible cpus. Link: https://lore.kernel.org/linux-riscv/xvdswl3iyikwvamny7ikrxo2ncuixshtg3f6uucjahpe3xpc5c@ud4cz4fkg5dj/ [1] Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley Reviewed-by: Sunil V L --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/kernel/cpu.c | 22 +++++++++++++++++++++- arch/riscv/kernel/smpboot.c | 2 +- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..3479f9fca4b0 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -75,6 +75,7 @@ static inline void wait_for_interrupt(void) struct device_node; int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); +int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid); int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); extern void riscv_fill_hwcap(void); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 637263f9a7b9..8025de06edb7 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -22,6 +22,26 @@ * isn't an enabled and valid RISC-V hart node. */ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) +{ + int cpu; + + *hart = (unsigned long)of_get_cpu_hwid(node, 0); + if (*hart == ~0UL) { + pr_warn("Found CPU without hart ID\n"); + return -ENODEV; + } + + cpu = riscv_hartid_to_cpuid(*hart); + if (cpu < 0) + return cpu; + + if (!cpu_possible(cpu)) + return -ENODEV; + + return 0; +} + +int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) { const char *isa; @@ -30,7 +50,7 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) return -ENODEV; } - *hart = (unsigned long) of_get_cpu_hwid(node, 0); + *hart = (unsigned long)of_get_cpu_hwid(node, 0); if (*hart == ~0UL) { pr_warn("Found CPU without hart ID\n"); return -ENODEV; diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 67bc5ef3e8b2..3f42331c8912 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -148,7 +148,7 @@ static void __init of_parse_and_init_cpus(void) cpu_set_ops(0); for_each_of_cpu_node(dn) { - rc = riscv_of_processor_hartid(dn, &hart); + rc = riscv_early_of_processor_hartid(dn, &hart); if (rc < 0) continue; From patchwork Wed Jun 7 20:28:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13271245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B6ECC7EE23 for ; Wed, 7 Jun 2023 20:29:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 7 Jun 2023 20:28:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 47EBAC433A0; Wed, 7 Jun 2023 20:28:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1686169730; bh=hJ38CPjxWwjX4V8XKtRn/M80pqJIL4wsmO+H2FqHFgA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J6GZDEBNvEbqPckqQAG9sc+1v+oU++bsVa661H2Gt8mtcuake5RIz7my4qS7+6/vJ w8h+hfdeSnr/ZhnAV7mGW1hIwqFa9nbmbo2qy+S7ZxMcFBw5/Iz8CU03gttgudGpoy R1JoyE1nJHHoF9Q7u2lrEIn7Ja3mkxeZF2VQqpreAfg9GU/ASp3Hj0D3DgHvO94/I9 a1sf4taodGsr+kcrVA6kvCSS89pSzoakn0pz4qbIc8w/DvpShi7LUVhMNzSZxbuvAf K5oe/lXndSzr2z+S8zh7C/TEDvJymwPUTJPPItPmEWREeTqKKs3vay5+96iHyx2kGH xdEkP9NvNoIEQ== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v3 3/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing Date: Wed, 7 Jun 2023 21:28:27 +0100 Message-Id: <20230607-guts-blurry-67e711acf328@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud> References: <20230607-audacity-overhaul-82bb867a825f@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1996; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=OFfsnmkyItfIBILoPmIAAAogZG8wbQXtmYDyF7w+9u4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkNLzLlLrGJrswqDD3q75XFuefGQb7GO3/Xt4emM/E7W oV2ZL3rKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwES2fGVkWCPtUR/VqdQmVXFp yiKdDwdyI15uifO8PW1TrpfLFz/jZkaG50d5FsVa9TSrrD0qxuW5fuV5m+uRYge29N86ZyFyPoO dCQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_132851_726754_CE38325D X-CRM114-Status: GOOD ( 12.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , conor@kernel.org, Yangyu Chen , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Since riscv_fill_hwcap() now only iterates over possible cpus, the basic validation of whether riscv,isa contains "rv" can be moved to riscv_early_of_processor_hartid(). Further, "ima" support is required by the kernel, so reject any CPU not fitting the bill. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley Reviewed-by: Sunil V L --- arch/riscv/kernel/cpu.c | 8 +++++--- arch/riscv/kernel/cpufeature.c | 12 ++++++------ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 8025de06edb7..dfb4a2a61050 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -65,10 +65,12 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); return -ENODEV; } - if (tolower(isa[0]) != 'r' || tolower(isa[1]) != 'v') { - pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) + return -ENODEV; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) return -ENODEV; - } return 0; } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c8635211fc18..c3851c8cfa9c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -148,12 +148,12 @@ void __init riscv_fill_hwcap(void) } } - if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4)) - continue; - - if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4)) - continue; - + /* + * For all possible cpus, we have already validated in + * the boot process that they at least contain "rv" and + * whichever of "32"/"64" this kernel supports, and so this + * section can be skipped. + */ isa += 4; bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); From patchwork Wed Jun 7 20:28:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13271244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71698C7EE25 for ; Wed, 7 Jun 2023 20:29:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Wed, 07 Jun 2023 20:28:55 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A418D644BD; Wed, 7 Jun 2023 20:28:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE8C0C4339E; Wed, 7 Jun 2023 20:28:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1686169733; bh=eY1UqwYJntMLMU5Yd8lkw/zWfSR41OHe1x/9kSmW+Ek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ApBq1xCZHN18wc0R9zdT9eYGRLFkA6Xtg9RKeBK1uqlfn1dqJN+WMxfBH91SyGYTU /vFDACsUiC8E8iX1AIZIDOc37VngXOCJ/B0e8EDXAZlbApb038tasCxdrsE+XidvPP wuljKsHEZbxxrepFeDqdWN70kGasU4E9lB1jqWrzTzQHU/DS5/loxvZSwGFZyeJpct OBgimt/NtihYGQ6rJXJ4USE3mQJxPqtV2LLh7apiRo2yB8AMnQ2ZuEEDsrI9oyvWZW noxfeEw4wDNkjFqtvkdLS0EcvMSmYJXUIJPVouAPjvUgtrflsL0RQQO3WfGdHZKUqT PRmKof92hqkFw== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v3 4/7] RISC-V: rework comments in ISA string parser Date: Wed, 7 Jun 2023 21:28:28 +0100 Message-Id: <20230607-headpiece-tannery-83ed5cc4856a@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud> References: <20230607-audacity-overhaul-82bb867a825f@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4612; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=pRBb9rN0x8kEbAvR9LC8Ni1TdOFEl8xAcaZ/+5Mew2g=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkNLzKrH83bnrv7k1D3pvfXf7RpsX4parjaJSAX6fKFS bRs4RrvjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExkaycjw15Wta0lkdNa3hw6 6c02eRH7ooSZby/tLf9ZX2t168zRu8KMDPs8Aq+taBd6dN7yyJLFgVFSqrp9833L92+Q4i6e2n5 mAyMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_132854_129923_F415ABF3 X-CRM114-Status: GOOD ( 24.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , conor@kernel.org, Yangyu Chen , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley I have found these comments to not be at all helpful whenever I look at the parser. Further, the comments in the default case (single letter parser) are not quite right either. Group the comments into a larger one at the start of each case, that attempts to explain things at a higher level. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 70 ++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c3851c8cfa9c..7dd4589e79a4 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -164,7 +164,7 @@ void __init riscv_fill_hwcap(void) switch (*ext) { case 's': - /** + /* * Workaround for invalid single-letter 's' & 'u'(QEMU). * No need to set the bit in riscv_isa as 's' & 'u' are * not valid ISA extensions. It works until multi-letter @@ -181,53 +181,101 @@ void __init riscv_fill_hwcap(void) case 'X': case 'z': case 'Z': + /* + * Before attempting to parse the extension itself, we find its end. + * As multi-letter extensions must be split from other multi-letter + * extensions with an "_", the end of a multi-letter extension will + * either be the null character or the "_" at the start of the next + * multi-letter extension. + * + * Next, as the extensions version is currently ignored, we + * eliminate that portion. This is done by parsing backwards from + * the end of the extension, removing any numbers. This may be a + * major or minor number however, so the process is repeated if a + * minor number was found. + * + * ext_end is intended to represent the first character *after* the + * name portion of an extension, but will be decremented to the last + * character itself while eliminating the extensions version number. + * A simple re-increment solves this problem. + */ ext_long = true; - /* Multi-letter extension must be delimited */ for (; *isa && *isa != '_'; ++isa) if (unlikely(!isalnum(*isa))) ext_err = true; - /* Parse backwards */ + ext_end = isa; if (unlikely(ext_err)) break; + if (!isdigit(ext_end[-1])) break; - /* Skip the minor version */ + while (isdigit(*--ext_end)) ; - if (tolower(ext_end[0]) != 'p' - || !isdigit(ext_end[-1])) { - /* Advance it to offset the pre-decrement */ + + if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { ++ext_end; break; } - /* Skip the major version */ + while (isdigit(*--ext_end)) ; + ++ext_end; break; default: + /* + * Things are a little easier for single-letter extensions, as they + * are parsed forwards. + * + * After checking that our starting position is valid, we need to + * ensure that, when isa was incremented at the start of the loop, + * that it arrived at the start of the next extension. + * + * If we are already on a non-digit, there is nothing to do. Either + * we have a multi-letter extension's _, or the start of an + * extension. + * + * Otherwise we have found the current extension's major version + * number. Parse past it, and a subsequent p/minor version number + * if present. The `p` extension must not appear immediately after + * a number, so there is no fear of missing it. + * + */ if (unlikely(!isalpha(*ext))) { ext_err = true; break; } - /* Find next extension */ + if (!isdigit(*isa)) break; - /* Skip the minor version */ + while (isdigit(*++isa)) ; + if (tolower(*isa) != 'p') break; + if (!isdigit(*++isa)) { --isa; break; } - /* Skip the major version */ + while (isdigit(*++isa)) ; + break; } + + /* + * The parser expects that at the start of an iteration isa points to the + * character before the start of the next extension. This will not be the + * case if we have just parsed a single-letter extension and the next + * extension is not a multi-letter extension prefixed with an "_". It is + * also not the case at the end of the string, where it will point to the + * terminating null character. + */ if (*isa != '_') --isa; From patchwork Wed Jun 7 20:28:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13271246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B9F5C7EE25 for ; Wed, 7 Jun 2023 20:29:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dLqp4x09ayX1lhrr56rRgQNKGME+fj4ZeDoexTz2LBQ=; b=Ui7rCHhcwjFaYu o7eYCU1kPrDfJ0VXkd1Wt38YvNH0P/JrdcBEt3P5Mffru2VOt7+uAWsCJ3FLrEfBfUi0h31JgKi8R tK0y/ctC4sjv+ycLy2OMZnaI245r0NU2QUwqvg/qvhIF0vYqtz4tE+dx8z+MOWZvoumbSrfJXH6Me uW4+RCvSQPT9pt+MSW/RRg1U/ZYBz7yMs1GFS7T8j8PV7cKcN62wv4NdpYshsaUmO8BhnZT29ij7q P8uvQ7SJejV8ekmH2laFOL2+i0UuehsLnXyvq2hH0D6yqR0fiKV/6uluY3w/rL42V3Ck0GOvQDoxU WGioTloKk6YrJ8IkTrVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6zm7-0077pL-0y; Wed, 07 Jun 2023 20:28:59 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6zm4-0077nw-2R for linux-riscv@lists.infradead.org; Wed, 07 Jun 2023 20:28:58 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4566B644C6; Wed, 7 Jun 2023 20:28:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 82497C433A0; Wed, 7 Jun 2023 20:28:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1686169735; bh=42Kr9DzcOlyMxwqIlPuzrYxXlGgPnmpJsSEXMJrIrpM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JEUvlFkCHtsoStuAUAN1kg1abUypK2wAJ0nXv/XlOUUH+7v/E6fas34a6PfjK0xP1 AVd9JohTDay4aRP7CbeIdxjS+Rt9qaIoabwmjAChDHAHfmcl+8tMGlItmeVyUtiNnB g4wsfdiQoy1wLwEOAwQ4rBgJOPknKVW5dqnH8o5cGR1JA5rEb8/gVvBg17eobBO/wF HauNqFjHNykQ8IPtICGqHerhDYRjsKLDzejSlr07wru9Nm4wArMk5oOSx0aoDrYm0w SMPz0VPufBX4tDDC6pcU04B9XApc+stdrHEOJ/aw9HwuNEPW7PkJui2OE6Ls9dfky7 n+EEV0/u6cy0Q== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v3 5/7] RISC-V: remove decrement/increment dance in ISA string parser Date: Wed, 7 Jun 2023 21:28:29 +0100 Message-Id: <20230607-estate-left-f20faabefb89@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud> References: <20230607-audacity-overhaul-82bb867a825f@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2940; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=MU74K4Z8b6PROrfxVKK7QLzTi9OJvvgiRmgVU5FGIKM=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkNLzKXrIpN0f6tv+Bou25zxfp7eQUeM/oEnXzmNP0+p VKta/ypo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABPptmH4K58Zdr3r/L8+od4L PXa+zF3PXyR59QU4ZRwLFZkonOXuyfA/btcl4Y3qN38fzRdnTNz1Zvn90DnzpjyzKToc1BHy79U WdgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_132856_878002_3D61BA9D X-CRM114-Status: GOOD ( 20.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , conor@kernel.org, Yangyu Chen , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley While expanding on the comments in the ISA string parsing code, I noticed that the conditional decrement of `isa` at the end of the loop was a bit odd. The parsing code expects that at the start of the for loop, `isa` will point to the first character of the next unparsed extension. However, depending on what the next extension is, this may not be true. Unless the next extension is a multi-letter extension preceded by an underscore, `isa` will either point to the string's null-terminator or to the first character of the next extension, once the switch statement has been evaluated. Obviously incrementing `isa` at the end of the loop could cause it to increment past the null terminator or miss a single letter extension, so `isa` is conditionally decremented, just so that the loop can increment it again. It's easier to understand the code if, instead of this decrement + increment dance, we instead use a while loop & rely on the handling of individual extension types to leave `isa` pointing to the first character of the next extension. As already mentioned, this won't be the case where the following extension is multi-letter & preceded by an underscore. To handle that, invert the check and increment rather than decrement. Hopefully this eliminates a "huh?!?" moment the next time somebody tries to understand this code. Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley Reviewed-by: Sunil V L --- arch/riscv/kernel/cpufeature.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7dd4589e79a4..84dc44a3e6e5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -157,7 +157,7 @@ void __init riscv_fill_hwcap(void) isa += 4; bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); - for (; *isa; ++isa) { + while (*isa) { const char *ext = isa++; const char *ext_end = isa; bool ext_long = false, ext_err = false; @@ -270,14 +270,12 @@ void __init riscv_fill_hwcap(void) /* * The parser expects that at the start of an iteration isa points to the - * character before the start of the next extension. This will not be the - * case if we have just parsed a single-letter extension and the next - * extension is not a multi-letter extension prefixed with an "_". It is - * also not the case at the end of the string, where it will point to the - * terminating null character. + * first character of the next extension. As we stop parsing an extension + * on meeting a non-alphanumeric character, an extra increment is needed + * where the succeeding extension is a multi-letter prefixed with an "_". */ - if (*isa != '_') - --isa; + if (*isa == '_') + ++isa; #define SET_ISA_EXT_MAP(name, bit) \ do { \ From patchwork Wed Jun 7 20:28:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13271247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80029C7EE2E for ; Wed, 7 Jun 2023 20:29:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yoDS85ze/vZ5o/l0+0FxIsxiIIdeWeJSej6+e4N84QM=; b=RHc/O5b2foM+r1 VVmMxXY3k079zfTLvzjpssVsAFWSr0x2mHtCKusrF1OD8MUnM1v8IlGpXNBuyw/VPkQntXAmE9+hk ImB58vGF+/Idxbarh6sJWQwnZDX3S0c1cCjOj0JH9U59E5I6oBjzd3/NWvQSXYvdl3gdphWkitK93 y4R2mj0GnRCySbbPweLM94+X/7Q7sKjtryD1vDWzwbBk94amGX2zI7HHeKHU2swSxZwOzq2sxSzJP 9xSpzdHUuqz6sG18cnmA9zkfcW6AsKyOaaiByhUYpLx9RUr0BjZpf4GztEkNxxiAK/0afwcxicp4h Q0449EDQNdROvZYoiWXg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6zm9-0077rB-2z; Wed, 07 Jun 2023 20:29:01 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6zm7-0077pI-1d for linux-riscv@lists.infradead.org; Wed, 07 Jun 2023 20:29:00 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 17EB8644CA; Wed, 7 Jun 2023 20:28:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 240AFC433D2; Wed, 7 Jun 2023 20:28:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1686169738; bh=vFxtHREVJ9UNBDng1m71MFH7Sb5ddr33ZSLOi8jzDkE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hVU/uMrosox7GhZBtN3DjCMhKJnUZE3rQcYVmRehFgQzXHiqV1CJWoD2BMB++Dfs3 y75HSiWEFpNlJtmqvPaIT8jr3AtnFW8NSMDkaMx/yDBNkMU7dqQJAu91ABT0aEtk0Z UEooWXMKcEsp4MDgxp6nearkENg7oWO3Sf1ByOab5n6niw+uu7HP9W+dTFIoO5Gsuy 8STDiuf7LJVAOJZ3PrW238+kVFbSjbajIBGA5CpAvBOUC8oNBvi4ffpp2xA+p/D71n svPKzM4VpK3HiZBFrnHW2wCzucMjpWVeN6N1m1WYk8kvAcf7xeH/DrMSQLLq/tzy6S RJBm9GNhvzZgA== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v3 6/7] dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support Date: Wed, 7 Jun 2023 21:28:30 +0100 Message-Id: <20230607-rerun-retinal-5e8ba89e98f1@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud> References: <20230607-audacity-overhaul-82bb867a825f@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1333; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=FqaBAVwOvKHQOTc+2d9mFz4gWPu5PBX8oewfgU7Ysuc=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkNL7JE9b1ZHx2YWfOowT5n/abnKddnzDD5eONE1I4Aj eqjT1kYO0pZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjARmyBGhi8+3BME1ogvqma3 mvMwPkPAUu/d7Iz1W9Kyiyc0+mqEPmdkaN624Hz04roMl8VSr5e1xM71clQ5nrNgX4BCPMOZoKK vXAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_132859_585460_B6C5D4C2 X-CRM114-Status: GOOD ( 12.10 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , conor@kernel.org, Yangyu Chen , Conor Dooley , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Similar to commit 41ebfc91f785 ("dt-bindings: riscv: explicitly mention assumption of Zicsr & Zifencei support"), the Zicntr and Zihpm extensions also used to be part of the base ISA but were removed after the bindings were merged. Document the assumption of their presence in the base ISA. Suggested-by: Palmer Dabbelt Signed-off-by: Conor Dooley Acked-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index db5253a2a74a..d5208881a1fb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -89,8 +89,8 @@ properties: Due to revisions of the ISA specification, some deviations have arisen over time. Notably, riscv,isa was defined prior to the creation of the - Zicsr and Zifencei extensions and thus "i" implies - "zicsr_zifencei". + Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" + implies "zicntr_zicsr_zifencei_zihpm". While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all From patchwork Wed Jun 7 20:28:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13271248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4ABE3C83005 for ; Wed, 7 Jun 2023 20:29:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=W56yAu/LVRqJ7nsl0qpWiYqy5l22GlKfn5QX0vKts5w=; b=hTXsEyFUxkDuyW LvrT5qMALYnvKRX22EqkVstXFMVOEAVO0sSrfg/A0OVJFTGFQKhvotO9SLCi2C/L9bmX+LGE85sJb 3K0OpCG1qJbOwULP+hmmpTkoGk6c6uDlXq9LGglqpRu9PVOQJpVkZ7EIMW6w0zemjXk2uTIDdA+pV ZM/WK0Xijw4vaIspp4KEa9cqvOztZYvH+b/g7A2eWrqfx9spzI6rXpnHo5kpqBDc96TfVWKtl9OKg 5F704Nkh8EudfbB4zXEJsVA8lh3FBX59au02vRKBwKaB/ERtP1EJUIevMET5b404C2LQRuJA/QnG0 vBp77vz7pgnlu3pk21sA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6zmD-0077tk-1v; Wed, 07 Jun 2023 20:29:05 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6zmA-0077rC-0q for linux-riscv@lists.infradead.org; Wed, 07 Jun 2023 20:29:03 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A8A0C644B0; Wed, 7 Jun 2023 20:29:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E565CC4339B; Wed, 7 Jun 2023 20:28:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1686169741; bh=9oebp7azzGjLgz0ypSgYRXS/QfAFTsMr5qzXixfR5fA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Xn9XhSOY0lxzKI2YpbBGSwRxnCMyzAccwqx1wVCxlJiPCma0RrclvBlI8ykecj1Ca rsmK/oj2CAYrxMg0t9gqjJpovCMqD7WbxximgFi2qF79R0y6yl1ml4ZWWGzuAWk13r mvua4QmR9DQoLwTtIlnDLHjdPPAhuSlx1cuk1SdvXjRESGi11g9ghHKfbZIci7sbkD 3vE6uU/hJ3gvIb1zj6F4O+V1xZCLGL2DN1KkipsPo3d7r0TokR0Ynah/cHJAxYTJIO wfVO+SAtC/FbgU2pHswZZ4Xknv4vqVHsHNaOtf5E1ImEvrwJjWOtCt9F6szJ8NIyBo YCkXNFYW0wOKg== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v3 7/7] RISC-V: always report presence of extensions formerly part of the base ISA Date: Wed, 7 Jun 2023 21:28:31 +0100 Message-Id: <20230607-nest-collision-5796b6be8be6@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud> References: <20230607-audacity-overhaul-82bb867a825f@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3008; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=KitXjnHxXOis6xsSJvnLbEG72mCiB4pyRS+qy+W2cAY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCkNL7Iuc69dHpYlr3xOmdMr1nSbUM0l1oYtAYUhk65sU BT56H25o5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABPZv4qRYVdaX+iZ4s5lFbs2 xn44eeIhr2Hwj5cqzAcNjRNMt5Y1nGJk2FLax2Ru9VrtZob4jr38WyWvehXLpCvf0K40Ksw7OIW JBQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_132902_381496_6BB91F54 X-CRM114-Status: GOOD ( 14.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , conor@kernel.org, Yangyu Chen , Conor Dooley , Krzysztof Kozlowski , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Of these four extensions, two were part of the base ISA when the port was written and are required by the kernel. The other two are implied when `i` is in riscv,isa on DT systems. There's not much that userspace can do with this extra information, but there is no harm in reporting an ISA string that closer resembles the current versions of the specifications either. Signed-off-by: Conor Dooley --- Intentionally avoided your conditional tag here Drew. --- arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpu.c | 4 ++++ arch/riscv/kernel/cpufeature.c | 17 +++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e0c40a4c63d5..e0eb9ad06805 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -46,6 +46,10 @@ #define RISCV_ISA_EXT_ZICBOZ 34 #define RISCV_ISA_EXT_SMAIA 35 #define RISCV_ISA_EXT_SSAIA 36 +#define RISCV_ISA_EXT_ZICNTR 37 +#define RISCV_ISA_EXT_ZICSR 38 +#define RISCV_ISA_EXT_ZIFENCEI 39 +#define RISCV_ISA_EXT_ZIHPM 40 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index dfb4a2a61050..6aea6412cf65 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -208,7 +208,11 @@ arch_initcall(riscv_cpuinfo_init); static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), + __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), + __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 84dc44a3e6e5..d21f7e8a33ef 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -311,6 +311,23 @@ void __init riscv_fill_hwcap(void) #undef SET_ISA_EXT_MAP } + /* + * Linux requires the following extensions, so we may as well + * always set them. + */ + set_bit(RISCV_ISA_EXT_ZICSR, this_isa); + set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa); + + /* + * These ones were as they were part of the base ISA when the + * port & dt-bindings were upstreamed, and so can be set + * unconditionally where `i` is in riscv,isa on DT systems. + */ + if (acpi_disabled) { + set_bit(RISCV_ISA_EXT_ZICNTR, this_isa); + set_bit(RISCV_ISA_EXT_ZIHPM, this_isa); + } + /* * All "okay" hart should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't