From patchwork Thu Jun 8 07:58:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED455C7EE29 for ; Thu, 8 Jun 2023 07:58:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233854AbjFHH6n (ORCPT ); Thu, 8 Jun 2023 03:58:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232040AbjFHH6l (ORCPT ); Thu, 8 Jun 2023 03:58:41 -0400 Received: from mail-qt1-x831.google.com (mail-qt1-x831.google.com [IPv6:2607:f8b0:4864:20::831]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A4351BF9 for ; Thu, 8 Jun 2023 00:58:40 -0700 (PDT) Received: by mail-qt1-x831.google.com with SMTP id d75a77b69052e-3f6a494810fso2783251cf.1 for ; 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} - printf("unhandled cpu exception %#lx\n", regs->trap); + printf("unhandled cpu exception %#lx at NIA:0x%016lx MSR:0x%016lx\n", regs->trap, regs->nip, regs->msr); abort(); } From patchwork Thu Jun 8 07:58:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BE2AC7EE23 for ; Thu, 8 Jun 2023 07:58:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233896AbjFHH6r (ORCPT ); Thu, 8 Jun 2023 03:58:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232040AbjFHH6p (ORCPT ); Thu, 8 Jun 2023 03:58:45 -0400 Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C2921FFE for ; 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Signed-off-by: Nicholas Piggin Reviewed-by: Thomas Huth --- Since v3: - Simplified code as suggested by Thomas. lib/powerpc/processor.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c index 05b4b04f..0550e4fc 100644 --- a/lib/powerpc/processor.c +++ b/lib/powerpc/processor.c @@ -19,12 +19,16 @@ static struct { void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void * data) { + assert(!(trap & ~0xf00)); + trap >>= 8; - if (trap < 16) { - handlers[trap].func = func; - handlers[trap].data = data; + if (func && handlers[trap].func) { + printf("exception handler installed twice %#x\n", trap); + abort(); } + handlers[trap].func = func; + handlers[trap].data = data; } void do_handle_exception(struct pt_regs *regs) From patchwork Thu Jun 8 07:58:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23A43C7EE23 for ; Thu, 8 Jun 2023 07:58:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233955AbjFHH6x (ORCPT ); Thu, 8 Jun 2023 03:58:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233894AbjFHH6t (ORCPT ); Thu, 8 Jun 2023 03:58:49 -0400 Received: from mail-qt1-x82b.google.com (mail-qt1-x82b.google.com [IPv6:2607:f8b0:4864:20::82b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A7BE212E for ; Thu, 8 Jun 2023 00:58:48 -0700 (PDT) Received: by mail-qt1-x82b.google.com with SMTP id d75a77b69052e-3f6c6020cfbso2191101cf.2 for ; Thu, 08 Jun 2023 00:58:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686211127; x=1688803127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mmEhHDXqBF9dQ1veYws/GnTEIhu9OPeqy9gy1d4w4DM=; b=FSas9QUg0UpdaLQcAcrgO+WSq/ocmCN8xKJ4KaAPW84Dm1aS8VCARaSFulSe1vWHVS nrK/ONUP3MvBx+ePiWqriKeg3gwanhQv3yghafty8pF3wexJAcWqGSlsqHNN/hYxpbVx iohdAGMELlqbyrR8sZX40mSSF9+OkqzutNEnwViW3tAxDM8+cMxIRyESG1ZQY1Z7ocn8 OZI+QSIJBk912zU93j7b1fGjUwsDG0aMnGmnLHF2+05BG+doiwRs2jNYDntLYaymX6fm 8v1+3JtWuBZQC7NCSDy5QB7RXn/DXmu1VRb2dSD20bZBPHiVMbW3y1esS9kEa82tK/DM k8WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686211127; x=1688803127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mmEhHDXqBF9dQ1veYws/GnTEIhu9OPeqy9gy1d4w4DM=; b=eZqVwbOcXC+9y34lUaRCbMtd1fc3wDMLd7dujIEv9t5DmWsQ+6aeJyhkJNMfkCZUnP F9cbQDK5CdJ1vgj2AhTPzdQuKAC+s9sCrgOxRaouiqnspTl5j49PYodMa0JKDR4bKtE0 u2nOQyI9mB157I6L97TaPeJBI3AC1kTzEJHlChID3HydbS9rDqXapA/UI8uWlXNFDgmD RFGyf6+he1mMlr37BtO4Zqhatqwr9THx1Rdh4M2RXlm8s36me4q76eH9QRjeaDrCGoeh aRdrCrIF92az4sJ82wni7uanMUmY4NdXzxxuO3vVzUlmiMO5UP0xO1SprIcZzcwj2EAf ALKA== X-Gm-Message-State: AC+VfDyeur2c6ySmXLGrT/psoWYBmiBbXHYgo/qS8uXXBOkq/IZ+/oYS hfWO038V+kuKlA7t9VIOFlK9T8CBapw= X-Google-Smtp-Source: ACHHUZ5pZcO+N3Su+GOBU3WMg4D9ivP4jx6OqrrOSe/69gNNpjrbL1hXdwcvJQzjzuzgsPF6UNMhWw== X-Received: by 2002:a05:622a:180a:b0:3f8:6b32:480d with SMTP id t10-20020a05622a180a00b003f86b32480dmr6247042qtc.46.1686211126897; Thu, 08 Jun 2023 00:58:46 -0700 (PDT) Received: from wheely.local0.net ([1.146.34.117]) by smtp.gmail.com with ESMTPSA id 17-20020a630011000000b00542d7720a6fsm673182pga.88.2023.06.08.00.58.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 00:58:46 -0700 (PDT) From: Nicholas Piggin To: kvm@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Laurent Vivier , Thomas Huth Subject: [kvm-unit-tests v4 03/12] powerpc: Abstract H_CEDE calls into a sleep functions Date: Thu, 8 Jun 2023 17:58:17 +1000 Message-Id: <20230608075826.86217-4-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608075826.86217-1-npiggin@gmail.com> References: <20230608075826.86217-1-npiggin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This consolidates several implementations, and it no longer leaves MSR[EE] enabled after the decrementer interrupt is handled, but rather disables it on return. The handler no longer allows a continuous ticking, but rather dec has to be re-armed and EE re-enabled (e.g., via H_CEDE hcall) each time. Signed-off-by: Nicholas Piggin --- lib/powerpc/asm/handlers.h | 2 +- lib/powerpc/asm/ppc_asm.h | 1 + lib/powerpc/asm/processor.h | 7 ++++++ lib/powerpc/handlers.c | 10 ++++----- lib/powerpc/processor.c | 43 +++++++++++++++++++++++++++++++++++++ powerpc/sprs.c | 6 +----- powerpc/tm.c | 20 +---------------- 7 files changed, 58 insertions(+), 31 deletions(-) diff --git a/lib/powerpc/asm/handlers.h b/lib/powerpc/asm/handlers.h index 64ba727a..e4a0cd45 100644 --- a/lib/powerpc/asm/handlers.h +++ b/lib/powerpc/asm/handlers.h @@ -3,6 +3,6 @@ #include -void dec_except_handler(struct pt_regs *regs, void *data); +void dec_handler_oneshot(struct pt_regs *regs, void *data); #endif /* _ASMPOWERPC_HANDLERS_H_ */ diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h index 1b85f6bb..6299ff53 100644 --- a/lib/powerpc/asm/ppc_asm.h +++ b/lib/powerpc/asm/ppc_asm.h @@ -36,6 +36,7 @@ #endif /* __BYTE_ORDER__ */ /* Machine State Register definitions: */ +#define MSR_EE_BIT 15 /* External Interrupts Enable */ #define MSR_SF_BIT 63 /* 64-bit mode */ #endif /* _ASMPOWERPC_PPC_ASM_H */ diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h index ac001e18..ebfeff2b 100644 --- a/lib/powerpc/asm/processor.h +++ b/lib/powerpc/asm/processor.h @@ -20,6 +20,8 @@ static inline uint64_t get_tb(void) extern void delay(uint64_t cycles); extern void udelay(uint64_t us); +extern void sleep_tb(uint64_t cycles); +extern void usleep(uint64_t us); static inline void mdelay(uint64_t ms) { @@ -27,4 +29,9 @@ static inline void mdelay(uint64_t ms) udelay(1000); } +static inline void msleep(uint64_t ms) +{ + usleep(ms * 1000); +} + #endif /* _ASMPOWERPC_PROCESSOR_H_ */ diff --git a/lib/powerpc/handlers.c b/lib/powerpc/handlers.c index c8721e0a..296f14ff 100644 --- a/lib/powerpc/handlers.c +++ b/lib/powerpc/handlers.c @@ -9,15 +9,13 @@ #include #include #include +#include /* * Generic handler for decrementer exceptions (0x900) - * Just reset the decrementer back to the value specified when registering the - * handler + * Return with MSR[EE] disabled. */ -void dec_except_handler(struct pt_regs *regs __unused, void *data) +void dec_handler_oneshot(struct pt_regs *regs, void *data) { - uint64_t dec = *((uint64_t *) data); - - asm volatile ("mtdec %0" : : "r" (dec)); + regs->msr &= ~(1UL << MSR_EE_BIT); } diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c index 0550e4fc..aaf45b68 100644 --- a/lib/powerpc/processor.c +++ b/lib/powerpc/processor.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include static struct { void (*func)(struct pt_regs *, void *data); @@ -58,3 +60,44 @@ void udelay(uint64_t us) { delay((us * tb_hz) / 1000000); } + +void sleep_tb(uint64_t cycles) +{ + uint64_t start, end, now; + + start = now = get_tb(); + end = start + cycles; + + while (end > now) { + uint64_t left = end - now; + + /* TODO: Could support large decrementer */ + if (left > 0x7fffffff) + left = 0x7fffffff; + + /* DEC won't fire until H_CEDE is called because EE=0 */ + asm volatile ("mtdec %0" : : "r" (left)); + handle_exception(0x900, &dec_handler_oneshot, NULL); + /* + * H_CEDE is called with MSR[EE] clear and enables it as part + * of the hcall, returning with EE enabled. The dec interrupt + * is then taken immediately and the handler disables EE. + * + * If H_CEDE returned for any other interrupt than dec + * expiring, that is considered an unhandled interrupt and + * the test case would be stopped. + */ + if (hcall(H_CEDE) != H_SUCCESS) { + printf("H_CEDE failed\n"); + abort(); + } + handle_exception(0x900, NULL, NULL); + + now = get_tb(); + } +} + +void usleep(uint64_t us) +{ + sleep_tb((us * tb_hz) / 1000000); +} diff --git a/powerpc/sprs.c b/powerpc/sprs.c index 5cc1cd16..ba4ddee4 100644 --- a/powerpc/sprs.c +++ b/powerpc/sprs.c @@ -254,7 +254,6 @@ int main(int argc, char **argv) 0x1234567890ABCDEFULL, 0xFEDCBA0987654321ULL, -1ULL, }; - static uint64_t decr = 0x7FFFFFFF; /* Max value */ for (i = 1; i < argc; i++) { if (!strcmp(argv[i], "-w")) { @@ -288,10 +287,7 @@ int main(int argc, char **argv) if (pause) { migrate_once(); } else { - puts("Sleeping...\n"); - handle_exception(0x900, &dec_except_handler, &decr); - asm volatile ("mtdec %0" : : "r" (0x3FFFFFFF)); - hcall(H_CEDE); + msleep(2000); } get_sprs(after); diff --git a/powerpc/tm.c b/powerpc/tm.c index 65cacdf5..7fa91636 100644 --- a/powerpc/tm.c +++ b/powerpc/tm.c @@ -48,17 +48,6 @@ static int count_cpus_with_tm(void) return available; } -static int h_cede(void) -{ - register uint64_t r3 asm("r3") = H_CEDE; - - asm volatile ("sc 1" : "+r"(r3) : - : "r0", "r4", "r5", "r6", "r7", "r8", "r9", - "r10", "r11", "r12", "xer", "ctr", "cc"); - - return r3; -} - /* * Enable transactional memory * Returns: FALSE - Failure @@ -95,14 +84,10 @@ static bool enable_tm(void) static void test_h_cede_tm(int argc, char **argv) { int i; - static uint64_t decr = 0x3FFFFF; /* ~10ms */ if (argc > 2) report_abort("Unsupported argument: '%s'", argv[2]); - handle_exception(0x900, &dec_except_handler, &decr); - asm volatile ("mtdec %0" : : "r" (decr)); - if (!start_all_cpus(halt, 0)) report_abort("Failed to start secondary cpus"); @@ -120,10 +105,7 @@ static void test_h_cede_tm(int argc, char **argv) "bf 2,1b" : : : "cr0"); for (i = 0; i < 500; i++) { - uint64_t rval = h_cede(); - - if (rval != H_SUCCESS) - break; + msleep(10); mdelay(5); } From patchwork Thu Jun 8 07:58:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 153BCC7EE23 for ; Thu, 8 Jun 2023 07:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234001AbjFHH64 (ORCPT ); Thu, 8 Jun 2023 03:58:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233680AbjFHH6x (ORCPT ); Thu, 8 Jun 2023 03:58:53 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62273213C for ; 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Reviewed-by: Thomas Huth Signed-off-by: Nicholas Piggin --- powerpc/sprs.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/powerpc/sprs.c b/powerpc/sprs.c index ba4ddee4..6ee6dba6 100644 --- a/powerpc/sprs.c +++ b/powerpc/sprs.c @@ -117,6 +117,15 @@ static void set_sprs_book3s_300(uint64_t val) mtspr(823, val); /* PSSCR */ } +/* SPRs from Power ISA Version 3.1B */ +static void set_sprs_book3s_31(uint64_t val) +{ + set_sprs_book3s_207(val); + mtspr(48, val); /* PIDR */ + /* 3.1 removes TIDR */ + mtspr(823, val); /* PSSCR */ +} + static void set_sprs(uint64_t val) { uint32_t pvr = mfspr(287); /* Processor Version Register */ @@ -137,6 +146,9 @@ static void set_sprs(uint64_t val) case 0x4e: /* POWER9 */ set_sprs_book3s_300(val); break; + case 0x80: /* POWER10 */ + set_sprs_book3s_31(val); + break; default: puts("Warning: Unknown processor version!\n"); } @@ -220,6 +232,13 @@ static void get_sprs_book3s_300(uint64_t *v) v[823] = mfspr(823); /* PSSCR */ } +static void get_sprs_book3s_31(uint64_t *v) +{ + get_sprs_book3s_207(v); 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Thu, 08 Jun 2023 00:58:54 -0700 (PDT) From: Nicholas Piggin To: kvm@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Laurent Vivier , Thomas Huth Subject: [kvm-unit-tests v4 05/12] powerpc: Extract some common helpers and defines to headers Date: Thu, 8 Jun 2023 17:58:19 +1000 Message-Id: <20230608075826.86217-6-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608075826.86217-1-npiggin@gmail.com> References: <20230608075826.86217-1-npiggin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Move some common helpers and defines to processor.h. Signed-off-by: Nicholas Piggin --- lib/powerpc/asm/processor.h | 38 +++++++++++++++++++++++++++++++++---- powerpc/spapr_hcall.c | 9 +-------- powerpc/sprs.c | 9 --------- 3 files changed, 35 insertions(+), 21 deletions(-) diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h index ebfeff2b..4ad6612b 100644 --- a/lib/powerpc/asm/processor.h +++ b/lib/powerpc/asm/processor.h @@ -9,13 +9,43 @@ void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void *); void do_handle_exception(struct pt_regs *regs); #endif /* __ASSEMBLY__ */ -static inline uint64_t get_tb(void) +#define SPR_TB 0x10c +#define SPR_SPRG0 0x110 +#define SPR_SPRG1 0x111 +#define SPR_SPRG2 0x112 +#define SPR_SPRG3 0x113 + +static inline uint64_t mfspr(int nr) { - uint64_t tb; + uint64_t ret; + + asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr) : "memory"); + + return ret; +} - asm volatile ("mfspr %[tb],268" : [tb] "=r" (tb)); +static inline void mtspr(int nr, uint64_t val) +{ + asm volatile("mtspr %0,%1" : : "i"(nr), "r"(val) : "memory"); +} + +static inline uint64_t mfmsr(void) +{ + uint64_t msr; - return tb; + asm volatile ("mfmsr %[msr]" : [msr] "=r" (msr) :: "memory"); + + return msr; +} + +static inline void mtmsr(uint64_t msr) +{ + asm volatile ("mtmsrd %[msr]" :: [msr] "r" (msr) : "memory"); +} + +static inline uint64_t get_tb(void) +{ + return mfspr(SPR_TB); } extern void delay(uint64_t cycles); diff --git a/powerpc/spapr_hcall.c b/powerpc/spapr_hcall.c index 823a574a..0d0f25af 100644 --- a/powerpc/spapr_hcall.c +++ b/powerpc/spapr_hcall.c @@ -9,20 +9,13 @@ #include #include #include +#include #define PAGE_SIZE 4096 #define H_ZERO_PAGE (1UL << (63-48)) #define H_COPY_PAGE (1UL << (63-49)) -#define mfspr(nr) ({ \ - uint64_t ret; \ - asm volatile("mfspr %0,%1" : "=r"(ret) : "i"(nr)); \ - ret; \ -}) - -#define SPR_SPRG0 0x110 - /** * Test the H_SET_SPRG0 h-call by setting some values and checking whether * the SPRG0 register contains the correct values afterwards diff --git a/powerpc/sprs.c b/powerpc/sprs.c index 6ee6dba6..57e487ce 100644 --- a/powerpc/sprs.c +++ b/powerpc/sprs.c @@ -28,15 +28,6 @@ #include #include -#define mfspr(nr) ({ \ - uint64_t ret; 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Thu, 08 Jun 2023 00:58:59 -0700 (PDT) From: Nicholas Piggin To: kvm@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Laurent Vivier , Thomas Huth Subject: [kvm-unit-tests v4 06/12] powerpc/sprs: Specify SPRs with data rather than code Date: Thu, 8 Jun 2023 17:58:20 +1000 Message-Id: <20230608075826.86217-7-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608075826.86217-1-npiggin@gmail.com> References: <20230608075826.86217-1-npiggin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A significant rework that builds an array of 'struct spr', where each element describes an SPR. This makes various metadata about the SPR like name and access type easier to carry and use. Hypervisor privileged registers are described despite not being used at the moment for completeness, but also the code might one day be reused for a hypervisor-privileged test. Acked-by: Thomas Huth Signed-off-by: Nicholas Piggin --- This ended up a little over-engineered perhaps, but there are lots of SPRs, lots of access types, lots of changes between processor and ISA versions, and lots of places they are implemented and used, so lots of room for mistakes. There is not a good system in place to easily see that userspace, supervisor, etc., switches perform all the right SPR context switching so this is a nice test case to have. The sprs test quickly caught a few QEMU TCG SPR bugs which really motivated me to improve the SPR coverage. --- powerpc/sprs.c | 643 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 450 insertions(+), 193 deletions(-) diff --git a/powerpc/sprs.c b/powerpc/sprs.c index 57e487ce..d5664201 100644 --- a/powerpc/sprs.c +++ b/powerpc/sprs.c @@ -28,231 +28,465 @@ #include #include -uint64_t before[1024], after[1024]; - -/* Common SPRs for all PowerPC CPUs */ -static void set_sprs_common(uint64_t val) +/* "Indirect" mfspr/mtspr which accept a non-constant spr number */ +static uint64_t __mfspr(unsigned spr) { - mtspr(9, val); /* CTR */ - // mtspr(273, val); /* SPRG1 */ /* Used by our exception handler */ - mtspr(274, val); /* SPRG2 */ - mtspr(275, val); /* SPRG3 */ + uint64_t tmp; + uint64_t ret; + + asm volatile( +" bcl 20, 31, 1f \n" +"1: mflr %0 \n" +" addi %0, %0, (2f-1b) \n" +" add %0, %0, %2 \n" +" mtctr %0 \n" +" bctr \n" +"2: \n" +".LSPR=0 \n" +".rept 1024 \n" +" mfspr %1, .LSPR \n" +" b 3f \n" +" .LSPR=.LSPR+1 \n" +".endr \n" +"3: \n" + : "=&r"(tmp), + "=r"(ret) + : "r"(spr*8) /* 8 bytes per 'mfspr ; b' block */ + : "lr", "ctr"); + + return ret; } -/* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */ -static void set_sprs_book3s_201(uint64_t val) +static void __mtspr(unsigned spr, uint64_t val) { - mtspr(18, val); /* DSISR */ - mtspr(19, val); /* DAR */ - mtspr(152, val); /* CTRL */ - mtspr(256, val); /* VRSAVE */ - mtspr(786, val); /* MMCRA */ - mtspr(795, val); /* MMCR0 */ - mtspr(798, val); /* MMCR1 */ + uint64_t tmp; + + asm volatile( +" bcl 20, 31, 1f \n" +"1: mflr %0 \n" +" addi %0, %0, (2f-1b) \n" +" add %0, %0, %2 \n" +" mtctr %0 \n" +" bctr \n" +"2: \n" +".LSPR=0 \n" +".rept 1024 \n" +" mtspr .LSPR, %1 \n" +" b 3f \n" +" .LSPR=.LSPR+1 \n" +".endr \n" +"3: \n" + : "=&r"(tmp) + : "r"(val), + "r"(spr*8) /* 8 bytes per 'mfspr ; b' block */ + : "lr", "ctr", "xer"); } +static uint64_t before[1024], after[1024]; + +#define SPR_PR_READ 0x0001 +#define SPR_PR_WRITE 0x0002 +#define SPR_OS_READ 0x0010 +#define SPR_OS_WRITE 0x0020 +#define SPR_HV_READ 0x0100 +#define SPR_HV_WRITE 0x0200 + +#define RW 0x333 +#define RO 0x111 +#define WO 0x222 +#define OS_RW 0x330 +#define OS_RO 0x110 +#define OS_WO 0x220 +#define HV_RW 0x300 +#define HV_RO 0x100 +#define HV_WO 0x200 + +#define SPR_ASYNC 0x1000 /* May be updated asynchronously */ +#define SPR_INT 0x2000 /* May be updated by synchronous interrupt */ +#define SPR_HARNESS 0x4000 /* Test harness uses the register */ + +struct spr { + const char *name; + uint8_t width; + uint16_t access; + uint16_t type; +}; + +/* SPRs common denominator back to PowerPC Operating Environment Architecture */ +static const struct spr sprs_common[1024] = { + [1] = {"XER", 64, RW, SPR_HARNESS, }, /* Compiler */ + [8] = {"LR", 64, RW, SPR_HARNESS, }, /* Compiler, mfspr/mtspr */ + [9] = {"CTR", 64, RW, SPR_HARNESS, }, /* Compiler, mfspr/mtspr */ + [18] = {"DSISR", 32, OS_RW, SPR_INT, }, + [19] = {"DAR", 64, OS_RW, SPR_INT, }, + [26] = {"SRR0", 64, OS_RW, SPR_INT, }, + [27] = {"SRR1", 64, OS_RW, SPR_INT, }, +[268] = {"TB", 64, RO , SPR_ASYNC, }, +[269] = {"TBU", 32, RO, SPR_ASYNC, }, +[272] = {"SPRG0", 64, OS_RW, SPR_HARNESS, }, /* Int stack */ +[273] = {"SPRG1", 64, OS_RW, SPR_HARNESS, }, /* Scratch */ +[274] = {"SPRG2", 64, OS_RW, }, +[275] = {"SPRG3", 64, OS_RW, }, +[287] = {"PVR", 32, OS_RO, }, +}; + +/* SPRs from PowerPC Operating Environment Architecture, Book III, Vers. 2.01 */ +static const struct spr sprs_201[1024] = { + [22] = {"DEC", 32, OS_RW, SPR_ASYNC, }, + [25] = {"SDR1", 64, HV_RW | OS_RO, }, + [29] = {"ACCR", 64, OS_RW, }, +[136] = {"CTRL", 32, RO, }, +[152] = {"CTRL", 32, OS_WO, }, +[259] = {"SPRG3", 64, RO, }, +/* ASR, EAR omitted */ +[268] = {"TB", 64, RO, }, +[269] = {"TBU", 32, RO, }, +[284] = {"TBL", 32, HV_WO, }, +[285] = {"TBU", 32, HV_WO, }, +[310] = {"HDEC", 32, HV_RW, }, +[1013]= {"DABR", 64, HV_RW | OS_RO, }, +[1023]= {"PIR", 32, OS_RO, }, +}; + +static const struct spr sprs_970_pmu[1024] = { +/* POWER4+ PMU, should find PPC970 and confirm */ +[770] = {"MMCRA", 64, RO, }, +[771] = {"PMC1", 32, RO, }, +[772] = {"PMC2", 32, RO, }, +[773] = {"PMC3", 32, RO, }, +[774] = {"PMC4", 32, RO, }, +[775] = {"PMC5", 32, RO, }, +[776] = {"PMC6", 32, RO, }, +[777] = {"PMC7", 32, RO, }, +[778] = {"PMC8", 32, RO, }, +[779] = {"MMCR0", 64, RO, }, +[780] = {"SIAR", 64, RO, }, +[781] = {"SDAR", 64, RO, }, +[782] = {"MMCR1", 64, RO, }, +[786] = {"MMCRA", 64, OS_RW, }, +[787] = {"PMC1", 32, OS_RW, }, +[788] = {"PMC2", 32, OS_RW, }, +[789] = {"PMC3", 32, OS_RW, }, +[790] = {"PMC4", 32, OS_RW, }, +[791] = {"PMC5", 32, OS_RW, }, +[792] = {"PMC6", 32, OS_RW, }, +[793] = {"PMC7", 32, OS_RW, }, +[794] = {"PMC8", 32, OS_RW, }, +[795] = {"MMCR0", 64, OS_RW, }, +[796] = {"SIAR", 64, OS_RW, }, +[797] = {"SDAR", 64, OS_RW, }, +[798] = {"MMCR1", 64, OS_RW, }, +}; + +/* These are common SPRs from 2.07S onward (POWER CPUs that support KVM HV) */ +static const struct spr sprs_power_common[1024] = { + [3] = {"DSCR", 64, RW, }, + [13] = {"AMR", 64, RW, }, + [17] = {"DSCR", 64, OS_RW, }, + [28] = {"CFAR", 64, OS_RW, SPR_ASYNC, }, /* Effectively async */ + [29] = {"AMR", 64, OS_RW, }, + [61] = {"IAMR", 64, OS_RW, }, +[136] = {"CTRL", 32, RO, }, +[152] = {"CTRL", 32, OS_WO, }, +[153] = {"FSCR", 64, OS_RW, }, +[157] = {"UAMOR", 64, OS_RW, }, +[159] = {"PSPB", 32, OS_RW, }, +[176] = {"DPDES", 64, HV_RW | OS_RO, }, +[180] = {"DAWR0", 64, HV_RW, }, +[186] = {"RPR", 64, HV_RW, }, +[187] = {"CIABR", 64, HV_RW, }, +[188] = {"DAWRX0", 32, HV_RW, }, +[190] = {"HFSCR", 64, HV_RW, }, +[256] = {"VRSAVE", 32, RW, }, +[259] = {"SPRG3", 64, RO, }, +[284] = {"TBL", 32, HV_WO, }, +[285] = {"TBU", 32, HV_WO, }, +[286] = {"TBU40", 64, HV_WO, }, +[304] = {"HSPRG0", 64, HV_RW, }, +[305] = {"HSPRG1", 64, HV_RW, }, +[306] = {"HDSISR", 32, HV_RW, SPR_INT, }, +[307] = {"HDAR", 64, HV_RW, SPR_INT, }, +[308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, +[309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, +[313] = {"HRMOR", 64, HV_RW, }, +[314] = {"HSRR0", 64, HV_RW, SPR_INT, }, +[315] = {"HSRR1", 64, HV_RW, SPR_INT, }, +[318] = {"LPCR", 64, HV_RW, }, +[319] = {"LPIDR", 32, HV_RW, }, +[336] = {"HMER", 64, HV_RW, }, +[337] = {"HMEER", 64, HV_RW, }, +[338] = {"PCR", 64, HV_RW, }, +[349] = {"AMOR", 64, HV_RW, }, +[446] = {"TIR", 64, OS_RO, }, +[800] = {"BESCRS", 64, RW, }, +[801] = {"BESCRSU", 32, RW, }, +[802] = {"BESCRR", 64, RW, }, +[803] = {"BESCRRU", 32, RW, }, +[804] = {"EBBHR", 64, RW, }, +[805] = {"EBBRR", 64, RW, }, +[806] = {"BESCR", 64, RW, }, +[815] = {"TAR", 64, RW, }, +[848] = {"IC", 64, HV_RW | OS_RO, SPR_ASYNC, }, +[849] = {"VTB", 64, HV_RW | OS_RO, SPR_ASYNC, }, +[896] = {"PPR", 64, RW, }, +[898] = {"PPR32", 32, RW, }, +[1023]= {"PIR", 32, OS_RO, }, +}; + +static const struct spr sprs_tm[1024] = { +#if 0 + /* XXX: leave these out until enabling TM facility (and more testing) */ +[128] = {"TFHAR", 64, RW, }, +[129] = {"TFIAR", 64, RW, }, +[130] = {"TEXASR", 64, RW, }, +[131] = {"TEXASRU", 32, RW, }, +#endif +}; + /* SPRs from PowerISA 2.07 Book III-S */ -static void set_sprs_book3s_207(uint64_t val) -{ - mtspr(3, val); /* DSCR */ - mtspr(13, val); /* AMR */ - mtspr(17, val); /* DSCR */ - mtspr(18, val); /* DSISR */ - mtspr(19, val); /* DAR */ - mtspr(29, val); /* AMR */ - mtspr(61, val); /* IAMR */ - // mtspr(152, val); /* CTRL */ /* TODO: Needs a fix in KVM */ - mtspr(153, val); /* FSCR */ - mtspr(157, val); /* UAMOR */ - mtspr(159, val); /* PSPB */ - mtspr(256, val); /* VRSAVE */ - // mtspr(272, val); /* SPRG0 */ /* Used by our exception handler */ - mtspr(769, val); /* MMCR2 */ - mtspr(770, val); /* MMCRA */ - mtspr(771, val); /* PMC1 */ - mtspr(772, val); /* PMC2 */ - mtspr(773, val); /* PMC3 */ - mtspr(774, val); /* PMC4 */ - mtspr(775, val); /* PMC5 */ - mtspr(776, val); /* PMC6 */ - mtspr(779, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ - mtspr(784, val); /* SIER */ - mtspr(785, val); /* MMCR2 */ - mtspr(786, val); /* MMCRA */ - mtspr(787, val); /* PMC1 */ - mtspr(788, val); /* PMC2 */ - mtspr(789, val); /* PMC3 */ - mtspr(790, val); /* PMC4 */ - mtspr(791, val); /* PMC5 */ - mtspr(792, val); /* PMC6 */ - mtspr(795, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); /* MMCR0 */ - mtspr(796, val); /* SIAR */ - mtspr(797, val); /* SDAR */ - mtspr(798, val); /* MMCR1 */ - mtspr(800, val); /* BESCRS */ - mtspr(801, val); /* BESCCRSU */ - mtspr(802, val); /* BESCRR */ - mtspr(803, val); /* BESCRRU */ - mtspr(804, val); /* EBBHR */ - mtspr(805, val); /* EBBRR */ - mtspr(806, val); /* BESCR */ - mtspr(815, val); /* TAR */ -} +static const struct spr sprs_207[1024] = { + [22] = {"DEC", 32, OS_RW, SPR_ASYNC, }, + [25] = {"SDR1", 64, HV_RW, }, +[177] = {"DHDES", 64, HV_RW, }, +[283] = {"CIR", 32, OS_RO, }, +[310] = {"HDEC", 32, HV_RW, SPR_ASYNC, }, +[312] = {"RMOR", 64, HV_RW, }, +[339] = {"HEIR", 32, HV_RW, }, +}; /* SPRs from PowerISA 3.00 Book III */ -static void set_sprs_book3s_300(uint64_t val) -{ - set_sprs_book3s_207(val); - mtspr(48, val); /* PIDR */ - mtspr(144, val); /* TIDR */ - mtspr(823, val); /* PSSCR */ -} +static const struct spr sprs_300[1024] = { + [22] = {"DEC", 64, OS_RW, SPR_ASYNC, }, + [48] = {"PIDR", 32, OS_RW, }, +[144] = {"TIDR", 64, OS_RW, }, +[283] = {"CIR", 32, OS_RO, }, +[310] = {"HDEC", 64, HV_RW, SPR_ASYNC, }, +[339] = {"HEIR", 32, HV_RW, }, +[464] = {"PTCR", 64, HV_RW, }, +[816] = {"ASDR", 64, HV_RW, SPR_INT}, +[823] = {"PSSCR", 64, OS_RW, }, +[855] = {"PSSCR", 64, HV_RW, }, +}; -/* SPRs from Power ISA Version 3.1B */ -static void set_sprs_book3s_31(uint64_t val) -{ - set_sprs_book3s_207(val); - mtspr(48, val); /* PIDR */ - /* 3.1 removes TIDR */ - mtspr(823, val); /* PSSCR */ -} +/* SPRs from PowerISA 3.1B Book III */ +static const struct spr sprs_31[1024] = { + [22] = {"DEC", 64, OS_RW, SPR_ASYNC, }, + [48] = {"PIDR", 32, OS_RW, }, +[181] = {"DAWR1", 64, HV_RW, }, +[189] = {"DAWRX1", 32, HV_RW, }, +[310] = {"HDEC", 64, HV_RW, SPR_ASYNC, }, +[339] = {"HEIR", 64, HV_RW, }, +[455] = {"HDEXCR", 32, RO, }, +[464] = {"PTCR", 64, HV_RW, }, +[468] = {"HASHKEYR", 64, OS_RW, }, +[469] = {"HASHPKEYR", 64, HV_RW, }, +[471] = {"HDEXCR", 64, HV_RW, }, +[812] = {"DEXCR", 32, RO, }, +[816] = {"ASDR", 64, HV_RW, SPR_INT, }, +[823] = {"PSSCR", 64, OS_RW, }, +[828] = {"DEXCR", 64, OS_RW, }, +[855] = {"PSSCR", 64, HV_RW, }, +}; -static void set_sprs(uint64_t val) +/* SPRs POWER9, POWER10 User Manual */ +static const struct spr sprs_power9_10[1024] = { +[276] = {"SPRC", 64, HV_RW, }, +[266] = {"SPRD", 64, HV_RW, }, +[317] = {"TFMR", 64, HV_RW, }, +[799] = {"IMC", 64, HV_RW, }, +[850] = {"LDBAR", 64, HV_RO, }, +[851] = {"MMCRC", 32, HV_RW, }, +[853] = {"PMSR", 32, HV_RO, }, +[861] = {"L2QOSR", 64, HV_WO, }, +[881] = {"TRIG1", 64, OS_WO, }, +[882] = {"TRIG2", 64, OS_WO, }, +[884] = {"PMCR", 64, HV_RW, }, +[885] = {"RWMR", 64, HV_RW, }, +[895] = {"WORT", 64, OS_RW, }, /* UM says 18-bits! */ +[921] = {"TSCR", 32, HV_RW, }, +[922] = {"TTR", 64, HV_RW, }, +[1006]= {"TRACE", 64, WO, }, +[1008]= {"HID", 64, HV_RW, }, +}; + +/* This covers POWER8 and POWER9 PMUs */ +static const struct spr sprs_power_common_pmu[1024] = { +[768] = {"SIER", 64, RO, }, +[769] = {"MMCR2", 64, RW, }, +[770] = {"MMCRA", 64, RW, }, +[771] = {"PMC1", 32, RW, }, +[772] = {"PMC2", 32, RW, }, +[773] = {"PMC3", 32, RW, }, +[774] = {"PMC4", 32, RW, }, +[775] = {"PMC5", 32, RW, }, +[776] = {"PMC6", 32, RW, }, +[779] = {"MMCR0", 64, RW, }, +[780] = {"SIAR", 64, RO, }, +[781] = {"SDAR", 64, RO, }, +[782] = {"MMCR1", 64, RO, }, +[784] = {"SIER", 64, OS_RW, }, +[785] = {"MMCR2", 64, OS_RW, }, +[786] = {"MMCRA", 64, OS_RW, }, +[787] = {"PMC1", 32, OS_RW, }, +[788] = {"PMC2", 32, OS_RW, }, +[789] = {"PMC3", 32, OS_RW, }, +[790] = {"PMC4", 32, OS_RW, }, +[791] = {"PMC5", 32, OS_RW, }, +[792] = {"PMC6", 32, OS_RW, }, +[795] = {"MMCR0", 64, OS_RW, }, +[796] = {"SIAR", 64, OS_RW, }, +[797] = {"SDAR", 64, OS_RW, }, +[798] = {"MMCR1", 64, OS_RW, }, +}; + +static const struct spr sprs_power10_pmu[1024] = { +[736] = {"SEIR2", 64, RO, }, +[737] = {"SEIR3", 64, RO, }, +[738] = {"MMCR3", 64, RO, }, +[752] = {"SEIR2", 64, OS_RW, }, +[753] = {"SEIR3", 64, OS_RW, }, +[754] = {"MMCR3", 64, OS_RW, }, +}; + +static struct spr sprs[1024]; + +static void setup_sprs(void) { uint32_t pvr = mfspr(287); /* Processor Version Register */ + int i; - set_sprs_common(val); + for (i = 0; i < 1024; i++) { + if (sprs_common[i].name) { + memcpy(&sprs[i], &sprs_common[i], sizeof(struct spr)); + } + } switch (pvr >> 16) { case 0x39: /* PPC970 */ case 0x3C: /* PPC970FX */ case 0x44: /* PPC970MP */ - set_sprs_book3s_201(val); + for (i = 0; i < 1024; i++) { + if (sprs_power_common[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr)); + } + if (sprs_201[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_201[i], sizeof(struct spr)); + } + if (sprs_970_pmu[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr)); + } + } break; + case 0x4b: /* POWER8E */ case 0x4c: /* POWER8NVL */ case 0x4d: /* POWER8 */ - set_sprs_book3s_207(val); + for (i = 0; i < 1024; i++) { + if (sprs_power_common[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr)); + } + if (sprs_207[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_207[i], sizeof(struct spr)); + } + if (sprs_tm[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_tm[i], sizeof(struct spr)); + } + if (sprs_power_common_pmu[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr)); + } + } break; + case 0x4e: /* POWER9 */ - set_sprs_book3s_300(val); + for (i = 0; i < 1024; i++) { + if (sprs_power_common[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr)); + } + if (sprs_300[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_300[i], sizeof(struct spr)); + } + if (sprs_tm[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_tm[i], sizeof(struct spr)); + } + if (sprs_power9_10[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power9_10[i], sizeof(struct spr)); + } + if (sprs_power_common_pmu[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr)); + } + } break; - case 0x80: /* POWER10 */ - set_sprs_book3s_31(val); + + case 0x80: /* POWER10 */ + for (i = 0; i < 1024; i++) { + if (sprs_power_common[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power_common[i], sizeof(struct spr)); + } + if (sprs_31[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_31[i], sizeof(struct spr)); + } + if (sprs_power9_10[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power9_10[i], sizeof(struct spr)); + } + if (sprs_power_common_pmu[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power_common_pmu[i], sizeof(struct spr)); + } + if (sprs_power10_pmu[i].name) { + assert(!sprs[i].name); + memcpy(&sprs[i], &sprs_power10_pmu[i], sizeof(struct spr)); + } + } break; + default: - puts("Warning: Unknown processor version!\n"); + memcpy(sprs, sprs_common, sizeof(sprs)); + puts("Warning: Unknown processor version, falling back to common SPRs!\n"); + break; } } -static void get_sprs_common(uint64_t *v) -{ - v[9] = mfspr(9); /* CTR */ - // v[273] = mfspr(273); /* SPRG1 */ /* Used by our exception handler */ - v[274] = mfspr(274); /* SPRG2 */ - v[275] = mfspr(275); /* SPRG3 */ -} - -static void get_sprs_book3s_201(uint64_t *v) -{ - v[18] = mfspr(18); /* DSISR */ - v[19] = mfspr(19); /* DAR */ - v[136] = mfspr(136); /* CTRL */ - v[256] = mfspr(256); /* VRSAVE */ - v[786] = mfspr(786); /* MMCRA */ - v[795] = mfspr(795); /* MMCR0 */ - v[798] = mfspr(798); /* MMCR1 */ -} - -static void get_sprs_book3s_207(uint64_t *v) -{ - v[3] = mfspr(3); /* DSCR */ - v[13] = mfspr(13); /* AMR */ - v[17] = mfspr(17); /* DSCR */ - v[18] = mfspr(18); /* DSISR */ - v[19] = mfspr(19); /* DAR */ - v[29] = mfspr(29); /* AMR */ - v[61] = mfspr(61); /* IAMR */ - // v[136] = mfspr(136); /* CTRL */ /* TODO: Needs a fix in KVM */ - v[153] = mfspr(153); /* FSCR */ - v[157] = mfspr(157); /* UAMOR */ - v[159] = mfspr(159); /* PSPB */ - v[256] = mfspr(256); /* VRSAVE */ - v[259] = mfspr(259); /* SPRG3 (read only) */ - // v[272] = mfspr(272); /* SPRG0 */ /* Used by our exception handler */ - v[769] = mfspr(769); /* MMCR2 */ - v[770] = mfspr(770); /* MMCRA */ - v[771] = mfspr(771); /* PMC1 */ - v[772] = mfspr(772); /* PMC2 */ - v[773] = mfspr(773); /* PMC3 */ - v[774] = mfspr(774); /* PMC4 */ - v[775] = mfspr(775); /* PMC5 */ - v[776] = mfspr(776); /* PMC6 */ - v[779] = mfspr(779); /* MMCR0 */ - v[780] = mfspr(780); /* SIAR (read only) */ - v[781] = mfspr(781); /* SDAR (read only) */ - v[782] = mfspr(782); /* MMCR1 (read only) */ - v[784] = mfspr(784); /* SIER */ - v[785] = mfspr(785); /* MMCR2 */ - v[786] = mfspr(786); /* MMCRA */ - v[787] = mfspr(787); /* PMC1 */ - v[788] = mfspr(788); /* PMC2 */ - v[789] = mfspr(789); /* PMC3 */ - v[790] = mfspr(790); /* PMC4 */ - v[791] = mfspr(791); /* PMC5 */ - v[792] = mfspr(792); /* PMC6 */ - v[795] = mfspr(795); /* MMCR0 */ - v[796] = mfspr(796); /* SIAR */ - v[797] = mfspr(797); /* SDAR */ - v[798] = mfspr(798); /* MMCR1 */ - v[800] = mfspr(800); /* BESCRS */ - v[801] = mfspr(801); /* BESCCRSU */ - v[802] = mfspr(802); /* BESCRR */ - v[803] = mfspr(803); /* BESCRRU */ - v[804] = mfspr(804); /* EBBHR */ - v[805] = mfspr(805); /* EBBRR */ - v[806] = mfspr(806); /* BESCR */ - v[815] = mfspr(815); /* TAR */ -} - -static void get_sprs_book3s_300(uint64_t *v) +static void get_sprs(uint64_t *v) { - get_sprs_book3s_207(v); - v[48] = mfspr(48); /* PIDR */ - v[144] = mfspr(144); /* TIDR */ - v[823] = mfspr(823); /* PSSCR */ -} + int i; -static void get_sprs_book3s_31(uint64_t *v) -{ - get_sprs_book3s_207(v); - v[48] = mfspr(48); /* PIDR */ - v[823] = mfspr(823); /* PSSCR */ + for (i = 0; i < 1024; i++) { + if (!(sprs[i].access & SPR_OS_READ)) + continue; + v[i] = __mfspr(i); + } } -static void get_sprs(uint64_t *v) +static void set_sprs(uint64_t val) { - uint32_t pvr = mfspr(287); /* Processor Version Register */ - - get_sprs_common(v); + int i; - switch (pvr >> 16) { - case 0x39: /* PPC970 */ - case 0x3C: /* PPC970FX */ - case 0x44: /* PPC970MP */ - get_sprs_book3s_201(v); - break; - case 0x4b: /* POWER8E */ - case 0x4c: /* POWER8NVL */ - case 0x4d: /* POWER8 */ - get_sprs_book3s_207(v); - break; - case 0x4e: /* POWER9 */ - get_sprs_book3s_300(v); - break; - case 0x80: /* POWER10 */ - get_sprs_book3s_31(v); - break; + for (i = 0; i < 1024; i++) { + if (!(sprs[i].access & SPR_OS_WRITE)) + continue; + if (sprs[i].type & SPR_HARNESS) + continue; + if (!strcmp(sprs[i].name, "MMCR0")) { + /* XXX: could use a comment or better abstraction! */ + __mtspr(i, (val & 0xfffffffffbab3fffULL) | 0xfa0b2070); + } else { + __mtspr(i, val); + } } } @@ -289,7 +523,9 @@ int main(int argc, char **argv) } } - printf("Settings SPRs to %#lx...\n", pat); + setup_sprs(); + + printf("Setting SPRs to 0x%lx...\n", pat); set_sprs(pat); memset(before, 0, sizeof(before)); @@ -301,16 +537,37 @@ int main(int argc, char **argv) migrate_once(); } else { msleep(2000); + + /* Taking a dec updates SRR0, SRR1, SPRG1, so don't fail. */ + sprs[26].type |= SPR_ASYNC; + sprs[27].type |= SPR_ASYNC; + sprs[273].type |= SPR_ASYNC; } get_sprs(after); puts("Checking SPRs...\n"); for (i = 0; i < 1024; i++) { - if (before[i] != 0 || after[i] != 0) - report(before[i] == after[i], - "SPR %d:\t%#018lx <==> %#018lx", i, before[i], - after[i]); + bool pass = true; + + if (!(sprs[i].access & SPR_OS_READ)) + continue; + + if (sprs[i].width == 32) { + if (before[i] >> 32) + pass = false; + } + if (!(sprs[i].type & SPR_ASYNC) && (before[i] != after[i])) + pass = false; + + if (sprs[i].width == 32 && !(before[i] >> 32) && !(after[i] >> 32)) + report(pass, "%-10s(%4d):\t 0x%08lx <==> 0x%08lx", + sprs[i].name, i, + before[i], after[i]); + else + report(pass, "%-10s(%4d):\t0x%016lx <==> 0x%016lx", + sprs[i].name, i, + before[i], after[i]); } return report_summary(); From patchwork Thu Jun 8 07:58:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D6F3C7EE29 for ; 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Thu, 08 Jun 2023 00:59:03 -0700 (PDT) Received: from wheely.local0.net ([1.146.34.117]) by smtp.gmail.com with ESMTPSA id 17-20020a630011000000b00542d7720a6fsm673182pga.88.2023.06.08.00.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 00:59:02 -0700 (PDT) From: Nicholas Piggin To: kvm@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Laurent Vivier , Thomas Huth Subject: [kvm-unit-tests v4 07/12] powerpc/spapr_vpa: Add basic VPA tests Date: Thu, 8 Jun 2023 17:58:21 +1000 Message-Id: <20230608075826.86217-8-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608075826.86217-1-npiggin@gmail.com> References: <20230608075826.86217-1-npiggin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The VPA is an optional memory structure shared between the hypervisor and operating system, defined by PAPR. This test defines the structure and adds registration, deregistration, and a few simple sanity tests. [Thanks to Thomas Huth for suggesting many of the test cases.] Reviewed-by: Thomas Huth Signed-off-by: Nicholas Piggin --- lib/powerpc/asm/hcall.h | 1 + lib/ppc64/asm/vpa.h | 62 +++++++++++++++ powerpc/Makefile.ppc64 | 2 +- powerpc/spapr_vpa.c | 172 ++++++++++++++++++++++++++++++++++++++++ powerpc/unittests.cfg | 3 + 5 files changed, 239 insertions(+), 1 deletion(-) create mode 100644 lib/ppc64/asm/vpa.h create mode 100644 powerpc/spapr_vpa.c diff --git a/lib/powerpc/asm/hcall.h b/lib/powerpc/asm/hcall.h index 1173feaa..e0f5009e 100644 --- a/lib/powerpc/asm/hcall.h +++ b/lib/powerpc/asm/hcall.h @@ -18,6 +18,7 @@ #define H_SET_SPRG0 0x24 #define H_SET_DABR 0x28 #define H_PAGE_INIT 0x2c +#define H_REGISTER_VPA 0xDC #define H_CEDE 0xE0 #define H_GET_TERM_CHAR 0x54 #define H_PUT_TERM_CHAR 0x58 diff --git a/lib/ppc64/asm/vpa.h b/lib/ppc64/asm/vpa.h new file mode 100644 index 00000000..11dde018 --- /dev/null +++ b/lib/ppc64/asm/vpa.h @@ -0,0 +1,62 @@ +#ifndef _ASMPOWERPC_VPA_H_ +#define _ASMPOWERPC_VPA_H_ +/* + * This work is licensed under the terms of the GNU LGPL, version 2. + */ + +#ifndef __ASSEMBLY__ + +struct vpa { + uint32_t descriptor; + uint16_t size; + uint8_t reserved1[3]; + uint8_t status; + uint8_t reserved2[14]; + uint32_t fru_node_id; + uint32_t fru_proc_id; + uint8_t reserved3[56]; + uint8_t vhpn_change_counters[8]; + uint8_t reserved4[80]; + uint8_t cede_latency; + uint8_t maintain_ebb; + uint8_t reserved5[6]; + uint8_t dtl_enable_mask; + uint8_t dedicated_cpu_donate; + uint8_t maintain_fpr; + uint8_t maintain_pmc; + uint8_t reserved6[28]; + uint64_t idle_estimate_purr; + uint8_t reserved7[28]; + uint16_t maintain_nr_slb; + uint8_t idle; + uint8_t maintain_vmx; + uint32_t vp_dispatch_count; + uint32_t vp_dispatch_dispersion; + uint64_t vp_fault_count; + uint64_t vp_fault_tb; + uint64_t purr_exprop_idle; + uint64_t spurr_exprop_idle; + uint64_t purr_exprop_busy; + uint64_t spurr_exprop_busy; + uint64_t purr_donate_idle; + uint64_t spurr_donate_idle; + uint64_t purr_donate_busy; + uint64_t spurr_donate_busy; + uint64_t vp_wait3_tb; + uint64_t vp_wait2_tb; + uint64_t vp_wait1_tb; + uint64_t purr_exprop_adjunct_busy; + uint64_t spurr_exprop_adjunct_busy; + uint32_t supervisor_pagein_count; + uint8_t reserved8[4]; + uint64_t purr_exprop_adjunct_idle; + uint64_t spurr_exprop_adjunct_idle; + uint64_t adjunct_insns_executed; + uint8_t reserved9[120]; + uint64_t dtl_index; + uint8_t reserved10[96]; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASMPOWERPC_VPA_H_ */ diff --git a/powerpc/Makefile.ppc64 b/powerpc/Makefile.ppc64 index ea684470..b0ed2b10 100644 --- a/powerpc/Makefile.ppc64 +++ b/powerpc/Makefile.ppc64 @@ -19,7 +19,7 @@ reloc.o = $(TEST_DIR)/reloc64.o OBJDIRS += lib/ppc64 # ppc64 specific tests -tests = +tests = $(TEST_DIR)/spapr_vpa.elf include $(SRCDIR)/$(TEST_DIR)/Makefile.common diff --git a/powerpc/spapr_vpa.c b/powerpc/spapr_vpa.c new file mode 100644 index 00000000..5586eb8d --- /dev/null +++ b/powerpc/spapr_vpa.c @@ -0,0 +1,172 @@ +/* + * Test sPAPR "Per Virtual Processor Area" and H_REGISTER_VPA hypervisor call + * (also known as VPA, also known as lppaca in the Linux pseries kernel). + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* for endian accessors */ + +static int verbose; + +static void print_vpa(struct vpa *vpa) +{ + printf("VPA\n"); + printf("descriptor: 0x%08x\n", be32_to_cpu(vpa->descriptor)); + printf("size: 0x%04x\n", be16_to_cpu(vpa->size)); + printf("status: 0x%02x\n", vpa->status); + printf("fru_node_id: 0x%08x\n", be32_to_cpu(vpa->fru_node_id)); + printf("fru_proc_id: 0x%08x\n", be32_to_cpu(vpa->fru_proc_id)); + printf("vhpn_change_counters: 0x%02x %02x %02x %02x %02x %02x %02x %02x\n", vpa->vhpn_change_counters[0], vpa->vhpn_change_counters[1], vpa->vhpn_change_counters[2], vpa->vhpn_change_counters[3], vpa->vhpn_change_counters[4], vpa->vhpn_change_counters[5], vpa->vhpn_change_counters[6], vpa->vhpn_change_counters[7]); + printf("vp_dispatch_count: 0x%08x\n", be32_to_cpu(vpa->vp_dispatch_count)); + printf("vp_dispatch_dispersion: 0x%08x\n", be32_to_cpu(vpa->vp_dispatch_dispersion)); + printf("vp_fault_count: 0x%08lx\n", be64_to_cpu(vpa->vp_fault_count)); + printf("vp_fault_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_fault_tb)); + printf("purr_exprop_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_idle)); + printf("spurr_exprop_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_idle)); + printf("purr_exprop_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_busy)); + printf("spurr_exprop_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_busy)); + printf("purr_donate_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_donate_idle)); + printf("spurr_donate_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_donate_idle)); + printf("purr_donate_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_donate_busy)); + printf("spurr_donate_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_donate_busy)); + printf("vp_wait3_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait3_tb)); + printf("vp_wait2_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait2_tb)); + printf("vp_wait1_tb: 0x%08lx\n", be64_to_cpu(vpa->vp_wait1_tb)); + printf("purr_exprop_adjunct_busy: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_adjunct_busy)); + printf("spurr_exprop_adjunct_busy: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_adjunct_busy)); + printf("purr_exprop_adjunct_idle: 0x%08lx\n", be64_to_cpu(vpa->purr_exprop_adjunct_idle)); + printf("spurr_exprop_adjunct_idle: 0x%08lx\n", be64_to_cpu(vpa->spurr_exprop_adjunct_idle)); + printf("adjunct_insns_executed: 0x%08lx\n", be64_to_cpu(vpa->adjunct_insns_executed)); + printf("dtl_index: 0x%08lx\n", be64_to_cpu(vpa->dtl_index)); +} + +#define SUBFUNC_RESERVED (0ULL << 45) +#define SUBFUNC_REGISTER (1ULL << 45) +#define SUBFUNC_DEREGISTER (5ULL << 45) + +/** + * Test the H_REGISTER_VPA h-call register/deregister calls. + */ +static void test_register_vpa(void) +{ + struct vpa *vpa; + uint32_t cpuid = fdt_boot_cpuid_phys(dt_fdt()); + int rc; + + report_prefix_push("H_REGISTER_VPA"); + + vpa = memalign(4096, sizeof(*vpa)); + + memset(vpa, 0, sizeof(*vpa)); + + vpa->size = cpu_to_be16(sizeof(*vpa)); + + rc = hcall(H_REGISTER_VPA, SUBFUNC_RESERVED, cpuid, vpa); + report(rc == H_PARAMETER, "Reserved sub-function fails with H_PARAMETER"); + + rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, 0xbadbad, vpa); + report(rc == H_PARAMETER, "Register with invalid proc-no fails"); + + rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa + 8); + report(rc == H_PARAMETER, "Register with VPA not cacheline aligned fails"); + + + rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa + 4096 - 128); + report(rc == H_PARAMETER, "Register with VPA spanning 4096 bytes fails"); + + vpa->size = cpu_to_be16(632); + rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, (void *)vpa); + report(rc == H_PARAMETER, "Register with VPA size < 640 bytes fails"); + vpa->size = cpu_to_be16(sizeof(*vpa)); + + rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, PHYSICAL_END); + report(rc == H_PARAMETER, "Register with VPA outside guest real memory fails"); + + + rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, vpa); + report(rc == H_SUCCESS, "VPA registered"); + + rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, NULL); + report(rc == H_SUCCESS, "VPA deregistered"); + + /* + * From PAPR: "note no check is made that a valid VPA registration + * exists". + */ + rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, NULL); + report(rc == H_SUCCESS, "Deregister succeeds with no VPA registered"); + + rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, 0xbadbad, NULL); + report(rc == H_PARAMETER, "Deregister with invalid proc-no fails"); + + report_prefix_pop(); +} + +/** + * Test some VPA fields. + */ +static void test_vpa(void) +{ + struct vpa *vpa; + uint32_t cpuid = fdt_boot_cpuid_phys(dt_fdt()); + int disp_count1, disp_count2; + int rc; + + report_prefix_push("VPA"); + + vpa = memalign(4096, sizeof(*vpa)); + + memset(vpa, 0, sizeof(*vpa)); + + vpa->size = cpu_to_be16(sizeof(*vpa)); + + rc = hcall(H_REGISTER_VPA, SUBFUNC_REGISTER, cpuid, vpa); + if (rc != H_SUCCESS) { + report_skip("VPA could not be registered"); + return; + } + + if (verbose) + print_vpa(vpa); + + disp_count1 = be32_to_cpu(vpa->vp_dispatch_count); + report(disp_count1 % 2 == 0, "Dispatch count is even while running"); + msleep(100); + disp_count2 = be32_to_cpu(vpa->vp_dispatch_count); + report(disp_count1 != disp_count2, "Dispatch count increments over H_CEDE"); + + rc = hcall(H_REGISTER_VPA, SUBFUNC_DEREGISTER, cpuid, vpa); + if (rc != H_SUCCESS) + report_fail("Could not deregister after registration"); + + disp_count1 = be32_to_cpu(vpa->vp_dispatch_count); + report(disp_count1 % 2 == 1, "Dispatch count is odd after deregister"); + + report_prefix_pop(); +} + +int main(int argc, char *argv[]) +{ + int i; + + for (i = 1; i < argc; i++) { + if (strcmp(argv[i], "-v") == 0) { + verbose = 1; + } + } + + test_register_vpa(); + + test_vpa(); + + return report_summary(); +} diff --git a/powerpc/unittests.cfg b/powerpc/unittests.cfg index e206a225..dd5f361c 100644 --- a/powerpc/unittests.cfg +++ b/powerpc/unittests.cfg @@ -39,6 +39,9 @@ groups = selftest [spapr_hcall] file = spapr_hcall.elf +[spapr_vpa] +file = spapr_vpa.elf + [rtas-get-time-of-day] file = rtas.elf timeout = 5 From patchwork Thu Jun 8 07:58:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71C26C7EE23 for ; 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Thu, 08 Jun 2023 00:59:07 -0700 (PDT) Received: from wheely.local0.net ([1.146.34.117]) by smtp.gmail.com with ESMTPSA id 17-20020a630011000000b00542d7720a6fsm673182pga.88.2023.06.08.00.59.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 00:59:06 -0700 (PDT) From: Nicholas Piggin To: kvm@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Laurent Vivier , Thomas Huth Subject: [kvm-unit-tests v4 08/12] powerpc: Expand exception handler vector granularity Date: Thu, 8 Jun 2023 17:58:22 +1000 Message-Id: <20230608075826.86217-9-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608075826.86217-1-npiggin@gmail.com> References: <20230608075826.86217-1-npiggin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Exception handlers are currently indexed in units of 0x100, but powerpc can have vectors that are aligned to as little as 0x20 bytes. Increase granularity of the handler functions before adding support for those vectors. Signed-off-by: Nicholas Piggin --- Since v3: - Fix typo [Thomas] lib/powerpc/processor.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c index aaf45b68..64d7ae01 100644 --- a/lib/powerpc/processor.c +++ b/lib/powerpc/processor.c @@ -16,19 +16,25 @@ static struct { void (*func)(struct pt_regs *, void *data); void *data; -} handlers[16]; +} handlers[128]; +/* + * Exception handlers span from 0x100 to 0x1000 and can have a granularity + * of 0x20 bytes in some cases. Indexing spans 0-0x1000 with 0x20 increments + * resulting in 128 slots. + */ void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void * data) { - assert(!(trap & ~0xf00)); + assert(!(trap & ~0xfe0)); - trap >>= 8; + trap >>= 5; if (func && handlers[trap].func) { printf("exception handler installed twice %#x\n", trap); abort(); } + handlers[trap].func = func; handlers[trap].data = data; } @@ -37,9 +43,9 @@ void do_handle_exception(struct pt_regs *regs) { unsigned char v; - v = regs->trap >> 8; + v = regs->trap >> 5; - if (v < 16 && handlers[v].func) { + if (v < 128 && handlers[v].func) { handlers[v].func(regs, handlers[v].data); return; } From patchwork Thu Jun 8 07:58:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0516AC7EE2E for ; Thu, 8 Jun 2023 07:59:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233680AbjFHH7b (ORCPT ); Thu, 8 Jun 2023 03:59:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232164AbjFHH73 (ORCPT ); Thu, 8 Jun 2023 03:59:29 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E49CE26AC for ; Thu, 8 Jun 2023 00:59:12 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-650c8cb68aeso133540b3a.3 for ; Thu, 08 Jun 2023 00:59:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686211150; x=1688803150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mDS1ZqNe46iVTWhss4bYT0AM3F6nP4Ljt86rnC65yFU=; b=swgYATDFtVxRXbCrZ6sfBsvPr7JsC9QKv/gPSKaGFHJup7RwzVfOgUa24YMr348IN2 hEg6tizvdu6j8ouoYGCxpaQUBXYx2ra5k6jFAt+BO8PO2dGnNzG6aeiKP+3R+3KUHYvC VxYeMsvddYrsgGk5ViBmm2nni5mJbXQ9tFjFc9q1NcVbpTeIB3py4VcomWGdpGJINgha FR5M0H2B0EFnUSFCeDP6+uh8evcp9d+mNEkMBsSNpv1zycWlNlK/lXWh5Q4u5jvtDcKc +sqp6oDVTzFBfke9sSjb200B8qkEw+TeweyRp7k93CWINYSDp88Mpkqara2Phbu0t2IU hPBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686211150; x=1688803150; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mDS1ZqNe46iVTWhss4bYT0AM3F6nP4Ljt86rnC65yFU=; b=NPmjGDas2POHyJKV3ODWy7YiX6LXijPZW6gx+ifW5t6pgmF321r7Gr7eZUStZcy7oe 9ycQmR/UiMOAhFg17LN+2yGKIFgXxL3f9XC8l3IEDqOuLPmMecpya1USMJtAki+m78Xj JDOI0PhOLMu27w/vXdXG4yq+WNv6fi06aLBOSRkfAkIVi9bJxENmkE9v+ejjIvOJhDNi d4JdIMwsmH2e98bSJZT0ZhoUKDTps3hOLxxhFq9Mlp7bhuIQpZpXwQHw4PLQ6k4beRQF 9IOf/QV2uKWdY/AyvDZn47cKW2oTjx90uxUIN2YJkLFCjPl/HbtWq4F4iiWQokyQTgdX /kww== X-Gm-Message-State: AC+VfDzIB726I6rLOQ7zmscSQosWLWznPXckEOoZvkcbSQ3MLCP+lkX7 6KchfK8Ansh18XQxkis2Na+OkQ2SvHY= X-Google-Smtp-Source: ACHHUZ7bdMgOGbWdGi6/8pyWj3tH1+xk3V4UrVjhD/lMxg9d6oYh4A38PoSHkdANOG86yLgGuiLQBA== X-Received: by 2002:a05:6a20:3944:b0:104:4c7d:25f8 with SMTP id r4-20020a056a20394400b001044c7d25f8mr3440432pzg.3.1686211150512; Thu, 08 Jun 2023 00:59:10 -0700 (PDT) Received: from wheely.local0.net ([1.146.34.117]) by smtp.gmail.com with ESMTPSA id 17-20020a630011000000b00542d7720a6fsm673182pga.88.2023.06.08.00.59.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 00:59:09 -0700 (PDT) From: Nicholas Piggin To: kvm@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Laurent Vivier , Thomas Huth Subject: [kvm-unit-tests v4 09/12] powerpc: Add support for more interrupts including HV interrupts Date: Thu, 8 Jun 2023 17:58:23 +1000 Message-Id: <20230608075826.86217-10-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608075826.86217-1-npiggin@gmail.com> References: <20230608075826.86217-1-npiggin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Interrupt vectors were not being populated for all architected interrupt types, which could lead to crashes rather than a message for unhandled interrupts. 0x20 sized vectors require some reworking of the code to fit. This also adds support for HV / HSRR type interrupts which will be used in a later change. Acked-by: Thomas Huth Signed-off-by: Nicholas Piggin --- Since v3: - Build fix [Joel] lib/powerpc/asm/ppc_asm.h | 3 ++ powerpc/cstart64.S | 79 ++++++++++++++++++++++++++++++++------- 2 files changed, 68 insertions(+), 14 deletions(-) diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h index 6299ff53..46b4be00 100644 --- a/lib/powerpc/asm/ppc_asm.h +++ b/lib/powerpc/asm/ppc_asm.h @@ -35,6 +35,9 @@ #endif /* __BYTE_ORDER__ */ +#define SPR_HSRR0 0x13A +#define SPR_HSRR1 0x13B + /* Machine State Register definitions: */ #define MSR_EE_BIT 15 /* External Interrupts Enable */ #define MSR_SF_BIT 63 /* 64-bit mode */ diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S index 34e39341..b7514100 100644 --- a/powerpc/cstart64.S +++ b/powerpc/cstart64.S @@ -184,14 +184,6 @@ call_handler: mfcr r0 std r0,_CCR(r1) - /* nip and msr */ - - mfsrr0 r0 - std r0, _NIP(r1) - - mfsrr1 r0 - std r0, _MSR(r1) - /* restore TOC pointer */ LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR) @@ -238,6 +230,7 @@ call_handler: .section .text.ex +/* [H]VECTOR must not be more than 8 instructions to fit in 0x20 vectors */ .macro VECTOR vec . = \vec @@ -246,19 +239,28 @@ call_handler: subi r1,r1, INT_FRAME_SIZE /* save r0 and ctr to call generic handler */ - SAVE_GPR(0,r1) - mfctr r0 - std r0,_CTR(r1) + li r0,\vec + std r0,_TRAP(r1) - ld r0, P_HANDLER(0) - mtctr r0 + b handler_trampoline +.endm + +.macro HVECTOR vec + . = \vec + + mtsprg1 r1 /* save r1 */ + mfsprg0 r1 /* get exception stack address */ + subi r1,r1, INT_FRAME_SIZE + + /* save r0 and ctr to call generic handler */ + SAVE_GPR(0,r1) li r0,\vec std r0,_TRAP(r1) - bctr + b handler_htrampoline .endm . = 0x100 @@ -268,12 +270,61 @@ __start_interrupts: VECTOR(0x100) VECTOR(0x200) VECTOR(0x300) +VECTOR(0x380) VECTOR(0x400) +VECTOR(0x480) VECTOR(0x500) VECTOR(0x600) VECTOR(0x700) VECTOR(0x800) VECTOR(0x900) +HVECTOR(0x980) +VECTOR(0xa00) +VECTOR(0xc00) +VECTOR(0xd00) +HVECTOR(0xe00) +HVECTOR(0xe20) +HVECTOR(0xe40) +HVECTOR(0xe60) +HVECTOR(0xe80) +HVECTOR(0xea0) +VECTOR(0xf00) +VECTOR(0xf20) +VECTOR(0xf40) +VECTOR(0xf60) +HVECTOR(0xf80) + +handler_trampoline: + mfctr r0 + std r0,_CTR(r1) + + ld r0, P_HANDLER(0) + mtctr r0 + + /* nip and msr */ + mfsrr0 r0 + std r0, _NIP(r1) + + mfsrr1 r0 + std r0, _MSR(r1) + + bctr + +handler_htrampoline: + mfctr r0 + std r0,_CTR(r1) + + ld r0, P_HANDLER(0) + mtctr r0 + + /* nip and msr */ + mfspr r0, SPR_HSRR0 + std r0, _NIP(r1) + + mfspr r0, SPR_HSRR1 + std r0, _MSR(r1) + + bctr .align 7 .globl __end_interrupts From patchwork Thu Jun 8 07:58:24 2023 Content-Type: text/plain; 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Acked-by: Thomas Huth Signed-off-by: Nicholas Piggin --- powerpc/cstart64.S | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S index b7514100..e18ae9a2 100644 --- a/powerpc/cstart64.S +++ b/powerpc/cstart64.S @@ -33,9 +33,14 @@ start: * We were loaded at QEMU's kernel load address, but we're not * allowed to link there due to how QEMU deals with linker VMAs, * so we just linked at zero. This means the first thing to do is - * to find our stack and toc, and then do a relocate. + * to find our stack and toc, and then do a relocate. powernv and + * pseries load addresses are not the same, so find the address + * dynamically: */ - LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR) + bl 0f +0: mflr r31 + subi r31, r31, 0b - start /* QEMU's kernel load address */ + ld r1, (p_stack - start)(r31) ld r2, (p_toc - start)(r31) add r1, r1, r31 @@ -114,8 +119,11 @@ p_toc: .llong tocptr p_dyn: .llong dynamic_start .text +start_text: .align 3 +p_toc_text: .llong tocptr +.align 3 .globl hcall hcall: sc 1 @@ -185,9 +193,10 @@ call_handler: std r0,_CCR(r1) /* restore TOC pointer */ - - LOAD_REG_IMMEDIATE(r31, SPAPR_KERNEL_LOAD_ADDR) - ld r2, (p_toc - start)(r31) + bl 0f +0: mflr r31 + subi r31, r31, 0b - start_text + ld r2, (p_toc_text - start_text)(r31) /* FIXME: build stack frame */ From patchwork Thu Jun 8 07:58:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A47BC7EE2E for ; Thu, 8 Jun 2023 08:00:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234123AbjFHIAF (ORCPT ); Thu, 8 Jun 2023 04:00:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234070AbjFHH7q (ORCPT ); Thu, 8 Jun 2023 03:59:46 -0400 Received: from mail-qt1-x82c.google.com (mail-qt1-x82c.google.com [IPv6:2607:f8b0:4864:20::82c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 902C52139 for ; Thu, 8 Jun 2023 00:59:23 -0700 (PDT) Received: by mail-qt1-x82c.google.com with SMTP id d75a77b69052e-3f9baa69682so3091111cf.3 for ; Thu, 08 Jun 2023 00:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686211159; x=1688803159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l7rOGqXC37gafOauEwa0cFMpL8/CjScf7tEvGqgJo8o=; b=rfwHuFdRzuVr3mppnWLIdGnUEfW/ROFYDxVVAaVFXYspZT/EMsu8z331uOagMlXrrJ OscjyYJCrcxJUXflpUnpyKB9qSNkZSgnR+AhrULdQ3vJATnJPCrhawIH+NwZZMU+Hogc MFqJ8zcaj8OdbBB51uRWeVWQajFzl3MU+pfCz/9tYomBEmiKvjws5uyfpUDJXrIGE8Ne QwS9v/Q4mlaFFHcVgyJvx48c/T7lcnXRaXlYElPFjbUfBpoPKBkqs4hZwNk9fwCZ6/sr w3wu0uIFQrSxeHRZqKUiuPiCQsmcOn7eRPzkTi10XNq15hcqMGYMx5cgWnyDPZZrUeAl FEXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686211159; x=1688803159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l7rOGqXC37gafOauEwa0cFMpL8/CjScf7tEvGqgJo8o=; b=hFRokeQpbdhHxxkIOj+qjlyGwEXma6kPKaeqJcVgr1NyVy15Fwyh+ztEdVCd73D/sS tp3qAsAwbNOZ0bl2e7tn71fAQliuKmKWM1xiQ5GFiwD03Cye6YNv2bUZ0zLPLR8qDWR3 lE/U/OcOz/AMJm7ICrU/HH5Vf/qmUBKXAWzlf3kd+gHpJPMp4mcVTno8OixglIna67kv NwWCL3zEzQcdyt8U3p1OaBgXJVvqNseEnXTd4WZcg0CoNi6jQIjg4BaeQ8wuNb3YPQKd UPRM/9GMb7EwowD0ETXcp2Wm9hV66WLNfi2wv/Ialkx4pbZYs3RFbJ8cSvaU+QjWL8oS GXbw== X-Gm-Message-State: AC+VfDzYQlRuuxlGoZI8PAUqb5uIhGtMavO+NJQMTeG72ASezIWDgwm6 0whIfszR+L2SsJlMUu63f/S2y4C/7QI= X-Google-Smtp-Source: ACHHUZ4j8hBP4dC23PNbC/OKxYRz34uWel4HlrIonxyuc5wJwjuoLHdQeFkH0csrz9N44+pI2OPrzA== X-Received: by 2002:ac8:5a93:0:b0:3f6:b760:f3dd with SMTP id c19-20020ac85a93000000b003f6b760f3ddmr6981840qtc.33.1686211159233; Thu, 08 Jun 2023 00:59:19 -0700 (PDT) Received: from wheely.local0.net ([1.146.34.117]) by smtp.gmail.com with ESMTPSA id 17-20020a630011000000b00542d7720a6fsm673182pga.88.2023.06.08.00.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 00:59:18 -0700 (PDT) From: Nicholas Piggin To: kvm@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Laurent Vivier , Thomas Huth , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [kvm-unit-tests v4 11/12] powerpc: Support powernv machine with QEMU TCG Date: Thu, 8 Jun 2023 17:58:25 +1000 Message-Id: <20230608075826.86217-12-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608075826.86217-1-npiggin@gmail.com> References: <20230608075826.86217-1-npiggin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This is a basic first pass at powernv support using OPAL (skiboot) firmware. The ACCEL is a bit clunky, defaulting to kvm for powernv machine, which isn't right and has to be manually overridden. It also does not yet run in the run_tests.sh batch process, more work is needed to exclude certain tests (e.g., rtas) and adjust parameters (e.g., increase memory size) to allow powernv to work. For now it can run single test cases. Reviewed-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- Since v3: - Typo fix [Thomas] lib/powerpc/asm/ppc_asm.h | 5 +++ lib/powerpc/asm/processor.h | 10 +++++ lib/powerpc/hcall.c | 4 +- lib/powerpc/io.c | 27 +++++++++++++- lib/powerpc/io.h | 6 +++ lib/powerpc/processor.c | 10 +++++ lib/powerpc/setup.c | 8 ++-- lib/ppc64/asm/opal.h | 15 ++++++++ lib/ppc64/opal-calls.S | 46 +++++++++++++++++++++++ lib/ppc64/opal.c | 74 +++++++++++++++++++++++++++++++++++++ powerpc/Makefile.ppc64 | 2 + powerpc/cstart64.S | 7 ++++ powerpc/run | 35 ++++++++++++++++-- 13 files changed, 238 insertions(+), 11 deletions(-) create mode 100644 lib/ppc64/asm/opal.h create mode 100644 lib/ppc64/opal-calls.S create mode 100644 lib/ppc64/opal.c diff --git a/lib/powerpc/asm/ppc_asm.h b/lib/powerpc/asm/ppc_asm.h index 46b4be00..63f11d13 100644 --- a/lib/powerpc/asm/ppc_asm.h +++ b/lib/powerpc/asm/ppc_asm.h @@ -39,7 +39,12 @@ #define SPR_HSRR1 0x13B /* Machine State Register definitions: */ +#define MSR_LE_BIT 0 #define MSR_EE_BIT 15 /* External Interrupts Enable */ +#define MSR_HV_BIT 60 /* Hypervisor mode */ #define MSR_SF_BIT 63 /* 64-bit mode */ +#define SPR_HSRR0 0x13A +#define SPR_HSRR1 0x13B + #endif /* _ASMPOWERPC_PPC_ASM_H */ diff --git a/lib/powerpc/asm/processor.h b/lib/powerpc/asm/processor.h index 4ad6612b..9b318c3e 100644 --- a/lib/powerpc/asm/processor.h +++ b/lib/powerpc/asm/processor.h @@ -3,6 +3,7 @@ #include #include +#include #ifndef __ASSEMBLY__ void handle_exception(int trap, void (*func)(struct pt_regs *, void *), void *); @@ -43,6 +44,15 @@ static inline void mtmsr(uint64_t msr) asm volatile ("mtmsrd %[msr]" :: [msr] "r" (msr) : "memory"); } +/* + * This returns true on PowerNV / OPAL machines which run in hypervisor + * mode. False on pseries / PAPR machines that run in guest mode. + */ +static inline bool machine_is_powernv(void) +{ + return !!(mfmsr() & (1ULL << MSR_HV_BIT)); +} + static inline uint64_t get_tb(void) { return mfspr(SPR_TB); diff --git a/lib/powerpc/hcall.c b/lib/powerpc/hcall.c index 711cb1b0..37e52f54 100644 --- a/lib/powerpc/hcall.c +++ b/lib/powerpc/hcall.c @@ -25,7 +25,7 @@ int hcall_have_broken_sc1(void) return r3 == (unsigned long)H_PRIVILEGE; } -void putchar(int c) +void papr_putchar(int c) { unsigned long vty = 0; /* 0 == default */ unsigned long nr_chars = 1; @@ -34,7 +34,7 @@ void putchar(int c) hcall(H_PUT_TERM_CHAR, vty, nr_chars, chars); } -int __getchar(void) +int __papr_getchar(void) { register unsigned long r3 asm("r3") = H_GET_TERM_CHAR; register unsigned long r4 asm("r4") = 0; /* 0 == default vty */ diff --git a/lib/powerpc/io.c b/lib/powerpc/io.c index a381688b..ab7bb843 100644 --- a/lib/powerpc/io.c +++ b/lib/powerpc/io.c @@ -9,13 +9,33 @@ #include #include #include +#include #include "io.h" static struct spinlock print_lock; +void putchar(int c) +{ + if (machine_is_powernv()) + opal_putchar(c); + else + papr_putchar(c); +} + +int __getchar(void) +{ + if (machine_is_powernv()) + return __opal_getchar(); + else + return __papr_getchar(); +} + void io_init(void) { - rtas_init(); + if (machine_is_powernv()) + assert(!opal_init()); + else + rtas_init(); } void puts(const char *s) @@ -38,7 +58,10 @@ void exit(int code) // FIXME: change this print-exit/rtas-poweroff to chr_testdev_exit(), // maybe by plugging chr-testdev into a spapr-vty. printf("\nEXIT: STATUS=%d\n", ((code) << 1) | 1); - rtas_power_off(); + if (machine_is_powernv()) + opal_power_off(); + else + rtas_power_off(); halt(code); __builtin_unreachable(); } diff --git a/lib/powerpc/io.h b/lib/powerpc/io.h index d4f21ba1..943bf142 100644 --- a/lib/powerpc/io.h +++ b/lib/powerpc/io.h @@ -8,6 +8,12 @@ #define _POWERPC_IO_H_ extern void io_init(void); +extern int opal_init(void); +extern void opal_power_off(void); extern void putchar(int c); +extern void opal_putchar(int c); +extern void papr_putchar(int c); +extern int __opal_getchar(void); +extern int __papr_getchar(void); #endif diff --git a/lib/powerpc/processor.c b/lib/powerpc/processor.c index 64d7ae01..58fea8cf 100644 --- a/lib/powerpc/processor.c +++ b/lib/powerpc/processor.c @@ -71,6 +71,16 @@ void sleep_tb(uint64_t cycles) { uint64_t start, end, now; + if (machine_is_powernv()) { + /* + * Could use 'stop' to sleep here which would be interesting. + * stop with ESL=0 should be simple enough, ESL=1 would require + * SRESET based wakeup which is more involved. + */ + delay(cycles); + return; + } + start = now = get_tb(); end = start + cycles; diff --git a/lib/powerpc/setup.c b/lib/powerpc/setup.c index 1be4c030..dd758db4 100644 --- a/lib/powerpc/setup.c +++ b/lib/powerpc/setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include "io.h" @@ -97,12 +98,13 @@ static void cpu_init(void) tb_hz = params.tb_hz; /* Interrupt Endianness */ - + if (!machine_is_powernv()) { #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ - hcall(H_SET_MODE, 1, 4, 0, 0); + hcall(H_SET_MODE, 1, 4, 0, 0); #else - hcall(H_SET_MODE, 0, 4, 0, 0); + hcall(H_SET_MODE, 0, 4, 0, 0); #endif + } } static void mem_init(phys_addr_t freemem_start) diff --git a/lib/ppc64/asm/opal.h b/lib/ppc64/asm/opal.h new file mode 100644 index 00000000..7b1299f7 --- /dev/null +++ b/lib/ppc64/asm/opal.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _ASMPPC64_HCALL_H_ +#define _ASMPPC64_HCALL_H_ + +#define OPAL_SUCCESS 0 + +#define OPAL_CONSOLE_WRITE 1 +#define OPAL_CONSOLE_READ 2 +#define OPAL_CEC_POWER_DOWN 5 +#define OPAL_POLL_EVENTS 10 +#define OPAL_REINIT_CPUS 70 +# define OPAL_REINIT_CPUS_HILE_BE (1 << 0) +# define OPAL_REINIT_CPUS_HILE_LE (1 << 1) + +#endif diff --git a/lib/ppc64/opal-calls.S b/lib/ppc64/opal-calls.S new file mode 100644 index 00000000..1833358c --- /dev/null +++ b/lib/ppc64/opal-calls.S @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2016 IBM Corporation. + */ + +#include + + .text + .globl opal_call +opal_call: + mr r0,r3 + mr r3,r4 + mr r4,r5 + mr r5,r6 + mr r6,r7 + mflr r11 + std r11,16(r1) + mfcr r12 + stw r12,8(r1) + mr r13,r2 + + /* Set opal return address */ + LOAD_REG_ADDR(r11, opal_return) + mtlr r11 + mfmsr r12 + + /* switch to BE when we enter OPAL */ + li r11,(1 << MSR_LE_BIT) + andc r12,r12,r11 + mtspr SPR_HSRR1,r12 + + /* load the opal call entry point and base */ + LOAD_REG_ADDR(r11, opal) + ld r12,8(r11) + ld r2,0(r11) + mtspr SPR_HSRR0,r12 + hrfid + +opal_return: + FIXUP_ENDIAN + mr r2,r13; + lwz r11,8(r1); + ld r12,16(r1) + mtcr r11; + mtlr r12 + blr diff --git a/lib/ppc64/opal.c b/lib/ppc64/opal.c new file mode 100644 index 00000000..84ab97b8 --- /dev/null +++ b/lib/ppc64/opal.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * OPAL call helpers + */ +#include +#include +#include +#include +#include +#include "../powerpc/io.h" + +struct opal { + uint64_t base; + uint64_t entry; +} opal; + +extern int64_t opal_call(int64_t token, int64_t arg1, int64_t arg2, int64_t arg3); + +int opal_init(void) +{ + const struct fdt_property *prop; + int node, len; + + node = fdt_path_offset(dt_fdt(), "/ibm,opal"); + if (node < 0) + return -1; + + prop = fdt_get_property(dt_fdt(), node, "opal-base-address", &len); + if (!prop) + return -1; + opal.base = fdt64_to_cpu(*(uint64_t *)prop->data); + + prop = fdt_get_property(dt_fdt(), node, "opal-entry-address", &len); + if (!prop) + return -1; + opal.entry = fdt64_to_cpu(*(uint64_t *)prop->data); + +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + if (opal_call(OPAL_REINIT_CPUS, OPAL_REINIT_CPUS_HILE_LE, 0, 0) != OPAL_SUCCESS) + return -1; +#endif + + return 0; +} + +extern void opal_power_off(void) +{ + opal_call(OPAL_CEC_POWER_DOWN, 0, 0, 0); + while (true) + opal_call(OPAL_POLL_EVENTS, 0, 0, 0); +} + +void opal_putchar(int c) +{ + unsigned long vty = 0; /* 0 == default */ + unsigned long nr_chars = cpu_to_be64(1); + char ch = c; + + opal_call(OPAL_CONSOLE_WRITE, (int64_t)vty, (int64_t)&nr_chars, (int64_t)&ch); +} + +int __opal_getchar(void) +{ + unsigned long vty = 0; /* 0 == default */ + unsigned long nr_chars = cpu_to_be64(1); + char ch; + int rc; + + rc = opal_call(OPAL_CONSOLE_READ, (int64_t)vty, (int64_t)&nr_chars, (int64_t)&ch); + if (rc != OPAL_SUCCESS) + return -1; + + return ch; +} diff --git a/powerpc/Makefile.ppc64 b/powerpc/Makefile.ppc64 index b0ed2b10..06a7cf67 100644 --- a/powerpc/Makefile.ppc64 +++ b/powerpc/Makefile.ppc64 @@ -17,6 +17,8 @@ cstart.o = $(TEST_DIR)/cstart64.o reloc.o = $(TEST_DIR)/reloc64.o OBJDIRS += lib/ppc64 +cflatobjs += lib/ppc64/opal.o +cflatobjs += lib/ppc64/opal-calls.o # ppc64 specific tests tests = $(TEST_DIR)/spapr_vpa.elf diff --git a/powerpc/cstart64.S b/powerpc/cstart64.S index e18ae9a2..185ebad5 100644 --- a/powerpc/cstart64.S +++ b/powerpc/cstart64.S @@ -92,6 +92,13 @@ start: sync isync + /* powernv machine does not check broken_sc1 */ + mfmsr r3 + li r4,1 + sldi r4,r4,MSR_HV_BIT + and. r3,r3,r4 + bne 1f + /* patch sc1 if needed */ bl hcall_have_broken_sc1 cmpwi r3, 0 diff --git a/powerpc/run b/powerpc/run index ee38e075..f4ddd39c 100755 --- a/powerpc/run +++ b/powerpc/run @@ -1,5 +1,14 @@ #!/usr/bin/env bash +get_qemu_machine () +{ + if [ "$MACHINE" ]; then + echo $MACHINE + else + echo pseries + fi +} + if [ -z "$KUT_STANDALONE" ]; then if [ ! -f config.mak ]; then echo "run ./configure && make first. See ./configure -h" @@ -12,17 +21,35 @@ fi ACCEL=$(get_qemu_accelerator) || exit $? +MACHINE=$(get_qemu_machine) || + exit $? + +if [[ "$MACHINE" == "powernv"* ]] && [ "$ACCEL" = "kvm" ]; then + echo "PowerNV machine does not support KVM. ACCEL=tcg must be specified." + exit 2 +fi + qemu=$(search_qemu_binary) || exit $? -if ! $qemu -machine '?' 2>&1 | grep 'pseries' > /dev/null; then - echo "$qemu doesn't support pSeries ('-machine pseries'). Exiting." +if ! $qemu -machine '?' 2>&1 | grep $MACHINE > /dev/null; then + echo "$qemu doesn't support '-machine $MACHINE'. Exiting." exit 2 fi -M='-machine pseries' +M="-machine $MACHINE" M+=",accel=$ACCEL" -command="$qemu -nodefaults $M -bios $FIRMWARE" +B="" +if [[ "$MACHINE" == "pseries"* ]] ; then + B+="-bios $FIRMWARE" +fi + +D="" +if [[ "$MACHINE" == "powernv"* ]] ; then + D+="-device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10" +fi + +command="$qemu -nodefaults $M $B $D" command+=" -display none -serial stdio -kernel" command="$(migration_cmd) $(timeout_cmd) $command" From patchwork Thu Jun 8 07:58:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13271728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11D60C7EE23 for ; Thu, 8 Jun 2023 08:00:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234155AbjFHIAH (ORCPT ); Thu, 8 Jun 2023 04:00:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233970AbjFHH7s (ORCPT ); Thu, 8 Jun 2023 03:59:48 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC6622709 for ; Thu, 8 Jun 2023 00:59:24 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-662f0feafb2so251552b3a.1 for ; Thu, 08 Jun 2023 00:59:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686211163; x=1688803163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gIf7mMUq3IomvCRzE/BwBbmr5XmOTNpFkv4p84CsDuY=; b=jsPmE4fa/vT9fHYhtvIl+4+1qBxxy9x9h7KJous9XPUnlMoK2Yq84qaDVaYAgzdGsv wwzj9dh1JSY3RVDhi/CFgfB69g4HrwyEaHKcxW2Wj5JDpBmRfOT0mhRoEtc+XLq8vXE9 9F1JUrsDZXZ5oaAqZiF4NOvaROlEKlmclayf5q4alYReCrxdDy8uhu14teAPlnc0sH7z YiCaHdTlV2oWOU97+MdATNnkpUJ+qJM0Fe7wCzHoNghxfGfSqJfQ5ZHHET9gO3vQr8Ts AHhN5WQCMI2IgqpuqshQxUFf9CSgvmgEap3OI7UV6vERYP5duwMbmQSskAGbzNn3olBd hQ7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686211163; x=1688803163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gIf7mMUq3IomvCRzE/BwBbmr5XmOTNpFkv4p84CsDuY=; b=MbCRp34Ov0Q/B6VDAyxawWVu8iAEFRtN4WUiDL5fpmV1GfIl4ap7Ao3Bgi9wFea5X7 oBaoPmJjX4H/w3YILx2Oyan4dQXWHf3XDMqb0vuPrOFxTHpN4F2Fy2PDvIUA4zg1hUH3 XHM2+uusS2wmU9//KtY1fU4Q3+NZJH0e+/qOXPbQNr2r+f5d+X1QB4UUnHYKTZjwOnWm 02CxUO69RD1ZxfX0II7IRFNpPhMtgWmlreq5m5OHcPLgcHO5aF/E7SKiZZG1e8K8QbEM gaDKqzqlfHwSiqEbPE3IxJIUabytgIKtMnnEE3msE6K11i4PgeMwC8EZmSzL6L9+DRgG nIXw== X-Gm-Message-State: AC+VfDwn+00S38mG84zQLWUB/5/smriYe1/rJ4SGAF9jupOH6YKX6kVK q230JNjluG/NB7DPKBwRgrlJFyqOiHQ= X-Google-Smtp-Source: ACHHUZ7j9tL8nMT4K1M5MLI0aYyAcL3vvSvos/iW3DoAZcAQYrxGQJhr3f0xfPBxEk3BSMBsxI26nQ== X-Received: by 2002:a05:6a20:8405:b0:103:b585:b587 with SMTP id c5-20020a056a20840500b00103b585b587mr1786346pzd.13.1686211163017; Thu, 08 Jun 2023 00:59:23 -0700 (PDT) Received: from wheely.local0.net ([1.146.34.117]) by smtp.gmail.com with ESMTPSA id 17-20020a630011000000b00542d7720a6fsm673182pga.88.2023.06.08.00.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 00:59:22 -0700 (PDT) From: Nicholas Piggin To: kvm@vger.kernel.org Cc: Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Laurent Vivier , Thomas Huth Subject: [kvm-unit-tests v4 12/12] powerpc/sprs: Test hypervisor registers on powernv machine Date: Thu, 8 Jun 2023 17:58:26 +1000 Message-Id: <20230608075826.86217-13-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230608075826.86217-1-npiggin@gmail.com> References: <20230608075826.86217-1-npiggin@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org This enables HV privilege registers to be tested with the powernv machine. Acked-by: Thomas Huth Signed-off-by: Nicholas Piggin --- powerpc/sprs.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/powerpc/sprs.c b/powerpc/sprs.c index d5664201..07a4e759 100644 --- a/powerpc/sprs.c +++ b/powerpc/sprs.c @@ -199,16 +199,16 @@ static const struct spr sprs_power_common[1024] = { [190] = {"HFSCR", 64, HV_RW, }, [256] = {"VRSAVE", 32, RW, }, [259] = {"SPRG3", 64, RO, }, -[284] = {"TBL", 32, HV_WO, }, -[285] = {"TBU", 32, HV_WO, }, -[286] = {"TBU40", 64, HV_WO, }, +[284] = {"TBL", 32, HV_WO, }, /* Things can go a bit wonky with */ +[285] = {"TBU", 32, HV_WO, }, /* Timebase changing. Should save */ +[286] = {"TBU40", 64, HV_WO, }, /* and restore it. */ [304] = {"HSPRG0", 64, HV_RW, }, [305] = {"HSPRG1", 64, HV_RW, }, [306] = {"HDSISR", 32, HV_RW, SPR_INT, }, [307] = {"HDAR", 64, HV_RW, SPR_INT, }, [308] = {"SPURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, [309] = {"PURR", 64, HV_RW | OS_RO, SPR_ASYNC, }, -[313] = {"HRMOR", 64, HV_RW, }, +[313] = {"HRMOR", 64, HV_RW, SPR_HARNESS, }, /* Harness can't cope with HRMOR changing */ [314] = {"HSRR0", 64, HV_RW, SPR_INT, }, [315] = {"HSRR1", 64, HV_RW, SPR_INT, }, [318] = {"LPCR", 64, HV_RW, }, @@ -306,7 +306,7 @@ static const struct spr sprs_power9_10[1024] = { [921] = {"TSCR", 32, HV_RW, }, [922] = {"TTR", 64, HV_RW, }, [1006]= {"TRACE", 64, WO, }, -[1008]= {"HID", 64, HV_RW, }, +[1008]= {"HID", 64, HV_RW, SPR_HARNESS, }, /* At least HILE would be unhelpful to change */ }; /* This covers POWER8 and POWER9 PMUs */ @@ -350,6 +350,22 @@ static const struct spr sprs_power10_pmu[1024] = { static struct spr sprs[1024]; +static bool spr_read_perms(int spr) +{ + if (machine_is_powernv()) + return !!(sprs[spr].access & SPR_HV_READ); + else + return !!(sprs[spr].access & SPR_OS_READ); +} + +static bool spr_write_perms(int spr) +{ + if (machine_is_powernv()) + return !!(sprs[spr].access & SPR_HV_WRITE); + else + return !!(sprs[spr].access & SPR_OS_WRITE); +} + static void setup_sprs(void) { uint32_t pvr = mfspr(287); /* Processor Version Register */ @@ -466,7 +482,7 @@ static void get_sprs(uint64_t *v) int i; for (i = 0; i < 1024; i++) { - if (!(sprs[i].access & SPR_OS_READ)) + if (!spr_read_perms(i)) continue; v[i] = __mfspr(i); } @@ -477,8 +493,9 @@ static void set_sprs(uint64_t val) int i; for (i = 0; i < 1024; i++) { - if (!(sprs[i].access & SPR_OS_WRITE)) + if (!spr_write_perms(i)) continue; + if (sprs[i].type & SPR_HARNESS) continue; if (!strcmp(sprs[i].name, "MMCR0")) { @@ -550,7 +567,7 @@ int main(int argc, char **argv) for (i = 0; i < 1024; i++) { bool pass = true; - if (!(sprs[i].access & SPR_OS_READ)) + if (!spr_read_perms(i)) continue; if (sprs[i].width == 32) {