From patchwork Thu Jun 8 12:53:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 13272285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7A66C7EE45 for ; Thu, 8 Jun 2023 12:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236594AbjFHMxj (ORCPT ); Thu, 8 Jun 2023 08:53:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236599AbjFHMxa (ORCPT ); Thu, 8 Jun 2023 08:53:30 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8790630C8 for ; Thu, 8 Jun 2023 05:53:22 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-30af56f5f52so423290f8f.1 for ; Thu, 08 Jun 2023 05:53:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686228801; x=1688820801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uE6yetChMOkuyV+sjyKHm251FghkzA4hPqZSw4S47tc=; b=Qs964vZiSrUd9xRN3bUR/kE1/e/8gR9C1EDcHEoEQBiZ158H5xj3aAZ6L/9ZLCs1Pk ndRB/ofQDZyBz6zBADVcceYTgIKIM/HO62OVhUmNUW8gz8LWamZeE3+YsMZnlc8v+EWW htU6R6duJkyyrjU7L6hbbUNGKCjfuIh/ejC3O3PIAeuhhx8I5PjNOwjmgU/hEpzBCB6Z bKtCkVZ0TeXBrsQY7voGzc2CYsz3JIgdim2Il1bPLj0WIvmIGYYMcaUmTA98Bu3pLXLl cjk9JQgO+Fuf1i5pmyBqAVsqW1wE/ib8m7/vxbblwm1kM0BpvastTaXbmu1JInicssul 8mKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686228801; x=1688820801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uE6yetChMOkuyV+sjyKHm251FghkzA4hPqZSw4S47tc=; b=e4NGqIdHDLg5/ethK2HKcLFoz+36JtNu9gseiZgaX7PWouAweh0HYn5s1AzQb9ddNo MYEkRO6SASPDi6ZeUUvg0ez+bAT/Ahwy3dgm0fjpPF2MRrkErsFrES6D1pji6geng3vW w3Ta/wpJGuvvQKvM92FDt7UyOCimTDysg1gRTGB/Wio5zVhQnUOwDPfm5mpPIJRSozds WErX4PF+USWrTaDzQH3+5dDf7tVvB46nLHBZVOj03ws2MWdPdD4gkNEV6EyE8Uv9BsxH A+7adsNylRV8sxb7adqOVabQ++sbtxNYtb9fTN7t+18OVKCwM7sBOB32BlgG/OvgXpDX Yd7g== X-Gm-Message-State: AC+VfDztImSFnh9InlCRDZAe7Jv8sfJ2HMoC9tecvBWQNt+DwJED6jE4 kS+RfOcFkhinMh5maS/NGLThuQ== X-Google-Smtp-Source: ACHHUZ636bbC4LpcLeOPnpSyZyMFlV/AWPyMeWt7bFH+vrpAbzR1F2n5Km6Sc8dcNnvF98MFXtKM5A== X-Received: by 2002:a5d:510c:0:b0:309:3af4:8c8c with SMTP id s12-20020a5d510c000000b003093af48c8cmr6725833wrt.54.1686228800773; Thu, 08 Jun 2023 05:53:20 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id m22-20020a7bce16000000b003f7e4d143cfsm1894032wmc.15.2023.06.08.05.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 05:53:20 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v3 1/6] dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP Date: Thu, 8 Jun 2023 13:53:10 +0100 Message-Id: <20230608125315.11454-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230608125315.11454-1-srinivas.kandagatla@linaro.org> References: <20230608125315.11454-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 50 +++++++++++++++++++ .../dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 12 +++++ 2 files changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml create mode 100644 include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 000000000000..047cae91f443 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-lpasscc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0x033e0000 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h new file mode 100644 index 000000000000..df800ea2741c --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H + +/* LPASS TCSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + +#endif From patchwork Thu Jun 8 12:53:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 13272286 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23C8EC7EE25 for ; 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Thu, 08 Jun 2023 05:53:21 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id m22-20020a7bce16000000b003f7e4d143cfsm1894032wmc.15.2023.06.08.05.53.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 05:53:21 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v3 2/6] dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP Date: Thu, 8 Jun 2023 13:53:11 +0100 Message-Id: <20230608125315.11454-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230608125315.11454-1-srinivas.kandagatla@linaro.org> References: <20230608125315.11454-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 10 ++++++++++ include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 047cae91f443..3326dcd6766c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -19,6 +19,7 @@ description: | properties: compatible: enum: + - qcom,sc8280xp-lpassaudiocc - qcom,sc8280xp-lpasscc reg: @@ -39,6 +40,15 @@ required: additionalProperties: false examples: + - | + #include + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + - | #include lpasscc: clock-controller@33e0000 { diff --git a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h index df800ea2741c..d190d57fc81a 100644 --- a/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h +++ b/include/dt-bindings/clock/qcom,sc8280xp-lpasscc.h @@ -6,6 +6,11 @@ #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + /* LPASS TCSR */ #define LPASS_AUDIO_SWR_TX_CGCR 0 From patchwork Thu Jun 8 12:53:12 2023 Content-Type: text/plain; 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This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold --- drivers/clk/qcom/Kconfig | 9 ++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-sc8280xp.c | 64 +++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sc8280xp.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9cd1f05d436b..263e55d75e3f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -551,6 +551,15 @@ config SC_LPASSCC_7280 Say Y if you want to use the LPASS branch clocks of the LPASS clock controller to reset the LPASS subsystem. +config SC_LPASSCC_8280XP + tristate "SC8280 Low Power Audio Subsystem (LPASS) Clock Controller" + depends on ARM64 || COMPILE_TEST + select SC_GCC_8280XP + help + Support for the LPASS clock controller on SC8280XP devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SC_LPASS_CORECC_7180 tristate "SC7180 LPASS Core Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 75d035150118..e6e294274c35 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o obj-$(CONFIG_SC_LPASSCC_7280) += lpasscc-sc7280.o +obj-$(CONFIG_SC_LPASSCC_8280XP) += lpasscc-sc8280xp.o obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o obj-$(CONFIG_SC_LPASS_CORECC_7280) += lpasscorecc-sc7280.o lpassaudiocc-sc7280.o obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc-sc8280xp.c new file mode 100644 index 000000000000..4a0470fc6153 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "reset.h" + +static const struct qcom_reset_map lpasscc_sc8280xp_resets[] = { + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 }, +}; + +static struct regmap_config lpasscc_sc8280xp_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-tcsr", + .max_register = 0x12000, +}; + +static const struct qcom_cc_desc lpasscc_sc8280xp_reset_desc = { + .config = &lpasscc_sc8280xp_regmap_config, + .resets = lpasscc_sc8280xp_resets, + .num_resets = ARRAY_SIZE(lpasscc_sc8280xp_resets), +}; + +static const struct of_device_id lpasscc_sc8280xp_match_table[] = { + { + .compatible = "qcom,sc8280xp-lpasscc", + .data = &lpasscc_sc8280xp_reset_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpasscc_sc8280xp_match_table); + +static int lpasscc_sc8280xp_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc = of_device_get_match_data(&pdev->dev); + + return qcom_cc_probe_by_index(pdev, 0, desc); +} + +static struct platform_driver lpasscc_sc8280xp_driver = { + .probe = lpasscc_sc8280xp_probe, + .driver = { + .name = "lpasscc-sc8280xp", + .of_match_table = lpasscc_sc8280xp_match_table, + }, +}; + +module_platform_driver(lpasscc_sc8280xp_driver); + +MODULE_AUTHOR("Srinivas Kandagatla "); +MODULE_DESCRIPTION("QTI LPASSCC SC8280XP Driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Jun 8 12:53:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 13272288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F566C7EE45 for ; Thu, 8 Jun 2023 12:53:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236680AbjFHMxq (ORCPT ); Thu, 8 Jun 2023 08:53:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236621AbjFHMxh (ORCPT ); Thu, 8 Jun 2023 08:53:37 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30A2A2D57 for ; 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This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold --- drivers/clk/qcom/lpasscc-sc8280xp.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc-sc8280xp.c index 4a0470fc6153..43b37ce397cf 100644 --- a/drivers/clk/qcom/lpasscc-sc8280xp.c +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -15,6 +15,26 @@ #include "common.h" #include "reset.h" +static const struct qcom_reset_map lpass_audiocc_sc8280xp_resets[] = { + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 }, + [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 }, +}; + +static struct regmap_config lpass_audiocc_sc8280xp_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-audio-csr", + .max_register = 0x1000, +}; + +static const struct qcom_cc_desc lpass_audiocc_sc8280xp_reset_desc = { + .config = &lpass_audiocc_sc8280xp_regmap_config, + .resets = lpass_audiocc_sc8280xp_resets, + .num_resets = ARRAY_SIZE(lpass_audiocc_sc8280xp_resets), +}; + static const struct qcom_reset_map lpasscc_sc8280xp_resets[] = { [LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 }, }; @@ -35,6 +55,9 @@ static const struct qcom_cc_desc lpasscc_sc8280xp_reset_desc = { static const struct of_device_id lpasscc_sc8280xp_match_table[] = { { + .compatible = "qcom,sc8280xp-lpassaudiocc", + .data = &lpass_audiocc_sc8280xp_reset_desc, + }, { .compatible = "qcom,sc8280xp-lpasscc", .data = &lpasscc_sc8280xp_reset_desc, }, From patchwork Thu Jun 8 12:53:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 13272289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 426A8C7EE43 for ; Thu, 8 Jun 2023 12:53:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236689AbjFHMxu (ORCPT ); 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Thu, 08 Jun 2023 05:53:25 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v3 5/6] arm64: dts: qcom: sc8280xp: add resets for soundwire controllers Date: Thu, 8 Jun 2023 13:53:14 +0100 Message-Id: <20230608125315.11454-6-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230608125315.11454-1-srinivas.kandagatla@linaro.org> References: <20230608125315.11454-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Soundwire controllers on sc8280xp needs an explicit reset, add support for this. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 6730349e34f4..6b1bb203b1d1 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -2560,6 +2561,8 @@ swr1: soundwire-controller@3210000 { interrupts = ; clocks = <&rxmacro>; clock-names = "iface"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names = "swr_audio_cgcr"; label = "RX"; qcom,din-ports = <0>; @@ -2634,6 +2637,8 @@ swr0: soundwire-controller@3250000 { interrupts = ; clocks = <&wsamacro>; clock-names = "iface"; + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names = "swr_audio_cgcr"; label = "WSA"; qcom,din-ports = <2>; @@ -2656,6 +2661,13 @@ swr0: soundwire-controller@3250000 { status = "disabled"; }; + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0 0x032a9000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + swr2: soundwire-controller@3330000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03330000 0 0x2000>; @@ -2665,6 +2677,8 @@ swr2: soundwire-controller@3330000 { clocks = <&txmacro>; clock-names = "iface"; + resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names = "swr_audio_cgcr"; label = "TX"; #sound-dai-cells = <1>; #address-cells = <2>; @@ -2858,6 +2872,13 @@ data-pins { }; }; + lpasscc: clock-controller@33e0000 { + compatible = "qcom,sc8280xp-lpasscc"; + reg = <0 0x033e0000 0 0x12000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + sdc2: mmc@8804000 { compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; From patchwork Thu Jun 8 12:53:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 13272290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9754AC7EE45 for ; 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Thu, 08 Jun 2023 05:53:27 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id m22-20020a7bce16000000b003f7e4d143cfsm1894032wmc.15.2023.06.08.05.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 05:53:26 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla , Krzysztof Kozlowski Subject: [PATCH v3 6/6] arm64: defconfig: Enable sc828x0xp lpasscc clock controller Date: Thu, 8 Jun 2023 13:53:15 +0100 Message-Id: <20230608125315.11454-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230608125315.11454-1-srinivas.kandagatla@linaro.org> References: <20230608125315.11454-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Enabled sc828x0xp lpasscc clock controller driver required for X13s laptop. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e05706d3893d..bc5d75cf71de 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1185,6 +1185,7 @@ CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SC_GCC_8180X=y CONFIG_SC_GCC_8280XP=y +CONFIG_SC_LPASSCC_8280XP=m CONFIG_SDM_CAMCC_845=m CONFIG_SDM_GPUCC_845=y CONFIG_SDM_VIDEOCC_845=y