From patchwork Fri Jun 9 05:41:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parikshit Pareek X-Patchwork-Id: 13273235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DD40C7EE37 for ; Fri, 9 Jun 2023 05:42:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229969AbjFIFm4 (ORCPT ); Fri, 9 Jun 2023 01:42:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229493AbjFIFmz (ORCPT ); Fri, 9 Jun 2023 01:42:55 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BF96270B; Thu, 8 Jun 2023 22:42:54 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3595gN9i016448; Fri, 9 Jun 2023 05:42:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=6xDwXST5JmukggFNWVIpAXN41vdJwQIThumaYJkh+Ws=; b=UNlvxv1uSKXXSKY9kRjf9z73t86ZPFwMrVfn4XDiIJWxtdtK+BM9YZ2uMUqImPNlqgpF HBOHm+xOXk52xPHYKuG8SU/XS9GJunDzo433ajC4BWcL379Vw362jv6NKz6kL5Xh5Vv3 T+xWq++R28fx1c/iZaiM/q/enq2aYoDhcnqG6M42LWyFP72VV33zGmEte90Te0NLQn5x iSA5ToWTKVyyKZCxYxiP6o2PJR4rQGfBeBkhRPolSAD5Y3rZ4IdxJoPvvYvz+uOweri7 cbUAKusrxmvSenK2jxmJ+QScT7CeBibaCTPQL7wj5U/w9lEWBUOwgas3XGMtVq1rsDdp CQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r3uja08e0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 09 Jun 2023 05:42:30 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3595gTPI012410 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 9 Jun 2023 05:42:29 GMT Received: from hu-ppareek-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 8 Jun 2023 22:42:24 -0700 From: Parikshit Pareek To: Will Deacon , Robin Murphy , "Joerg Roedel" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio CC: Manivannan Sadhasivam , Dmitry Baryshkov , Marijn Suijten , Adam Skladowski , , , , , "linux-kernel @ vger . kernel . org Prasanna Kumar" , Shazad Hussain , Parikshit Pareek Subject: [PATCH 1/3] dt-bindings: arm-smmu: Add interconnect for qcom SMMUs Date: Fri, 9 Jun 2023 11:11:40 +0530 Message-ID: <20230609054141.18938-2-quic_ppareek@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230609054141.18938-1-quic_ppareek@quicinc.com> References: <20230609054141.18938-1-quic_ppareek@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gx-BzWCa23aZDU4sT8BqnqVZm3RuNFw1 X-Proofpoint-ORIG-GUID: gx-BzWCa23aZDU4sT8BqnqVZm3RuNFw1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_03,2023-06-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090048 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There are certain SMMUs on qcom SoCs, which need to set interconnect- bandwidth, before accessing any MIMO mapped HW registers, and accessing RAM during page table walk. Hence introduce the due bindings for interconnects. Reported-by: Eric Chanudet Signed-off-by: Parikshit Pareek --- .../devicetree/bindings/iommu/arm,smmu.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index ba677d401e24..75e00789d8c2 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -327,6 +327,28 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + contains: + enum: + qcom,sa8775p-smmu-500 + then: + properties: + interconnects: + minItems: 1 + maxItems: 1 + + interconnect-names: + minItems: 1 + items: + - const: tbu_mc + + icc_bw: + $ref: /schemas/types.yaml#/definitions/int32 + description: + An integer expressing the interconnect bandwidth(MBps) to be set. + - if: properties: compatible: From patchwork Fri Jun 9 05:41:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parikshit Pareek X-Patchwork-Id: 13273236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D33E3C7EE25 for ; Fri, 9 Jun 2023 05:43:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236109AbjFIFnu (ORCPT ); Fri, 9 Jun 2023 01:43:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229493AbjFIFnt (ORCPT ); Fri, 9 Jun 2023 01:43:49 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00C7A270B; Thu, 8 Jun 2023 22:43:48 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3594bDBD027801; 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Fri, 9 Jun 2023 05:43:33 GMT Received: from hu-ppareek-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 8 Jun 2023 22:43:27 -0700 From: Parikshit Pareek To: Will Deacon , Robin Murphy , "Joerg Roedel" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio CC: Manivannan Sadhasivam , Dmitry Baryshkov , Marijn Suijten , Adam Skladowski , , , , , "linux-kernel @ vger . kernel . org Prasanna Kumar" , Shazad Hussain , Parikshit Pareek Subject: [PATCH 2/3] arm64: dts: qcom: sa8775p: Add interconnect to PCIe SMMU Date: Fri, 9 Jun 2023 11:11:41 +0530 Message-ID: <20230609054141.18938-3-quic_ppareek@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230609054141.18938-1-quic_ppareek@quicinc.com> References: <20230609054141.18938-1-quic_ppareek@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YcfMlfEhbts9EiUZmDTRXNmahaPwH2ex X-Proofpoint-ORIG-GUID: YcfMlfEhbts9EiUZmDTRXNmahaPwH2ex X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_03,2023-06-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 spamscore=0 impostorscore=0 phishscore=0 adultscore=0 mlxlogscore=700 lowpriorityscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090049 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce the interconnect, connecting PCIe SMMU to the memory. This is accessed during memory mapped IO access of smmu registers, and during page table walks. Reported-by: Eric Chanudet Signed-off-by: Parikshit Pareek --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index b130136acffe..ea3c37019c46 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2137,6 +2137,10 @@ , , ; + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "tbu_mc"; + icc_bw = <250>; }; intc: interrupt-controller@17a00000 { From patchwork Fri Jun 9 05:52:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parikshit Pareek X-Patchwork-Id: 13273243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 039D1C7EE25 for ; Fri, 9 Jun 2023 05:53:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229796AbjFIFx3 (ORCPT ); Fri, 9 Jun 2023 01:53:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229518AbjFIFx1 (ORCPT ); Fri, 9 Jun 2023 01:53:27 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EA3E30D1; Thu, 8 Jun 2023 22:53:26 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3594WSIb029465; Fri, 9 Jun 2023 05:53:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=Sa241Jhc0rB20AIxBgrwQotffKxAIKzXI/CdDmbz5MY=; b=BROYdUlsLF6FwXfEkJpuWovySZaU3VyRaMUnhXuBR5LHwy6vvG5pqxDLW+pkMw7a2IEY 6+OLdT2wfhcho5EZbh0drp5VyvM5MsoGwSUvlXokraYKoCPQLAiGXL6iVKKbaQA98n7q WspV+1EU2MJwZ/BLQbZ0JFXLjgEgvBnyh6nbn8KGy/mYeeQSkE8JJl0go+IsJzlBKslx yoX+wT0JuH5ual7npA+XyK2BV5JX8zeoXdcNjGlbw4Xqk7fX+yc9Bs371b7enQHrLIDr JKwTJ9qon8JZOzvQNN6iAJetGkmum+HyU27FpofLHAVaxRPwibMcPh8wqv20Kap05D9P vQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r3uja08wa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 09 Jun 2023 05:53:10 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3595r9Xt010946 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 9 Jun 2023 05:53:09 GMT Received: from hu-ppareek-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 8 Jun 2023 22:52:48 -0700 From: Parikshit Pareek To: Will Deacon , Robin Murphy , "Joerg Roedel" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio CC: Manivannan Sadhasivam , Dmitry Baryshkov , Marijn Suijten , Adam Skladowski , , , , , "linux-kernel @ vger . kernel . org Prasanna Kumar" , Shazad Hussain , Parikshit Pareek Subject: [PATCH 3/3] iommu/arm-smmu-qcom: Add support for the interconnect Date: Fri, 9 Jun 2023 11:22:25 +0530 Message-ID: <20230609055225.20717-1-quic_ppareek@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230609054141.18938-1-quic_ppareek@quicinc.com> References: <20230609054141.18938-1-quic_ppareek@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 53Kv0YAoHXBldbEtHdhUviorfcHk1GPp X-Proofpoint-ORIG-GUID: 53Kv0YAoHXBldbEtHdhUviorfcHk1GPp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_03,2023-06-08_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090050 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce support to detect the interconnect, and set its bandwidth. For certain targets, we need to set the bandwidth of interconnect, connecting smmu to memory. This is accessed during memory mapped IO access to smmu registers, and during page tables walks. Reported-by: Eric Chanudet Signed-off-by: Parikshit Pareek --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index c71afda79d64..6961d564869b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "arm-smmu.h" #include "arm-smmu-qcom.h" @@ -549,6 +550,8 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) { const struct device_node *np = smmu->dev->of_node; const struct of_device_id *match; + struct icc_path *icc_path; + int ret, icc_bw; #ifdef CONFIG_ACPI if (np == NULL) { @@ -558,6 +561,19 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) } #endif + icc_path = devm_of_icc_get(smmu->dev, "tbu_mc"); + if (IS_ERR(icc_path)) + return (struct arm_smmu_device *)icc_path; + + ret = of_property_read_u32(np, "icc_bw", &icc_bw); + + /*if interconnect exists, check for the bandwidth value*/ + if (icc_path && !ret) { + ret = icc_set_bw(icc_path, 0, MBps_to_icc(icc_bw)); + if (ret) + return ERR_PTR(ret); + } + match = of_match_node(qcom_smmu_impl_of_match, np); if (match) return qcom_smmu_create(smmu, match->data);