From patchwork Fri Jun 9 16:33:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13274174 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 319AF17750 for ; Fri, 9 Jun 2023 16:34:53 +0000 (UTC) Received: from sender4-op-o10.zoho.com (sender4-op-o10.zoho.com [136.143.188.10]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 861611BCC; Fri, 9 Jun 2023 09:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686328448; cv=none; d=zohomail.com; s=zohoarc; b=OVbpIvwVMV5r8luTIjlSt6DaVqJORIowdDYboJevmHSU1sH0LL9yn97xwmClAXlj9kXfBkwvVijS8p+Bv0SIBjZwX311EeV45xRWia1qAxnv4JiXa9UTPYX40vSZYX3LBtW3b2XeIJr/R+3LLEyQYcAg7yuMBUFXSCI/jBbeW3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686328448; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:MIME-Version:Message-ID:Subject:To; bh=0kpmv7bgbqSWfxD0zHmu1wp6zMxmyDJTtu6zFlZuJLc=; b=O4GWkxsi8YefZmctmAYfplIhvSpKHGp9zV3wO5QB+LLKRAcf7rbgnoTnECwX4keJ7NAXXGuJcb2SYZcL0PJMkGtO0wn/wRw6oaxdXL7vnKM39zehGrqktJJZtZKDcn8Ig1KFWZI9cXaKDKeJU1fmiiXAc0MryQCYwRwUG0oFFk0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1686328448; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=0kpmv7bgbqSWfxD0zHmu1wp6zMxmyDJTtu6zFlZuJLc=; b=jVDqE5JItTE8oAL19JKtQ2lwoe6OeXfWVRMQdyZv3JOf+z4KulRsmY0b0KCgCJN7 8lkzBg4Vnztv9YqmKk2LD5Bqk5FoB/Lzrx3zqWEec5BBtow2TAa9Kxjp2Iv1H6zPWFs mv94Oo2V2sRzixHnOJLCkCnCqSDwR2d0Z6HwH7QU= Received: from arinc9-Xeront.. (62.74.20.25 [62.74.20.25]) by mx.zohomail.com with SMTPS id 168632844644444.67253435735802; Fri, 9 Jun 2023 09:34:06 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net 1/5] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7531 Date: Fri, 9 Jun 2023 19:33:49 +0300 Message-Id: <20230609163353.78941-1-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Every bit of the CPU port bitmap for MT7531 and the switch on the MT7988 SoC represents a CPU port to trap frames to. These switches trap frames to the CPU port the user port, which the frames are received from, is affine to. Currently, only the bit that corresponds to the first found CPU port is set on the bitmap. When multiple CPU ports are being used, frames from the user ports affine to the other CPU port which are set to be trapped will be dropped as the affine CPU port is not set on the bitmap. Only the MT7531 switch is affected as there's only one port to be used as a CPU port on the switch on the MT7988 SoC. To fix this, introduce the MT7531_CPU_PMAP macro to individually set the bits of the CPU port bitmap. Set the CPU port bitmap for MT7531 and the switch on the MT7988 SoC on mt753x_cpu_port_enable() which runs on a loop for each CPU port. Add comments to explain frame trapping for these switches. According to the document MT7531 Reference Manual for Development Board v1.0, the MT7531_CPU_PMAP bits are unset after reset so no need to clear it beforehand. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 16 +++++++++------- drivers/net/dsa/mt7530.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9bc54e1348cb..8ab4718abb06 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1010,6 +1010,14 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) if (priv->id == ID_MT7621) mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on + * the MT7988 SoC. Any frames set for trapping to CPU port will be + * trapped to the CPU port the user port, which the frames are received + * from, is affine to. + */ + if (priv->id == ID_MT7531 || priv->id == ID_MT7988) + mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); + /* CPU port gets connected to all user ports of * the switch. */ @@ -2352,15 +2360,9 @@ static int mt7531_setup_common(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; - struct dsa_port *cpu_dp; int ret, i; - /* BPDU to CPU port */ - dsa_switch_for_each_cpu_port(cpu_dp, ds) { - mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, - BIT(cpu_dp->index)); - break; - } + /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, MT753X_BPDU_CPU_ONLY); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5084f48a8869..e590cf43f3ae 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -54,6 +54,7 @@ enum mt753x_id { #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) +#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) #define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ MT7531_CFC : MT7530_MFC) From patchwork Fri Jun 9 16:33:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13274176 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1A8619BCF for ; Fri, 9 Jun 2023 16:34:54 +0000 (UTC) Received: from sender3-op-o19.zoho.com (sender3-op-o19.zoho.com [136.143.184.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7BF71BEB; Fri, 9 Jun 2023 09:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686328454; cv=none; d=zohomail.com; s=zohoarc; b=JVut2M97hPKnK/J89UizmVeUsOoJAvCLgJkDz+A+uh5u1AQ9kN6cjB4NJWNyMg7fVcX9wJuiWBG1WSPC1zQxU00bpXD2Uqy0vd/+rova6Fv483TQ7Px7Nk6X2l9qlPi4qAqc3JsjgxoUnrzJh7G8R+fZ01Q8q7xXlhTxbd4wfhU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686328454; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=E8mfk1HF6L4tH///RyhbQqTPyEo53vj44BbOEOR1clM=; b=XcC/RX8Vshh4g+xgJ+hvot3xBEKGgMZ6OJJgoPF1oHF2r/gNLLO5A/FYyzsHO5NhKUdERDazFyA/MCo9KfOZozvNKkA24+BP/N95s3LkKVKKY8D3yly+CawaM394ap/vuZvkLlxCdMqIsP5BjsphTb9N+hF8cPycB7Za6hYYg5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1686328454; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=E8mfk1HF6L4tH///RyhbQqTPyEo53vj44BbOEOR1clM=; b=KOp1pBkb05UbfCtPpaeXJlA6xA1o4ElG2OIqh2z/+kWmzKjDbVd9ivGTOrZlahl3 0ZAJRnhA7LOtV4fj/SN3NeOtc9BcMPqJ+7JUtT4x8lb4gPBWLLIEocOWNCQgqBxeW1H 4kVXeR1+Iq04iChmDD6Dah4Q4RMa3j3bLFPVZRAo= Received: from arinc9-Xeront.. (62.74.20.25 [62.74.20.25]) by mx.zohomail.com with SMTPS id 1686328452823635.1140736606347; Fri, 9 Jun 2023 09:34:12 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net 2/5] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7530 Date: Fri, 9 Jun 2023 19:33:50 +0300 Message-Id: <20230609163353.78941-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230609163353.78941-1-arinc.unal@arinc9.com> References: <20230609163353.78941-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org The CPU_PORT bits represent the CPU port to trap frames to for the MT7530 switch. This switch traps frames to the CPU port set on the CPU_PORT bits, regardless of the affinity of the user port which the frames are received from. When multiple CPU ports are being used, the trapped frames won't be received when the DSA conduit interface, which the frames are supposed to be trapped to, is down because it's not affine to any user port. This requires the DSA conduit interface to be manually set up for the trapped frames to be received. To fix this, implement ds->ops->master_state_change() on this subdriver and set the CPU_PORT bits to the CPU port which the DSA conduit interface its affine to is up. Introduce the active_cpu_ports field to store the information of the active CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the register. Add comments to explain frame trapping for this switch. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Suggested-by: Vladimir Oltean Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 32 ++++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 6 ++++-- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 8ab4718abb06..da75f9b312bc 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1006,10 +1006,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); - /* Set CPU port number */ - if (priv->id == ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on * the MT7988 SoC. Any frames set for trapping to CPU port will be * trapped to the CPU port the user port, which the frames are received @@ -3063,6 +3059,33 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, return 0; } +static void +mt753x_master_state_change(struct dsa_switch *ds, + const struct net_device *master, + bool operational) +{ + struct mt7530_priv *priv = ds->priv; + struct dsa_port *cpu_dp = master->dsa_ptr; + + /* Set the CPU port to trap frames to for MT7530. There can be only one + * CPU port due to CPU_PORT having only 3 bits. Any frames received from + * a user port which are set for trapping to CPU port will be trapped to + * the numerically smallest CPU port which is affine to the DSA conduit + * interface that is up. + */ + if (priv->id != ID_MT7621) + return; + + if (operational) + priv->active_cpu_ports |= BIT(cpu_dp->index); + else + priv->active_cpu_ports &= ~BIT(cpu_dp->index); + + if (priv->active_cpu_ports) + mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, CPU_EN | + CPU_PORT(__ffs(priv->active_cpu_ports))); +} + static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { return 0; @@ -3117,6 +3140,7 @@ const struct dsa_switch_ops mt7530_switch_ops = { .phylink_mac_link_up = mt753x_phylink_mac_link_up, .get_mac_eee = mt753x_get_mac_eee, .set_mac_eee = mt753x_set_mac_eee, + .master_state_change = mt753x_master_state_change, }; EXPORT_SYMBOL_GPL(mt7530_switch_ops); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index e590cf43f3ae..28dbd131a535 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -41,8 +41,8 @@ enum mt753x_id { #define UNU_FFP(x) (((x) & 0xff) << 8) #define UNU_FFP_MASK UNU_FFP(~0) #define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) +#define CPU_PORT_MASK GENMASK(6, 4) +#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) #define MIRROR_EN BIT(3) #define MIRROR_PORT(x) ((x) & 0x7) #define MIRROR_MASK 0x7 @@ -753,6 +753,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + * @active_cpu_ports: Holding the active CPU ports */ struct mt7530_priv { struct device *dev; @@ -779,6 +780,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + unsigned long active_cpu_ports; }; struct mt7530_hw_vlan_entry { From patchwork Fri Jun 9 16:33:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13274175 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54A5F18C1A for ; Fri, 9 Jun 2023 16:34:54 +0000 (UTC) Received: from sender3-op-o18.zoho.com (sender3-op-o18.zoho.com [136.143.184.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 043961FDF; Fri, 9 Jun 2023 09:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686328460; cv=none; d=zohomail.com; s=zohoarc; b=hkYiuoaBGNcicBJqMrGa+snCNfic5+pcclNmkiojIZFM3G7OItv+puQxS/mRxyIxdfCHwJHqs4o/e93wKDzBSEOvyQVZl6Z6r2kC08kWe1XTVpZ7Q/gPIaGGADwqHeuQJZUAiNnEiyZz0ErLAmJRtQ8z45tQNNXn+R3yJOf6UVA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686328460; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=aMifJN4jd3TEuoV/A1C1hcI6+kLjQwx0MeZB39jRuMI=; b=Y+a1k8yfkLy8hNrO+k/rajLXz0KFDC6nTRVY3W0VLTJ8qgkIYpWKwMYhC53+zUwVlqyno27z2V4T9MzZdjIDdRWZS249M6b/7b1HCLtr3NpZpnsq1uypN/Jz++LFU/G79v+H6CnUh9/4ducMiZqCqV+6sCb6tQ83S4dtldnNZ3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1686328460; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=aMifJN4jd3TEuoV/A1C1hcI6+kLjQwx0MeZB39jRuMI=; b=DFyRV3X/taR7GcoW+p/IW6RLDHJCXicDmoS9WmiBXeT56swvQexR8GLmK9HbvCdt dTAW/1bkdbTpZi2epobukNpUs+OGWsVShsJjMVr3X5ConHHOLWwCWF4R9SozgrqyN3X dAVJzA+JzHsGrQKPXUTC3he8Tr4kbX1PTFv5SKxI= Received: from arinc9-Xeront.. (62.74.20.25 [62.74.20.25]) by mx.zohomail.com with SMTPS id 168632845896422.032713514232114; Fri, 9 Jun 2023 09:34:18 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net 3/5] net: dsa: mt7530: fix trapping frames on non-MT7621 SoC MT7530 switch Date: Fri, 9 Jun 2023 19:33:51 +0300 Message-Id: <20230609163353.78941-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230609163353.78941-1-arinc.unal@arinc9.com> References: <20230609163353.78941-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org The check for setting the CPU_PORT bits must include the non-MT7621 SoC MT7530 switch variants to trap frames. Expand the check to include them. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index da75f9b312bc..df2626f72367 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -3073,7 +3073,7 @@ mt753x_master_state_change(struct dsa_switch *ds, * the numerically smallest CPU port which is affine to the DSA conduit * interface that is up. */ - if (priv->id != ID_MT7621) + if (priv->id != ID_MT7530 && priv->id != ID_MT7621) return; if (operational) From patchwork Fri Jun 9 16:33:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13274177 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 655051B8EA for ; Fri, 9 Jun 2023 16:35:04 +0000 (UTC) Received: from sender3-op-o18.zoho.com (sender3-op-o18.zoho.com [136.143.184.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADF241BCC; Fri, 9 Jun 2023 09:35:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686328466; cv=none; d=zohomail.com; s=zohoarc; b=QuZMmV8/YwTVvEjCLAoUiijA4iO50VqCfBa+H5/lTcymqhkNSoAXffjLzZYn2/6+Zqvq/vhWvda5J9BnM9/BWtchPN0ULLboEllyGfUZpWYaI2xE/s79HqGuQZN1ctrxcremz8ykTe3tirLuR3lLcuR4Ez6DUa5/oa9k9ACRaB8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686328466; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=Atc+TvYEEosIOFDKzmslM57zX/4H0k5Y4Sf4I02uDEc=; b=NF/7QkD0Wn/WPhJ1gLiRAvMilB2geSRYUfS8pGSrXtv3v9ahAcU1nR7PnqR/VkyBpmI9QBtCV885uD3HLuapfJR7EbAgegvjOjRgqGCytjjrsa0bVIZNvjh1e3Fa1uOHXwT3fJ+ZRvK48RKtCYJBAJBMi5/dtfDh98B2gho2WC0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1686328466; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=Atc+TvYEEosIOFDKzmslM57zX/4H0k5Y4Sf4I02uDEc=; b=bxHqjJCW73PB2ZfrdkcmJyBaAPC8iQwPxmkm8BBuivR8LSALZ0si6T/pv62RWxJD a9J4Kh8ezwKiEutSdGQS4l3ZXzw/ik836GP7pFj7Qb4Nt94mXpp9pfggH67vB8UMPsy L2wX60GWja2HRLH0RMFSVpavTzZLyPXxdRsVrr+Q= Received: from arinc9-Xeront.. (62.74.20.25 [62.74.20.25]) by mx.zohomail.com with SMTPS id 1686328465173539.5619989375218; Fri, 9 Jun 2023 09:34:25 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net 4/5] net: dsa: introduce preferred_default_local_cpu_port and use on MT7530 Date: Fri, 9 Jun 2023 19:33:52 +0300 Message-Id: <20230609163353.78941-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230609163353.78941-1-arinc.unal@arinc9.com> References: <20230609163353.78941-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org From: Vladimir Oltean Since the introduction of the OF bindings, DSA has always had a policy that in case multiple CPU ports are present in the device tree, the numerically smallest one is always chosen. The MT7530 switch family, except the switch on the MT7988 SoC, has 2 CPU ports, 5 and 6, where port 6 is preferable on the MT7531BE switch because it has higher bandwidth. The MT7530 driver developers had 3 options: - to modify DSA when the MT7531 switch support was introduced, such as to prefer the better port - to declare both CPU ports in device trees as CPU ports, and live with the sub-optimal performance resulting from not preferring the better port - to declare just port 6 in the device tree as a CPU port Of course they chose the path of least resistance (3rd option), kicking the can down the road. The hardware description in the device tree is supposed to be stable - developers are not supposed to adopt the strategy of piecemeal hardware description, where the device tree is updated in lockstep with the features that the kernel currently supports. Now, as a result of the fact that they did that, any attempts to modify the device tree and describe both CPU ports as CPU ports would make DSA change its default selection from port 6 to 5, effectively resulting in a performance degradation visible to users with the MT7531BE switch as can be seen below. Without preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 374 MBytes 157 Mbits/sec 734 sender [ 5][TX-C] 0.00-20.00 sec 373 MBytes 156 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 778 Mbits/sec 0 sender [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 777 Mbits/sec receiver With preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 856 Mbits/sec 273 sender [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 855 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.72 GBytes 737 Mbits/sec 15 sender [ 7][RX-C] 0.00-20.00 sec 1.71 GBytes 736 Mbits/sec receiver Using one port for WAN and the other ports for LAN is a very popular use case which is what this test emulates. As such, this change proposes that we retroactively modify stable kernels to keep the mt7530 driver preferring port 6 even with device trees where the hardware is more fully described. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Vladimir Oltean Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 15 +++++++++++++++ include/net/dsa.h | 8 ++++++++ net/dsa/dsa.c | 24 +++++++++++++++++++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index df2626f72367..8ae068a148c7 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -399,6 +399,20 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); } +/* If port 6 is available as a CPU port, always prefer that as the default, + * otherwise don't care. + */ +static struct dsa_port * +mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp = dsa_to_port(ds, 6); + + if (dsa_port_is_cpu(cpu_dp)) + return cpu_dp; + + return NULL; +} + /* Setup port 6 interface mode and TRGMII TX circuit */ static int mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) @@ -3110,6 +3124,7 @@ static int mt7988_setup(struct dsa_switch *ds) const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, + .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, .get_strings = mt7530_get_strings, .get_ethtool_stats = mt7530_get_ethtool_stats, .get_sset_count = mt7530_get_sset_count, diff --git a/include/net/dsa.h b/include/net/dsa.h index 8903053fa5aa..ab0f0a5b0860 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -958,6 +958,14 @@ struct dsa_switch_ops { struct phy_device *phy); void (*port_disable)(struct dsa_switch *ds, int port); + /* + * Compatibility between device trees defining multiple CPU ports and + * drivers which are not OK to use by default the numerically smallest + * CPU port of a switch for its local ports. This can return NULL, + * meaning "don't know/don't care". + */ + struct dsa_port *(*preferred_default_local_cpu_port)(struct dsa_switch *ds); + /* * Port's MAC EEE settings */ diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c index ab1afe67fd18..1afed89e03c0 100644 --- a/net/dsa/dsa.c +++ b/net/dsa/dsa.c @@ -403,6 +403,24 @@ static int dsa_tree_setup_default_cpu(struct dsa_switch_tree *dst) return 0; } +static struct dsa_port * +dsa_switch_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp; + + if (!ds->ops->preferred_default_local_cpu_port) + return NULL; + + cpu_dp = ds->ops->preferred_default_local_cpu_port(ds); + if (!cpu_dp) + return NULL; + + if (WARN_ON(!dsa_port_is_cpu(cpu_dp) || cpu_dp->ds != ds)) + return NULL; + + return cpu_dp; +} + /* Perform initial assignment of CPU ports to user ports and DSA links in the * fabric, giving preference to CPU ports local to each switch. Default to * using the first CPU port in the switch tree if the port does not have a CPU @@ -410,12 +428,16 @@ static int dsa_tree_setup_default_cpu(struct dsa_switch_tree *dst) */ static int dsa_tree_setup_cpu_ports(struct dsa_switch_tree *dst) { - struct dsa_port *cpu_dp, *dp; + struct dsa_port *preferred_cpu_dp, *cpu_dp, *dp; list_for_each_entry(cpu_dp, &dst->ports, list) { if (!dsa_port_is_cpu(cpu_dp)) continue; + preferred_cpu_dp = dsa_switch_preferred_default_local_cpu_port(cpu_dp->ds); + if (preferred_cpu_dp && preferred_cpu_dp != cpu_dp) + continue; + /* Prefer a local CPU port */ dsa_switch_for_each_port(dp, cpu_dp->ds) { /* Prefer the first local CPU port found */ From patchwork Fri Jun 9 16:33:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13274178 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9ECE111A2 for ; Fri, 9 Jun 2023 16:35:11 +0000 (UTC) Received: from sender4-op-o10.zoho.com (sender4-op-o10.zoho.com [136.143.188.10]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84E0A1AB; Fri, 9 Jun 2023 09:35:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686328472; cv=none; d=zohomail.com; s=zohoarc; b=nCQc/O0+eyzFzFdA3cU4iniSspwm0aSzPhhEbJ1F0VUsendfmrK110KO+hTZ/pp7pL+uf9vZRYdJvuKbk3+x1CqK7OItoSqxGRTJRfumyN36EPgXaKNn6l8o3IigJZIwDcTlxhRNvJQ0PyrYpen0V/QJAxplISsU+uWQ00mzhno= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686328472; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=905cpt816UbdZmkAKTALR8SANtBmtQIMIITLaVtiS6c=; b=daSNiCsMeQeURLl8oORMKyvWrQM3+4l3kMrOOkoQjxyV7IYqnZUFiqID8vy17u/W9OPEEtInHgwQAKcYmP5U0Y1UHnjvNRxfqHaAMV+W59tOp2Lzi/GtDYEvhui6i1lV+lkzWjsnNmmtS07hkn0JLpr6+EdlQuJaWorSFJ97OBw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=arinc9.com; spf=pass smtp.mailfrom=arinc.unal@arinc9.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1686328472; s=zmail; d=arinc9.com; i=arinc.unal@arinc9.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Type:Content-Transfer-Encoding:Reply-To; bh=905cpt816UbdZmkAKTALR8SANtBmtQIMIITLaVtiS6c=; b=Y6RJX/0VwLcU2MdtxcTld/R0V3sgzjez3MVpalnsWWIeX6kDK/d+eUFpB4yw/RkI IOdIFV16iMN6Sdy4u85WesekI+VfU8iDEUOroKokwA383nQuK7ZiUed3q8hRaVhRkQo bxvfQdn0OEiIBARCv+1byh2XynPSU05pftmfzkHU= Received: from arinc9-Xeront.. (62.74.20.25 [62.74.20.25]) by mx.zohomail.com with SMTPS id 1686328471208371.83351132363543; Fri, 9 Jun 2023 09:34:31 -0700 (PDT) From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net 5/5] MAINTAINERS: add me as maintainer of MEDIATEK SWITCH DRIVER Date: Fri, 9 Jun 2023 19:33:53 +0300 Message-Id: <20230609163353.78941-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230609163353.78941-1-arinc.unal@arinc9.com> References: <20230609163353.78941-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add me as a maintainer of the MediaTek MT7530 DSA subdriver. List maintainers in alphabetical order by first name. Signed-off-by: Arınç ÜNAL Reviewed-by: Vladimir Oltean --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a73e5a98503a..c58d7fbb40ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13259,10 +13259,11 @@ F: drivers/memory/mtk-smi.c F: include/soc/mediatek/smi.h MEDIATEK SWITCH DRIVER -M: Sean Wang +M: Arınç ÜNAL +M: Daniel Golle M: Landen Chao M: DENG Qingfang -M: Daniel Golle +M: Sean Wang L: netdev@vger.kernel.org S: Maintained F: drivers/net/dsa/mt7530-mdio.c