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[178.147.169.233]) by smtp.gmail.com with ESMTPSA id s5-20020a7bc385000000b003f6132f95e6sm7748979wmj.35.2023.06.11.01.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:16:05 -0700 (PDT) From: " =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= " X-Google-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v2 1/7] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7531 Date: Sun, 11 Jun 2023 11:15:41 +0300 Message-Id: <20230611081547.26747-1-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Every bit of the CPU port bitmap for MT7531 and the switch on the MT7988 SoC represents a CPU port to trap frames to. These switches trap frames to the CPU port the user port, which the frames are received from, is affine to. Currently, only the bit that corresponds to the first found CPU port is set on the bitmap. When multiple CPU ports are being used, frames from the user ports affine to the other CPU port which are set to be trapped will be dropped as the affine CPU port is not set on the bitmap. Only the MT7531 switch is affected as there's only one port to be used as a CPU port on the switch on the MT7988 SoC. To fix this, introduce the MT7531_CPU_PMAP macro to individually set the bits of the CPU port bitmap. Set the CPU port bitmap for MT7531 and the switch on the MT7988 SoC on mt753x_cpu_port_enable() which runs on a loop for each CPU port. Add comments to explain frame trapping for these switches. According to the document MT7531 Reference Manual for Development Board v1.0, the MT7531_CPU_PMAP bits are unset after reset so no need to clear it beforehand. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 16 +++++++++------- drivers/net/dsa/mt7530.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9bc54e1348cb..8ab4718abb06 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1010,6 +1010,14 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) if (priv->id == ID_MT7621) mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on + * the MT7988 SoC. Any frames set for trapping to CPU port will be + * trapped to the CPU port the user port, which the frames are received + * from, is affine to. + */ + if (priv->id == ID_MT7531 || priv->id == ID_MT7988) + mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); + /* CPU port gets connected to all user ports of * the switch. */ @@ -2352,15 +2360,9 @@ static int mt7531_setup_common(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; - struct dsa_port *cpu_dp; int ret, i; - /* BPDU to CPU port */ - dsa_switch_for_each_cpu_port(cpu_dp, ds) { - mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, - BIT(cpu_dp->index)); - break; - } + /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, MT753X_BPDU_CPU_ONLY); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5084f48a8869..e590cf43f3ae 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -54,6 +54,7 @@ enum mt753x_id { #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) +#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) #define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ MT7531_CFC : MT7530_MFC) From patchwork Sun Jun 11 08:15:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13275126 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDDE85233 for ; Sun, 11 Jun 2023 08:16:12 +0000 (UTC) Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFD9F2D70; Sun, 11 Jun 2023 01:16:10 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f7ebb2b82cso34024475e9.2; Sun, 11 Jun 2023 01:16:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686471369; x=1689063369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E8mfk1HF6L4tH///RyhbQqTPyEo53vj44BbOEOR1clM=; b=GiCWLUvNxgWvmtsJRAWk33c7K1+9tTJBbZRCmi7oDh91nORFu4xQP0gRIxMqx7jGO9 t44TlMeeI/yuFIKmJL4btdULtiwSrNfDRoefXhn3LzuS3SgABnM+ItiecX7+5Cjy86lS vuKVjvBmrz8fg49oOo9CS4FCKyAIFELUmCtZkDdqnmo9TOmxXg4HhMMrPWCiR8NvxRQC xNeH4noFGOyg04WpLsI4o3tJDRwIfg7q/Z8KNp7VRU9ZzeAMepcF5WmccX0tetBOoaUP DZhtNQDjUkTo6YCZIJZuBDtudhriI0mesH5XgeKUjTR1HUc4k99oSIdWoeN3Iq+O5hhg hQug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686471369; x=1689063369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E8mfk1HF6L4tH///RyhbQqTPyEo53vj44BbOEOR1clM=; b=HNGDQkvZk7TZK9u82ONlqu6VxwxQv9xwswlS0Ry3KWrXC1Ts7R/nCZeDXRYHk+lx7N Y8qTFU+UBW7SkjclvGlMM6mMb7zaj0XauyIWXsaVxIfox/xxEpUxZPFRS4OcDguaz6g5 jUxOYwAzUABE7oNywAl4cHSYMTdKvrJazc88CXRkUEtQU5dX3oizATQBes4cgZZ0sUEr FSU+XlXiOW0S/z/7KAzFTMiV7oLjiZj6UeYjSEOTaP5a8Dk+BKm/iNXKF8Ym/eFFYNLl FpcOl2+8YXShKFIuduZL5esjS0ukq8qU5EvKwTYLV7C2kjck4e9FY9dZvvOJjfpVhORb wWNQ== X-Gm-Message-State: AC+VfDwfUH3a9Wn5lRPpVsUvXluGLvhXE/Y3Y1dobCmNBgDUpxITAZkK UsdzGXRs4dKs3+YfapwJap4= X-Google-Smtp-Source: ACHHUZ4nRShIhhavWUBNk/+Xe/dCRHhjdwx/3BaHka8pZfCOtN6J41mzD79JBpzFH1puk74mbIDPqA== X-Received: by 2002:a05:600c:2310:b0:3f5:f83:4d84 with SMTP id 16-20020a05600c231000b003f50f834d84mr4490072wmo.31.1686471369274; Sun, 11 Jun 2023 01:16:09 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id s5-20020a7bc385000000b003f6132f95e6sm7748979wmj.35.2023.06.11.01.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:16:09 -0700 (PDT) From: " =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= " X-Google-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v2 2/7] net: dsa: mt7530: fix trapping frames with multiple CPU ports on MT7530 Date: Sun, 11 Jun 2023 11:15:42 +0300 Message-Id: <20230611081547.26747-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611081547.26747-1-arinc.unal@arinc9.com> References: <20230611081547.26747-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org The CPU_PORT bits represent the CPU port to trap frames to for the MT7530 switch. This switch traps frames to the CPU port set on the CPU_PORT bits, regardless of the affinity of the user port which the frames are received from. When multiple CPU ports are being used, the trapped frames won't be received when the DSA conduit interface, which the frames are supposed to be trapped to, is down because it's not affine to any user port. This requires the DSA conduit interface to be manually set up for the trapped frames to be received. To fix this, implement ds->ops->master_state_change() on this subdriver and set the CPU_PORT bits to the CPU port which the DSA conduit interface its affine to is up. Introduce the active_cpu_ports field to store the information of the active CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the register. Add comments to explain frame trapping for this switch. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Suggested-by: Vladimir Oltean Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 32 ++++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 6 ++++-- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 8ab4718abb06..da75f9b312bc 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1006,10 +1006,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); - /* Set CPU port number */ - if (priv->id == ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on * the MT7988 SoC. Any frames set for trapping to CPU port will be * trapped to the CPU port the user port, which the frames are received @@ -3063,6 +3059,33 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, return 0; } +static void +mt753x_master_state_change(struct dsa_switch *ds, + const struct net_device *master, + bool operational) +{ + struct mt7530_priv *priv = ds->priv; + struct dsa_port *cpu_dp = master->dsa_ptr; + + /* Set the CPU port to trap frames to for MT7530. There can be only one + * CPU port due to CPU_PORT having only 3 bits. Any frames received from + * a user port which are set for trapping to CPU port will be trapped to + * the numerically smallest CPU port which is affine to the DSA conduit + * interface that is up. + */ + if (priv->id != ID_MT7621) + return; + + if (operational) + priv->active_cpu_ports |= BIT(cpu_dp->index); + else + priv->active_cpu_ports &= ~BIT(cpu_dp->index); + + if (priv->active_cpu_ports) + mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, CPU_EN | + CPU_PORT(__ffs(priv->active_cpu_ports))); +} + static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { return 0; @@ -3117,6 +3140,7 @@ const struct dsa_switch_ops mt7530_switch_ops = { .phylink_mac_link_up = mt753x_phylink_mac_link_up, .get_mac_eee = mt753x_get_mac_eee, .set_mac_eee = mt753x_set_mac_eee, + .master_state_change = mt753x_master_state_change, }; EXPORT_SYMBOL_GPL(mt7530_switch_ops); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index e590cf43f3ae..28dbd131a535 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -41,8 +41,8 @@ enum mt753x_id { #define UNU_FFP(x) (((x) & 0xff) << 8) #define UNU_FFP_MASK UNU_FFP(~0) #define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) +#define CPU_PORT_MASK GENMASK(6, 4) +#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) #define MIRROR_EN BIT(3) #define MIRROR_PORT(x) ((x) & 0x7) #define MIRROR_MASK 0x7 @@ -753,6 +753,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + * @active_cpu_ports: Holding the active CPU ports */ struct mt7530_priv { struct device *dev; @@ -779,6 +780,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + unsigned long active_cpu_ports; }; struct mt7530_hw_vlan_entry { From patchwork Sun Jun 11 08:15:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13275127 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1109053B5 for ; Sun, 11 Jun 2023 08:16:15 +0000 (UTC) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3F9E2D70; Sun, 11 Jun 2023 01:16:13 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f7353993cbso23664445e9.0; Sun, 11 Jun 2023 01:16:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686471372; x=1689063372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aMifJN4jd3TEuoV/A1C1hcI6+kLjQwx0MeZB39jRuMI=; b=PthLKHnGGkr2WcYkatNv4TnPl2TKewQFjocvu7QOVpW6epdBarlwxXnzjs67lNFm8z G51Em619D6KwVfuvv2GEQVUkBgfxOX9dtP7gJXDppNwmnOZmfNez9WzIwj7FemJUXC1j qC9GuZWA5ArVZbWYoXjGnP/Q2mZ3LExHhNJpL9rAKmne/k3DpirZWNwpYupx2Z3Ko5hU L3AeX1wezoLpPdRO060JOgp1sRtXiwovfxaeZJ6/uDs36q72Cwe+4bNtOOo7gnSSv3CJ SpJBFbqst6h2HuQQC112Yxmbk+Ak+mNp2iTSx7HRQRhnJ53qjpuI5enEGCoh4gdHRkxt LT4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686471372; x=1689063372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aMifJN4jd3TEuoV/A1C1hcI6+kLjQwx0MeZB39jRuMI=; b=QTkazCaTq0Kz9RRtfiHorTo7AK5OULmBtu8K1O+jmc3XPcEi18upDJI9mTArE4TXZU bZnqtCdV+e+mJ+JLbkUz6DTr0Ci5feYTQO1t4Em48lVU8mjdTm8vqQNNvr2hwYb+dVxc 5sQM+51KIwjHb2stjmjW1B0rT/mDkMAclHT5ExFrGLCnEVHa6QiTL8/InFG/8DZJHl3J ha1MrE83nr58EU0MaukoG5nIy195xS28qmOn01z4pUK5ihdBphPYZF7Q3REovmIRX9DW /+eLrOEoFmMVp7fQ/hJZxnmiLHJ1Hb55m5tt8Cq23yhYrghrgKdyP+wxIOOhnFBLQtni 8d8g== X-Gm-Message-State: AC+VfDy+wAoIL1HnfML/OJuVza5zTVcxjfwKdE831/1OkYFt1q7xt2iP wZ/J3nvAlLbJpmBl7FQpCD0= X-Google-Smtp-Source: ACHHUZ6RmdHmQyBkYL2UEpNAmKo5OiBthmTIpkl+PptirHvfGBelRvLejq6lO9XGvVBfdNBRgCRBWQ== X-Received: by 2002:a7b:c7da:0:b0:3f7:a20a:561d with SMTP id z26-20020a7bc7da000000b003f7a20a561dmr5316499wmk.8.1686471372137; Sun, 11 Jun 2023 01:16:12 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id s5-20020a7bc385000000b003f6132f95e6sm7748979wmj.35.2023.06.11.01.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:16:11 -0700 (PDT) From: " =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= " X-Google-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v2 3/7] net: dsa: mt7530: fix trapping frames on non-MT7621 SoC MT7530 switch Date: Sun, 11 Jun 2023 11:15:43 +0300 Message-Id: <20230611081547.26747-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611081547.26747-1-arinc.unal@arinc9.com> References: <20230611081547.26747-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org The check for setting the CPU_PORT bits must include the non-MT7621 SoC MT7530 switch variants to trap frames. Expand the check to include them. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index da75f9b312bc..df2626f72367 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -3073,7 +3073,7 @@ mt753x_master_state_change(struct dsa_switch *ds, * the numerically smallest CPU port which is affine to the DSA conduit * interface that is up. */ - if (priv->id != ID_MT7621) + if (priv->id != ID_MT7530 && priv->id != ID_MT7621) return; if (operational) From patchwork Sun Jun 11 08:15:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13275128 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 477297468 for ; Sun, 11 Jun 2023 08:16:18 +0000 (UTC) Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C053B30CB; Sun, 11 Jun 2023 01:16:16 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f7f4819256so23887925e9.1; Sun, 11 Jun 2023 01:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686471375; x=1689063375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xBp71EpjbBFFfBTbE6StpwPfHx+ioBBfY02xa9s3Mk8=; b=HTAA5G6Z9E/VB73DHO4rxeAG1KAOC1C45MY5RXkHifPQt7FGNuWFvjdVs5m0bne+lk 3BCWrTHY9yy7USuha4gY3tEjvNAnim+d6kKHvOL/XIQpv0IXDMzLEFfWlijpbswHPAsh RKEa/QF5dlzFQlsF/ZLH1lwPA6F5gewpZaHvRgEMub4iw5/sfjsKUFCF+3aXnNK4NEG7 xsvAmXF+jCmnUFzYBs9oz6fvy948T7na2FEi7zlczXwFmdlhieRn+rt1Bg6EUYapMHVc Pg5UTkssCyteoY05EJWkD440ZcdgzpzhWb3Zno14TGc45jVJj1zIi1cn55gkXBWuEU3j z2lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686471375; x=1689063375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xBp71EpjbBFFfBTbE6StpwPfHx+ioBBfY02xa9s3Mk8=; b=U4G8vM7ookhuFT0LpPvbbFLc4xJvSfuCjp+mtQXtMlO0YIfOy+xzVNn8fn9XfDDZXc J2jqDp/+ewavrDjDhvbRuLSr9uMZi/ZYrw7lRO9t9d6BuSBu70vZtvbv+jWqmjNYiQDl dk/KOXdneYzePFNJwH7vCG8VhI/5ikiwJv5uo4fNEiSAmfx7fkzARPDKXCLpKIQlP406 sKcqYDK/AmTDOyYsjCfbwjbyvX1lQaQTrYd9vvMl2MjfVYLF81b6iae1mVMewT+uq8cP NPk9hLaFDVd+6V7zcd6jPWPF+cym1RzWRnCM3m+y5MKqRGEmSnFFfvqAeVer6u/tqxCu A90w== X-Gm-Message-State: AC+VfDyDgnjztRfS+gKqA6AeDcPsf7vqcrMa3UdtaMu79XOyzgezR0aR 645pej0InEN4ui5iPRk7MWQ= X-Google-Smtp-Source: ACHHUZ4XULCaMtPSLP8E4rYYaX9aegzwRLkL2t9oCD5nApWgBEev2pWc/9iS09hK11hMr3BqiHyR8g== X-Received: by 2002:a7b:cb90:0:b0:3f5:878:c0c2 with SMTP id m16-20020a7bcb90000000b003f50878c0c2mr4382412wmi.3.1686471374902; Sun, 11 Jun 2023 01:16:14 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id s5-20020a7bc385000000b003f6132f95e6sm7748979wmj.35.2023.06.11.01.16.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:16:14 -0700 (PDT) From: " =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= " X-Google-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v2 4/7] net: dsa: mt7530: fix handling of BPDUs on MT7530 switch Date: Sun, 11 Jun 2023 11:15:44 +0300 Message-Id: <20230611081547.26747-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611081547.26747-1-arinc.unal@arinc9.com> References: <20230611081547.26747-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org BPDUs are link-local frames, therefore they must be trapped to the CPU port. Currently, the MT7530 switch treats BPDUs as regular multicast frames, therefore flooding them to user ports. To fix this, set BPDUs to be trapped to the CPU port. BPDUs received from a user port will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is up. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Signed-off-by: Arınç ÜNAL --- v2: Add this patch. --- drivers/net/dsa/mt7530.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index df2626f72367..c2af23f2bc5d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2259,6 +2259,10 @@ mt7530_setup(struct dsa_switch *ds) priv->p6_interface = PHY_INTERFACE_MODE_NA; + /* Trap BPDUs to the CPU port */ + mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, + MT753X_BPDU_CPU_ONLY); + /* Enable and reset MIB counters */ mt7530_mib_reset(ds); From patchwork Sun Jun 11 08:15:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13275129 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E42F079F3 for ; Sun, 11 Jun 2023 08:16:21 +0000 (UTC) Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A6C930E6; Sun, 11 Jun 2023 01:16:19 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f6e1394060so22880465e9.3; Sun, 11 Jun 2023 01:16:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686471378; x=1689063378; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UMmnTW6vfnMp79yuegpBgJKiMcf31rfT8bapddih3Ig=; b=rZwOZtBSliG8KRLdcxJNDpJOkRdM39rL67muP6AO0/LW8eghwVyMsjNvap51eh6sHt 7s5BWZaQ+GgvKV4HGn/tvZAewmFbJcdlPd8giWz9n8O/ExX7e4eWmShV4o1gNfiXEH4c YH2pTZMpc+z+S2oz7LbhLHqBH3FE7gxdb1QqRHgT0Xbrqi/2ksIA+KZGFK+cKp6cd8OM ySA64SDBACpuH7CFPtOW2OhwZ3n6MxGLczXf9g1kzQFifyTfjqrOwQjXKr5efpUnEkTH g2idI8AtGI9b3x5uuXwXBDPSL3b3EF7l7JYYXkVZsNCx+BYqygNB7xuIBcLCehaICjqj WOsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686471378; x=1689063378; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UMmnTW6vfnMp79yuegpBgJKiMcf31rfT8bapddih3Ig=; b=YDHI2zNcPstiQePUUtoPchPmm8oCHV8tdmKTYDRI0NR52G9ZDyqv33ghnTCxFsWoH+ zG0DFN2KAcEaQ0wlF0Src0W4B3nf4m50TpPQz48ITIUGAlfxzmhrsgomyel9hH859Q4K ATOg6EI0KR2BDEADfeOdL4Dw+sOMUUjBRRC7KoNvhylKc/Oz8dLYepRkdPSkbyRBhcDE wOnyU2Jsshd/2GREHFvkL1YYRwmC+1SFhx4kj7yYs49YQka08si4m2lfgX7h4a03zds5 a8O0410Lxw9yjz+nQEdMwi0ddolPKw8/sZO7JqVUA8gErxqN82febiAkiMmbPcNyCxym hr+w== X-Gm-Message-State: AC+VfDwtY7PrS+NvQo639h/UMSm0/UV6cuN9H923Scx+5EsL1MfaeXiJ cDfQjZ0bU0GawagOQrjR7jg= X-Google-Smtp-Source: ACHHUZ74BotKGO6LNp+U9VVf5CP5/GgQ2fN7FCyf09Nph5IYTWmjSTOJ98pBy8vhdXqB+L0ga9XVRw== X-Received: by 2002:a7b:cc83:0:b0:3f6:13f5:d1ea with SMTP id p3-20020a7bcc83000000b003f613f5d1eamr3641394wma.11.1686471377750; Sun, 11 Jun 2023 01:16:17 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id s5-20020a7bc385000000b003f6132f95e6sm7748979wmj.35.2023.06.11.01.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:16:17 -0700 (PDT) From: " =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= " X-Google-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v2 5/7] net: dsa: mt7530: fix handling of LLDP frames Date: Sun, 11 Jun 2023 11:15:45 +0300 Message-Id: <20230611081547.26747-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611081547.26747-1-arinc.unal@arinc9.com> References: <20230611081547.26747-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org LLDP frames are link-local frames, therefore they must be trapped to the CPU port. Currently, the MT753X switches treat LLDP frames as regular multicast frames, therefore flooding them to user ports. To fix this, set LLDP frames to be trapped to the CPU port(s). The mt753x_bpdu_port_fw enum is universally used for trapping frames, therefore rename it and the values in it to mt753x_port_fw. For MT7530, LLDP frames received from a user port will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is up. For MT7531 and the switch on the MT7988 SoC, LLDP frames received from a user port will be trapped to the CPU port the user port is affine to. The bit for R0E_MANG_FR is 27. When set, the switch regards the frames with :0E MAC DA as management (LLDP) frames. This bit is set to 1 after reset on MT7530 and MT7531 according to the documents MT7620 Programming Guide v1.0 and MT7531 Reference Manual for Development Board v1.0, so there's no need to deal with this bit. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Signed-off-by: Arınç ÜNAL --- v2: Add this patch. --- drivers/net/dsa/mt7530.c | 12 ++++++++++-- drivers/net/dsa/mt7530.h | 19 ++++++++++++------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index c2af23f2bc5d..97f389f8d6ea 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2261,7 +2261,11 @@ mt7530_setup(struct dsa_switch *ds) /* Trap BPDUs to the CPU port */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); + MT753X_PORT_FW_CPU_ONLY); + + /* Trap LLDP frames with :0E MAC DA to the CPU port */ + mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, + MT753X_R0E_PORT_FW(MT753X_PORT_FW_CPU_ONLY)); /* Enable and reset MIB counters */ mt7530_mib_reset(ds); @@ -2364,7 +2368,11 @@ mt7531_setup_common(struct dsa_switch *ds) /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); + MT753X_PORT_FW_CPU_ONLY); + + /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ + mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, + MT753X_R0E_PORT_FW(MT753X_PORT_FW_CPU_ONLY)); /* Enable and reset MIB counters */ mt7530_mib_reset(ds); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 28dbd131a535..5f048af2d89f 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -63,16 +63,21 @@ enum mt753x_id { #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ MT7531_MIRROR_MASK : MIRROR_MASK) -/* Registers for BPDU and PAE frame control*/ +/* Register for BPDU and PAE frame control */ #define MT753X_BPC 0x24 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) -enum mt753x_bpdu_port_fw { - MT753X_BPDU_FOLLOW_MFC, - MT753X_BPDU_CPU_EXCLUDE = 4, - MT753X_BPDU_CPU_INCLUDE = 5, - MT753X_BPDU_CPU_ONLY = 6, - MT753X_BPDU_DROP = 7, +/* Register for :03 and :0E MAC DA frame control */ +#define MT753X_RGAC2 0x2c +#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16) +#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x) + +enum mt753x_port_fw { + MT753X_PORT_FW_FOLLOW_MFC, + MT753X_PORT_FW_CPU_EXCLUDE = 4, + MT753X_PORT_FW_CPU_INCLUDE = 5, + MT753X_PORT_FW_CPU_ONLY = 6, + MT753X_PORT_FW_DROP = 7, }; /* Registers for address table access */ From patchwork Sun Jun 11 08:15:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13275130 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80CA9846C for ; Sun, 11 Jun 2023 08:16:27 +0000 (UTC) Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CA0635A3; Sun, 11 Jun 2023 01:16:22 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f736e0c9a8so23870395e9.2; Sun, 11 Jun 2023 01:16:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686471381; x=1689063381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MAnAZVSPifd50CdoCXOUbyrbAVvi3EcR5cj3t2QSLWo=; b=VWpJD6SlBaOq+NxDovnqEg9pbA5Wv2LBhEMXL+RwHvsFdlFYAPq0fhXrRJkFDLFZBU IDPwqt4hjHEf+vMfECOLQiufuUFGCIr9OHozjzaggbgBrqgnO0MZFHVka6OeJxrkB9ul KDYySLWGoU+wQgxDjVjbM1SSSzuvrkuNlZBfMdWoBGFYgUHY8A+v4M0uaIH0RN5aIi2i gq/T0vfQOSmZ30e/84v3I/5H0r2GDLWy6ZhQDWUSAGra5VIBqTt+vGAHut5pUDlXsOWM KBFHoQOSae+ZCtz7r0iNVCh/ioQOj+h5ckb0xafXy3J8FuJt51O2OusHne0zgKqfZcDN 2/ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686471381; x=1689063381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MAnAZVSPifd50CdoCXOUbyrbAVvi3EcR5cj3t2QSLWo=; b=SAchhMMheotz4P31SIwJAYwEGrn3IJEylI+WFRJw/qI3XXFaP0khTsFDN4a/f9P9IL AsMTRWGaiqJPCQ+UIpqXmHwzPdTCGexxXs+EpbHvrm/Nw6JiTcAHzKBFCbEYS1birgxK kNv/wsSQa9KNA8wyKyncL0N3hJafdjhpIaHHnPgoyE/k+Q80IsuxFvS5ugr9yPt53sq0 2Hfl+OKZJAmg+/rvrIglw9X+sWxoQgrvy4Y8ITSDvuNZLqeDjnKaSgHueFOwaJ7yhe4K YyqdIbXuZsHCKEppVad5wU64MYXVL+H6l9Sta75DkNHOarkFWk1AopP7g1KOaHcDID5Y 4v8A== X-Gm-Message-State: AC+VfDwPgBBDACQQgVBpPwITAfAHgPj/huPSusNld5oT5EBdPF/179cc X/cTGjsU+qKoWS5Zni/WKjY= X-Google-Smtp-Source: ACHHUZ4x9W1nwZTPcN9s8oBqrlu7DYRjTcc0l7HmZCbeh4/gNojpqubFNv9U0gnTVCHKu9r/rvm0yg== X-Received: by 2002:a05:600c:2190:b0:3f7:395e:46a2 with SMTP id e16-20020a05600c219000b003f7395e46a2mr3871261wme.16.1686471380957; Sun, 11 Jun 2023 01:16:20 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id s5-20020a7bc385000000b003f6132f95e6sm7748979wmj.35.2023.06.11.01.16.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:16:20 -0700 (PDT) From: " =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= " X-Google-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v2 6/7] net: dsa: introduce preferred_default_local_cpu_port and use on MT7530 Date: Sun, 11 Jun 2023 11:15:46 +0300 Message-Id: <20230611081547.26747-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611081547.26747-1-arinc.unal@arinc9.com> References: <20230611081547.26747-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org From: Vladimir Oltean Since the introduction of the OF bindings, DSA has always had a policy that in case multiple CPU ports are present in the device tree, the numerically smallest one is always chosen. The MT7530 switch family, except the switch on the MT7988 SoC, has 2 CPU ports, 5 and 6, where port 6 is preferable on the MT7531BE switch because it has higher bandwidth. The MT7530 driver developers had 3 options: - to modify DSA when the MT7531 switch support was introduced, such as to prefer the better port - to declare both CPU ports in device trees as CPU ports, and live with the sub-optimal performance resulting from not preferring the better port - to declare just port 6 in the device tree as a CPU port Of course they chose the path of least resistance (3rd option), kicking the can down the road. The hardware description in the device tree is supposed to be stable - developers are not supposed to adopt the strategy of piecemeal hardware description, where the device tree is updated in lockstep with the features that the kernel currently supports. Now, as a result of the fact that they did that, any attempts to modify the device tree and describe both CPU ports as CPU ports would make DSA change its default selection from port 6 to 5, effectively resulting in a performance degradation visible to users with the MT7531BE switch as can be seen below. Without preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 374 MBytes 157 Mbits/sec 734 sender [ 5][TX-C] 0.00-20.00 sec 373 MBytes 156 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 778 Mbits/sec 0 sender [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 777 Mbits/sec receiver With preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 856 Mbits/sec 273 sender [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 855 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.72 GBytes 737 Mbits/sec 15 sender [ 7][RX-C] 0.00-20.00 sec 1.71 GBytes 736 Mbits/sec receiver Using one port for WAN and the other ports for LAN is a very popular use case which is what this test emulates. As such, this change proposes that we retroactively modify stable kernels to keep the mt7530 driver preferring port 6 even with device trees where the hardware is more fully described. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Vladimir Oltean Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 15 +++++++++++++++ include/net/dsa.h | 8 ++++++++ net/dsa/dsa.c | 24 +++++++++++++++++++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 97f389f8d6ea..1ec047e552d2 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -399,6 +399,20 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); } +/* If port 6 is available as a CPU port, always prefer that as the default, + * otherwise don't care. + */ +static struct dsa_port * +mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp = dsa_to_port(ds, 6); + + if (dsa_port_is_cpu(cpu_dp)) + return cpu_dp; + + return NULL; +} + /* Setup port 6 interface mode and TRGMII TX circuit */ static int mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) @@ -3122,6 +3136,7 @@ static int mt7988_setup(struct dsa_switch *ds) const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, + .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, .get_strings = mt7530_get_strings, .get_ethtool_stats = mt7530_get_ethtool_stats, .get_sset_count = mt7530_get_sset_count, diff --git a/include/net/dsa.h b/include/net/dsa.h index 8903053fa5aa..ab0f0a5b0860 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -958,6 +958,14 @@ struct dsa_switch_ops { struct phy_device *phy); void (*port_disable)(struct dsa_switch *ds, int port); + /* + * Compatibility between device trees defining multiple CPU ports and + * drivers which are not OK to use by default the numerically smallest + * CPU port of a switch for its local ports. This can return NULL, + * meaning "don't know/don't care". + */ + struct dsa_port *(*preferred_default_local_cpu_port)(struct dsa_switch *ds); + /* * Port's MAC EEE settings */ diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c index ab1afe67fd18..1afed89e03c0 100644 --- a/net/dsa/dsa.c +++ b/net/dsa/dsa.c @@ -403,6 +403,24 @@ static int dsa_tree_setup_default_cpu(struct dsa_switch_tree *dst) return 0; } +static struct dsa_port * +dsa_switch_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp; + + if (!ds->ops->preferred_default_local_cpu_port) + return NULL; + + cpu_dp = ds->ops->preferred_default_local_cpu_port(ds); + if (!cpu_dp) + return NULL; + + if (WARN_ON(!dsa_port_is_cpu(cpu_dp) || cpu_dp->ds != ds)) + return NULL; + + return cpu_dp; +} + /* Perform initial assignment of CPU ports to user ports and DSA links in the * fabric, giving preference to CPU ports local to each switch. Default to * using the first CPU port in the switch tree if the port does not have a CPU @@ -410,12 +428,16 @@ static int dsa_tree_setup_default_cpu(struct dsa_switch_tree *dst) */ static int dsa_tree_setup_cpu_ports(struct dsa_switch_tree *dst) { - struct dsa_port *cpu_dp, *dp; + struct dsa_port *preferred_cpu_dp, *cpu_dp, *dp; list_for_each_entry(cpu_dp, &dst->ports, list) { if (!dsa_port_is_cpu(cpu_dp)) continue; + preferred_cpu_dp = dsa_switch_preferred_default_local_cpu_port(cpu_dp->ds); + if (preferred_cpu_dp && preferred_cpu_dp != cpu_dp) + continue; + /* Prefer a local CPU port */ dsa_switch_for_each_port(dp, cpu_dp->ds) { /* Prefer the first local CPU port found */ From patchwork Sun Jun 11 08:15:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13275131 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6C661FB5 for ; Sun, 11 Jun 2023 08:16:40 +0000 (UTC) Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4043A3589; Sun, 11 Jun 2023 01:16:30 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3f623adec61so34073285e9.0; Sun, 11 Jun 2023 01:16:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686471388; x=1689063388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=905cpt816UbdZmkAKTALR8SANtBmtQIMIITLaVtiS6c=; b=h/MSSj10JRL6ApDF6iyYGMohmvTHQ3M+eHoRkh5i7V7TCeqBorEhray69e0r/hc5lV JtI8UypsimaqLqMVlgh1J/hxp+Qu2Y3DXmorq0GSaanD8hRfUAgrBf687XK9fZ13xj6j NucacfbiQlUsN4KcOJ7qXcNTI7KPuV0s892RSQwqGSTl6nzOCPnaAIQTUXSTBGll/Pyv BY166lKAQ+32ZfTUWp4EIJmMkWbC0gCH+pnCRXhaHvsfq8Q9mgq1Rzr3OjheYvHqqAuU bhU9i3vcBPLmYQc8Uu3mZ4xFJpAv5fS4dynHzvgrDRxjImAtwG60KFq3d4TwPOeWTLq2 46ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686471388; x=1689063388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=905cpt816UbdZmkAKTALR8SANtBmtQIMIITLaVtiS6c=; b=OsRB9kaswIALZ4bzQggn4++beUN4Bi27X2qQVDaoLF0mRQtR7nFLB+bhpEovRrI2FE xysbotJtysj+Q6F1/jKUHWCHpIqnGYWvaRLZLqFNCPrA6gLvSwce2Az+ZDAckdYTBMRh 04K1qTw+jphpYbepv6ASBR8EeOgqz4S2M5L++w2gXurhbdIOMdrXWqsmRUQ/zaHls3KJ IGnoiq6vVi+QoUeomYEfElYC3S7QjoH3U/Q/aogkz9Y2lJL9dAoGErp0/duwVxY7L+nt OYDbF5jZh3dmX6XhhWVZGa6duh/eaOXPHs4JXPHF/EG8isR+QKTbWrNONKgHPgcEComu QIyw== X-Gm-Message-State: AC+VfDwpaEPqtAK8Hg7PvfCtYlumEiYnMO/ZRevOS4IV380RgT2TzeAp oqw/6LfD2Q4NFqBXy/whbWc= X-Google-Smtp-Source: ACHHUZ5UKivwW7FrZH24UXmp1MZ5paa9KqLvGS94uFeZPAjfJ06aSKFu6O7nwjmYS7Koeofs9Q1RUQ== X-Received: by 2002:a05:600c:21c7:b0:3f5:fb98:729e with SMTP id x7-20020a05600c21c700b003f5fb98729emr4963298wmj.22.1686471383710; Sun, 11 Jun 2023 01:16:23 -0700 (PDT) Received: from arinc9-Xeront.lan (178-147-169-233.haap.dm.cosmote.net. [178.147.169.233]) by smtp.gmail.com with ESMTPSA id s5-20020a7bc385000000b003f6132f95e6sm7748979wmj.35.2023.06.11.01.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 01:16:23 -0700 (PDT) From: " =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= " X-Google-Original-From: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= To: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: Landen Chao , Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net v2 7/7] MAINTAINERS: add me as maintainer of MEDIATEK SWITCH DRIVER Date: Sun, 11 Jun 2023 11:15:47 +0300 Message-Id: <20230611081547.26747-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230611081547.26747-1-arinc.unal@arinc9.com> References: <20230611081547.26747-1-arinc.unal@arinc9.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add me as a maintainer of the MediaTek MT7530 DSA subdriver. List maintainers in alphabetical order by first name. Signed-off-by: Arınç ÜNAL Reviewed-by: Vladimir Oltean --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a73e5a98503a..c58d7fbb40ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13259,10 +13259,11 @@ F: drivers/memory/mtk-smi.c F: include/soc/mediatek/smi.h MEDIATEK SWITCH DRIVER -M: Sean Wang +M: Arınç ÜNAL +M: Daniel Golle M: Landen Chao M: DENG Qingfang -M: Daniel Golle +M: Sean Wang L: netdev@vger.kernel.org S: Maintained F: drivers/net/dsa/mt7530-mdio.c