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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" "low" was written "lov", fix this. Fixes: 99d33ee61cb0 ("arm64: dts: qcom: sm8550: Add missing RPMhPD OPP levels") Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 75cd374943eb..972df1ef86ee 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3649,15 +3649,15 @@ rpmhpd_opp_min_svs: opp-48 { opp-level = ; }; - rpmhpd_opp_lov_svs_d2: opp-52 { + rpmhpd_opp_low_svs_d2: opp-52 { opp-level = ; }; - rpmhpd_opp_lov_svs_d1: opp-56 { + rpmhpd_opp_low_svs_d1: opp-56 { opp-level = ; }; - rpmhpd_opp_lov_svs_d0: opp-60 { + rpmhpd_opp_low_svs_d0: opp-60 { opp-level = ; }; From patchwork Mon Jun 12 15:26:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13276855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF32AC88CB6 for ; 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Mon, 12 Jun 2023 08:26:47 -0700 (PDT) From: Neil Armstrong Date: Mon, 12 Jun 2023 17:26:41 +0200 Subject: [PATCH v3 2/2] arm64: dts: qcom: sm8550: add display port nodes MIME-Version: 1.0 Message-Id: <20230601-topic-sm8550-upstream-dp-v3-2-5f9ffdcb8369@linaro.org> References: <20230601-topic-sm8550-upstream-dp-v3-0-5f9ffdcb8369@linaro.org> In-Reply-To: <20230601-topic-sm8550-upstream-dp-v3-0-5f9ffdcb8369@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Andy Gross , Bjorn Andersson , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3472; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=OT9fRI9abb+RycwRAR3WBnAhUBfEPjR/71I2pAue+x4=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkhzkzNMCe8HsWmMOH3B20DVFcSIBhFzdJrkQ+SEgW 5AkwBfCJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZIc5MwAKCRB33NvayMhJ0eDwD/ 9zdODZUvqdgFl9NF0db1A4Ghx6Zfx0diVgO3rjcprByoxdgIz0LqJhT5ySkTNQneTWr/Uz5gm6+DhM 5i7Nw+ORnQhKYqT5FMPlRE13yuS4VBb7I0GKqBkKQ3BZMhZqhzTEYtc6pU98oTAH5GTiYl1aymCxoA u1VycC8eWP4EJj4ib6/X2MjOdNmrhvixPn+bvXkiMvxI6qI5xisrYZPLUdtvQbsGaMQtHcVTKtnNuC iajYn2WthnCHgOiANjlRcB8B+O4PwavyRg0oAgNC3IiFXNQeXOVNW3C7q8CCL/9Edhzunva84e+Pa+ IqiJlPY7M3jACH3V50NQVusNAT3k0GVROyHagYMcZ5AQjVLr6hVVySnmsiv7z5qTIqtCIBQhz1RqL6 JF4yg7EfUKp7KaTWtnsPlfhZLnnivm89iVYWwE9YrGyrUJAAm8dvnJRDn/UKwWNmbvUn1l51QqYPwE XRjJQrjJzH88co0Fs0hdb2fmae9mALK7im+iSAGl7urR7c9X8MVGRJm1xRoJY5m1w0x+/oeFS/oS/G WieLzgdd46wMz5ZkbBKU4ZooFhBtcGDWUUSk8RqgIv/mGtdBpRoLi8unp5vTILXtU+oIu/SSxd/og1 UwD/H90N5uzEWAVA6BZVKVr88kQbaBhCMw3+KjTeYA7EmjR8tyyMZ4QSsn2Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the Display Port controller subnode to the MDSS node. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 89 +++++++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 972df1ef86ee..b41b3981b3ce 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2495,6 +2495,13 @@ dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2522,6 +2529,84 @@ opp-514000000 { }; }; + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dp0_out: endpoint { + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; @@ -2705,8 +2790,8 @@ dispcc: clock-controller@af00000 { <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, /* dp0 */ - <0>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ <0>, <0>, /* dp2 */