From patchwork Tue Jun 13 07:04:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278072 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9301C7EE2E for ; Tue, 13 Jun 2023 07:12:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 121EE10E32B; Tue, 13 Jun 2023 07:12:23 +0000 (UTC) X-Greylist: delayed 426 seconds by postgrey-1.36 at gabe; Tue, 13 Jun 2023 07:12:20 UTC Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id A79EF10E32B for ; Tue, 13 Jun 2023 07:12:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686640341; x=1718176341; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fRjFS0tyWhibQ8jFtctjzfuGuQJU7LCgPahmmxu6a7A=; b=kvDXdUSsW9bjChoU7pKfaFq1zG6sAGOHHIcdt1/guHgEn4Il4muKr+IW WWbBj7od1HVZG0v2GokTe5izXtYMSP43pvVA088revfCDOMCpkYoUHg8T z1UpFUvbMNIFx7YUSwAmbaeUK1O3pNNCyG9wzDQE85tJcx8HFqDea7boj jj3IUmuD8ht7Svn7TB2ZpAnbSYk6vK48yl4mEq35/ASkXNCk1SbZ5zWfu n1SG0I/tV9H1jWV3V8/4kxu+krHFBNnaVjQATiYbqbU3YOLrW7RSg71iv lg3tA6ZqzBDdvfkkB6TAXQS0rkHcu5FCi0tRCMC+LMxn0BzRmgyySAyBt g==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="218182139" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:05:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:11 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:02 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Subject: [PATCH 1/9] dt-bindings: mfd: Add bindings for SAM9X7 LCD controller Date: Tue, 13 Jun 2023 12:34:18 +0530 Message-ID: <20230613070426.467389-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai.ManickamKR@microchip.com, Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add new compatible string for the XLCD controller on SAM9X7 SoC. Signed-off-by: Manikandan Muralidharan Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt index 5f8880cc757e..7c77b6bf4adb 100644 --- a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt @@ -8,6 +8,7 @@ Required properties: "atmel,sama5d3-hlcdc" "atmel,sama5d4-hlcdc" "microchip,sam9x60-hlcdc" + "microchip,sam9x7-xlcdc" - reg: base address and size of the HLCDC device registers. - clock-names: the name of the 3 clocks requested by the HLCDC device. Should contain "periph_clk", "sys_clk" and "slow_clk". From patchwork Tue Jun 13 07:04:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278074 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC4A8C7EE2E for ; Tue, 13 Jun 2023 07:12:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EA31B10E32D; Tue, 13 Jun 2023 07:12:49 +0000 (UTC) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9679A10E32D for ; Tue, 13 Jun 2023 07:12:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686640369; x=1718176369; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dcrpTo/oO6xJJBlzsj5b3KkyljFQ24twXs1imiPXrW8=; b=HDtwOOcyDOoeMV2deThg4qB52UxOjCfX9Jd9qrZtYg3pX35/BZNZ2x7a FcVTohfkbPopH8XAJ39RDsLAnLwPpHBEVvY7tJEVcazXbETPRpCb57wP/ RLG/9yEqdry0reS+si0eSEkX6O4SWT8FiaFSjZFzMZuQRrBokm0aQaDVP ayMkMOzutg8GBDSbuVJ/X3tA9tkzL6TgENjjJF9VRoJrSPSVMET7RtmDN 71f2QOgUsT+f+CjB0Oh2T+TqSVZy+5/+QWs24zqAKNa2a+DdEhY6xBgJ+ 3VZhyezWP4bNi4/SSfL6olnlwqIa980TJPQnRROoUf7UuLF9mcb5kMu0i w==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="218182226" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:05:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:20 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:11 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Subject: [PATCH 2/9] mfd: atmel-hlcdc: Add compatible for SAM9X7 HLCD controller Date: Tue, 13 Jun 2023 12:34:19 +0530 Message-ID: <20230613070426.467389-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai.ManickamKR@microchip.com, Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add compatible for SAM9X7 HLCD controller. Signed-off-by: Manikandan Muralidharan --- drivers/mfd/atmel-hlcdc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c index 3c2414ba4b01..8755c91ce854 100644 --- a/drivers/mfd/atmel-hlcdc.c +++ b/drivers/mfd/atmel-hlcdc.c @@ -141,6 +141,7 @@ static const struct of_device_id atmel_hlcdc_match[] = { { .compatible = "atmel,sama5d3-hlcdc" }, { .compatible = "atmel,sama5d4-hlcdc" }, { .compatible = "microchip,sam9x60-hlcdc" }, + { .compatible = "microchip,sam9x7-xlcdc" }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_hlcdc_match); From patchwork Tue Jun 13 07:04:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65DE6C7EE2E for ; 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X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="218182246" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:05:45 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:29 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:20 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Subject: [PATCH 3/9] drm: atmel-hlcdc: add LCD controller layer definition for SAM9X7 Date: Tue, 13 Jun 2023 12:34:20 +0530 Message-ID: <20230613070426.467389-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai.ManickamKR@microchip.com, Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the LCD controller layer definition and descriptor structure for SAM9X7 for the following layers, - Base Layer - Overlay1 Layer - Overlay2 Layer - High End Overlay Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 96 ++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index fa0f9a93d50d..d7ad828e9e8c 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -462,6 +462,98 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = { .layers = atmel_hlcdc_sam9x60_layers, }; +static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x7_layers[] = { + { + .name = "base", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x60, + .id = 0, + .type = ATMEL_HLCDC_BASE_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .xstride = { 2 }, + .default_color = 3, + .general_config = 4, + .disc_pos = 5, + .disc_size = 6, + }, + .clut_offset = 0x700, + }, + { + .name = "overlay1", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x160, + .id = 1, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + .clut_offset = 0xb00, + }, + { + .name = "overlay2", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x260, + .id = 2, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + .clut_offset = 0xf00, + }, + { + .name = "high-end-overlay", + .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats, + .regs_offset = 0x360, + .id = 3, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x30, + .layout = { + .pos = 2, + .size = 3, + .memsize = 4, + .xstride = { 5, 7 }, + .pstride = { 6, 8 }, + .default_color = 9, + .chroma_key = 10, + .chroma_key_mask = 11, + .general_config = 12, + .csc = 16, + .scaler_config = 23, + }, + .clut_offset = 0x1300, + }, +}; + +static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x7 = { + .min_width = 0, + .min_height = 0, + .max_width = 2048, + .max_height = 2048, + .max_spw = 0xff, + .max_vpw = 0xff, + .max_hpw = 0x3ff, + .fixed_clksrc = true, + .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x7_layers), + .layers = atmel_xlcdc_sam9x7_layers, +}; + static const struct of_device_id atmel_hlcdc_of_match[] = { { .compatible = "atmel,at91sam9n12-hlcdc", @@ -487,6 +579,10 @@ static const struct of_device_id atmel_hlcdc_of_match[] = { .compatible = "microchip,sam9x60-hlcdc", .data = &atmel_hlcdc_dc_sam9x60, }, + { + .compatible = "microchip,sam9x7-xlcdc", + .data = &atmel_xlcdc_dc_sam9x7, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match); From patchwork Tue Jun 13 07:04:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21A02C77B7A for ; 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X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="217553976" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:05:38 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:38 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:29 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Subject: [PATCH 4/9] drm: atmel-hlcdc: Define SAM9X7 XLCDC specific registers Date: Tue, 13 Jun 2023 12:34:21 +0530 Message-ID: <20230613070426.467389-5-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai Manickam KR , Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Durai Manickam KR The register address of the XLCDC IP used in SAM9X7 are different from the previous HLCDC.Defining those address space with valid macros. Signed-off-by: Durai Manickam KR [manikandan.m@microchip.com: Remove unused macro definitions] Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 108 +++++++++++++++++++ include/linux/mfd/atmel-hlcdc.h | 10 ++ 2 files changed, 118 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 5b5c774e0edf..aed1742b3665 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -15,6 +15,7 @@ #include +/* LCD controller common registers */ #define ATMEL_HLCDC_LAYER_CHER 0x0 #define ATMEL_HLCDC_LAYER_CHDR 0x4 #define ATMEL_HLCDC_LAYER_CHSR 0x8 @@ -128,6 +129,113 @@ #define ATMEL_HLCDC_MAX_LAYERS 6 +/* XLCDC controller specific registers */ +#define ATMEL_XLCDC_LAYER_ENR 0x10 +#define ATMEL_XLCDC_LAYER_EN BIT(0) + +#define ATMEL_XLCDC_LAYER_IER 0x0 +#define ATMEL_XLCDC_LAYER_IDR 0x4 +#define ATMEL_XLCDC_LAYER_IMR 0x8 +#define ATMEL_XLCDC_LAYER_ISR 0xc +#define ATMEL_XLCDC_LAYER_DONE_IRQ(p) BIT(0 + (8 * (p))) +#define ATMEL_XLCDC_LAYER_ERROR_IRQ(p) BIT(1 + (8 * (p))) +#define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p))) + +#define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18) + +#define ATMEL_XLCDC_LAYER_DMA_CFG 0 +#define ATMEL_XLCDC_LAYER_DMA_BLEN_MASK GENMASK(6, 4) +#define ATMEL_XLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4) +#define ATMEL_XLCDC_LAYER_DMA_BLEN_INCR32 (4 << 4) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_MASK GENMASK(10, 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_SINGLE (0 << 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR4 (1 << 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR8 (2 << 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR16 (3 << 8) +#define ATMEL_XLCDC_LAYER_DMA_BLENCC_INCR32 (4 << 8) + +#define ATMEL_XLCDC_GAM BIT(2) + +#define ATMEL_XLCDC_LAYER_POS(x, y) ((x) | ((y) << 16)) +#define ATMEL_XLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16)) + +#define ATMEL_XLCDC_LAYER_DMA BIT(0) +#define ATMEL_XLCDC_LAYER_REP BIT(1) +#define ATMEL_XLCDC_LAYER_CRKEY BIT(2) +#define ATMEL_XLCDC_LAYER_DSTKEY BIT(3) +#define ATMEL_XLCDC_LAYER_DISCEN BIT(4) +#define ATMEL_XLCDC_LAYER_VIDPRI BIT(5) +#define ATMEL_XLCDC_LAYER_SFACTC_MASK GENMASK(8, 6) +#define ATMEL_XLCDC_LAYER_SFACTC_ONE (0 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_ZERO (1 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_A0 (2 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AD (3 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6) +#define ATMEL_XLCDC_LAYER_SFACTC_M_A0_MULT_AD (5 << 6) +#define ATMEL_XLCDC_LAYER_SFACTA_MASK GENMASK(10, 9) +#define ATMEL_XLCDC_LAYER_SFACTA_ZERO (0 << 9) +#define ATMEL_XLCDC_LAYER_SFACTA_ONE (1 << 9) +#define ATMEL_XLCDC_LAYER_SFACTA_A0 (2 << 9) +#define ATMEL_XLCDC_LAYER_SFACTA_A1 (3 << 9) +#define ATMEL_XLCDC_LAYER_DFACTC_MASK GENMASK(13, 11) +#define ATMEL_XLCDC_LAYER_DFACTC_ZERO (0 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_ONE (1 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_A0 (2 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_A1 (3 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_A0_MULT_AD (4 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AD (5 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11) +#define ATMEL_XLCDC_LAYER_DFACTC_M_A0 (7 << 11) +#define ATMEL_XLCDC_LAYER_DFACTA_MASK GENMASK(15, 14) +#define ATMEL_XLCDC_LAYER_DFACTA_ZERO (0 << 14) +#define ATMEL_XLCDC_LAYER_DFACTA_ONE (1 << 14) +#define ATMEL_XLCDC_LAYER_DFACTA_M_A0_MULT_AS (2 << 14) +#define ATMEL_XLCDC_LAYER_DFACTA_A1 (3 << 14) +#define ATMEL_XLCDC_LAYER_A0_SHIFT 16 +#define ATMEL_XLCDC_LAYER_A0_MASK \ + GENMASK(23, ATMEL_XLCDC_LAYER_A0_SHIFT) +#define ATMEL_XLCDC_LAYER_A0(x) \ + ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT) +#define ATMEL_XLCDC_LAYER_A1_SHIFT 24 +#define ATMEL_XLCDC_LAYER_A1_MASK \ + GENMASK(31, ATMEL_XLCDC_LAYER_A1_SHIFT) +#define ATMEL_XLCDC_LAYER_A1(x) \ + ((x) << ATMEL_XLCDC_LAYER_A1_SHIFT) + +#define ATMEL_XLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16)) +#define ATMEL_XLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16)) + +#define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0) +#define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1) +#define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5) + +#define ATMEL_XLCDC_LAYER_VXSYCFG_ZERO (0 << 0) +#define ATMEL_XLCDC_LAYER_VXSYCFG_ONE (1 << 0) +#define ATMEL_XLCDC_LAYER_VXSYCFG_TWO (2 << 0) +#define ATMEL_XLCDC_LAYER_VXSYCFG_THREE (3 << 0) +#define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_VXSYBICU_ENABLE BIT(5) +#define ATMEL_XLCDC_LAYER_VXSCCFG_ZERO (0 << 16) +#define ATMEL_XLCDC_LAYER_VXSCCFG_ONE (1 << 16) +#define ATMEL_XLCDC_LAYER_VXSCCFG_TWO (2 << 16) +#define ATMEL_XLCDC_LAYER_VXSCCFG_THREE (3 << 16) +#define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20) +#define ATMEL_XLCDC_LAYER_VXSCBICU_ENABLE BIT(21) + +#define ATMEL_XLCDC_LAYER_HXSYCFG_ZERO (0 << 0) +#define ATMEL_XLCDC_LAYER_HXSYCFG_ONE (1 << 0) +#define ATMEL_XLCDC_LAYER_HXSYCFG_TWO (2 << 0) +#define ATMEL_XLCDC_LAYER_HXSYCFG_THREE (3 << 0) +#define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4) +#define ATMEL_XLCDC_LAYER_HXSYBICU_ENABLE BIT(5) +#define ATMEL_XLCDC_LAYER_HXSCCFG_ZERO (0 << 16) +#define ATMEL_XLCDC_LAYER_HXSCCFG_ONE (1 << 16) +#define ATMEL_XLCDC_LAYER_HXSCCFG_TWO (2 << 16) +#define ATMEL_XLCDC_LAYER_HXSCCFG_THREE (3 << 16) +#define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20) +#define ATMEL_XLCDC_LAYER_HXSCBICU_ENABLE BIT(21) + /** * Atmel HLCDC Layer registers layout structure * diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h index a186119a49b5..80d675a03b39 100644 --- a/include/linux/mfd/atmel-hlcdc.h +++ b/include/linux/mfd/atmel-hlcdc.h @@ -22,6 +22,8 @@ #define ATMEL_HLCDC_DITHER BIT(6) #define ATMEL_HLCDC_DISPDLY BIT(7) #define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8) +#define ATMEL_XLCDC_MODE_MASK GENMASK(10, 8) +#define ATMEL_XLCDC_DPI BIT(11) #define ATMEL_HLCDC_PP BIT(10) #define ATMEL_HLCDC_VSPSU BIT(12) #define ATMEL_HLCDC_VSPHO BIT(13) @@ -34,6 +36,12 @@ #define ATMEL_HLCDC_IDR 0x30 #define ATMEL_HLCDC_IMR 0x34 #define ATMEL_HLCDC_ISR 0x38 +#define ATMEL_XLCDC_ATTRE 0x3c + +#define ATMEL_XLCDC_BASE_UPDATE BIT(0) +#define ATMEL_XLCDC_OVR1_UPDATE BIT(1) +#define ATMEL_XLCDC_OVR3_UPDATE BIT(2) +#define ATMEL_XLCDC_HEO_UPDATE BIT(3) #define ATMEL_HLCDC_CLKPOL BIT(0) #define ATMEL_HLCDC_CLKSEL BIT(2) @@ -48,6 +56,8 @@ #define ATMEL_HLCDC_DISP BIT(2) #define ATMEL_HLCDC_PWM BIT(3) #define ATMEL_HLCDC_SIP BIT(4) +#define ATMEL_XLCDC_SD BIT(5) +#define ATMEL_XLCDC_CM BIT(6) #define ATMEL_HLCDC_SOF BIT(0) #define ATMEL_HLCDC_SYNCDIS BIT(1) From patchwork Tue Jun 13 07:04:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org 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, , , , , , , Subject: [PATCH 5/9] drm: atmel-hlcdc: add compatible string check for XLCDC and HLCDC Date: Tue, 13 Jun 2023 12:34:22 +0530 Message-ID: <20230613070426.467389-6-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai Manickam KR , Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Durai Manickam KR Add compatible string check to differentiate XLCDC and HLCDC code within the atmel-hlcdc driver files. Signed-off-by: Durai Manickam KR Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 7 +++++++ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index d7ad828e9e8c..fbbd2592efc7 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -761,6 +761,13 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev) if (!dc) return -ENOMEM; + /* SAM9X7 supports XLCDC */ + if (!strcmp(match->compatible, "microchip,sam9x7-xlcdc")) + dc->is_xlcdc = true; + else + /* Other SoC's that supports HLCDC IP */ + dc->is_xlcdc = false; + dc->desc = match->data; dc->hlcdc = dev_get_drvdata(dev->dev->parent); dev->dev_private = dc; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index aed1742b3665..804e4d476f2b 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -451,6 +451,7 @@ struct atmel_hlcdc_dc { u32 imr; struct drm_atomic_state *state; } suspend; + bool is_xlcdc; }; extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; From patchwork Tue Jun 13 07:04:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75BD7C77B7A for ; Tue, 13 Jun 2023 07:13:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BE94710E333; Tue, 13 Jun 2023 07:13:22 +0000 (UTC) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0244B10E332 for ; Tue, 13 Jun 2023 07:13:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686640398; x=1718176398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EXoJDlE0rvVHtvzhro8MbvcrVWmqxytqo57znv5RaEU=; b=e0EXZC4cbB5+c4/xYO3alfAzsvrOOYa9nZz0XVwmYVQYqJVx+NjJGyez xPcUVawDfEvB0ehGPLVULNHKGJlnTuLxh4PM9HB1PVyK0jdljWIWxqGpK 9+Qqc+JN9L7VaHlzk6lRqDoz6mHLOq358ZoeRCt0jqJCEyFlavHOm/na0 JLazrO5SGuzm5VSV2IudrOszh4F365UCkvOVMt/krzVBfw6GDYWe2LNdC qSUua2XVcJRKg1KH9nlXsS96UDs00LtRr0uLD5d/6TKqlcPpSREeG04mG Gl0fQCb6nttlaBatHGqf3OEn6kxUKUajqzMiZ51ZFBX9z/TGteTZ0M/LH w==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="229806880" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:06:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:05:56 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:47 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Subject: [PATCH 6/9] drm: atmel_hlcdc: Add support for XLCDC in atmel LCD driver Date: Tue, 13 Jun 2023 12:34:23 +0530 Message-ID: <20230613070426.467389-7-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai Manickam KR , Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" - XLCDC in SAM9X7 has different sets of registers and additional configuration bits when compared to previous HLCDC IP. Read/write operation on the controller registers is now separated using the XLCDC status flag. - HEO scaling, window resampling, Alpha blending, YUV-to-RGB conversion in XLCDC is derived and handled using additional configuration bits and registers. - Writing one to the Enable fields of each layer in LCD_ATTRE is required to reflect the values set in Configuration, FBA, Enable registers of each layer Signed-off-by: Manikandan Muralidharan [Hari.PrasathGE@microchip.com: update the attribute field for each layer] Signed-off-by: Hari Prasath Gujulan Elango [durai.manickamkr@microchip.com: implement status flag to seprate register update] Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 28 +- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 297 ++++++++++++++---- 2 files changed, 256 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 58184cd6ab0b..7c9cf7c0c75d 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -139,10 +139,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); cfg = state->output_mode << 8; - if (adj->flags & DRM_MODE_FLAG_NVSYNC) + if (!crtc->dc->is_xlcdc && (adj->flags & DRM_MODE_FLAG_NVSYNC)) cfg |= ATMEL_HLCDC_VSPOL; - if (adj->flags & DRM_MODE_FLAG_NHSYNC) + if (!crtc->dc->is_xlcdc && (adj->flags & DRM_MODE_FLAG_NHSYNC)) cfg |= ATMEL_HLCDC_HSPOL; regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5), @@ -177,6 +177,18 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, pm_runtime_get_sync(dev->dev); + if (crtc->dc->is_xlcdc) { + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_CM); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + (status & ATMEL_XLCDC_CM)) + cpu_relax(); + + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_SD); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + !(status & ATMEL_XLCDC_SD)) + cpu_relax(); + } + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP); while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && (status & ATMEL_HLCDC_DISP)) @@ -231,6 +243,18 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, !(status & ATMEL_HLCDC_DISP)) cpu_relax(); + if (crtc->dc->is_xlcdc) { + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_CM); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + !(status & ATMEL_XLCDC_CM)) + cpu_relax(); + + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_SD); + while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && + (status & ATMEL_XLCDC_SD)) + cpu_relax(); + } + pm_runtime_put_sync(dev->dev); } diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index daa508504f47..fe33476818c4 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -330,11 +330,59 @@ static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, yfactor)); } +static void atmel_xlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, + struct atmel_hlcdc_plane_state *state) +{ + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; + u32 xfactor, yfactor; + + if (!desc->layout.scaler_config) + return; + + if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.scaler_config, 0); + return; + } + + /* xfactor = round[(2^20 * XMEMSIZE)/XSIZE)] */ + xfactor = (1048576 * state->src_w) / state->crtc_w; + + /* yfactor = round[(2^20 * YMEMSIZE)/YSIZE)] */ + yfactor = (1048576 * state->src_h) / state->crtc_h; + + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, + ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE | + ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE | + ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE | + ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE); + + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1, + yfactor); + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3, + xfactor); + + /* As per YCbCr window resampling configuration */ + if (state->base.fb->format->format == DRM_FORMAT_YUV420) { + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, + yfactor / 2); + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, + xfactor / 2); + } else { + /* As per ARGB window resampling configuration */ + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, + yfactor); + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, + xfactor); + } +} + static void atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) { const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; if (desc->layout.size) atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size, @@ -352,7 +400,10 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, ATMEL_HLCDC_LAYER_POS(state->crtc_x, state->crtc_y)); - atmel_hlcdc_plane_setup_scaler(plane, state); + if (!(dc->is_xlcdc)) + atmel_hlcdc_plane_setup_scaler(plane, state); + else + atmel_xlcdc_plane_setup_scaler(plane, state); } static void @@ -362,33 +413,58 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, unsigned int cfg = ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id; const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; const struct drm_format_info *format = state->base.fb->format; - + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; /* * Rotation optimization is not working on RGB888 (rotation is still * working but without any optimization). */ - if (format->format == DRM_FORMAT_RGB888) + if ((!(dc->is_xlcdc)) && format->format == DRM_FORMAT_RGB888) cfg |= ATMEL_HLCDC_LAYER_DMA_ROTDIS; - atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG, - cfg); + if (!(dc->is_xlcdc)) { + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG, + cfg); - cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP; + cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP; + } else { + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_XLCDC_LAYER_DMA_CFG, + cfg); + + cfg = ATMEL_XLCDC_LAYER_DMA | ATMEL_XLCDC_LAYER_REP; + } if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) { - cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL | - ATMEL_HLCDC_LAYER_ITER; + if (!(dc->is_xlcdc)) { + cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL | + ATMEL_HLCDC_LAYER_ITER; + + if (format->has_alpha) + cfg |= ATMEL_HLCDC_LAYER_LAEN; + else + cfg |= ATMEL_HLCDC_LAYER_GAEN | + ATMEL_HLCDC_LAYER_GA(state->base.alpha); + } else { + /* + * Alpha Blending bits specific to SAM9X7 SoC + */ + cfg |= ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS | + ATMEL_XLCDC_LAYER_SFACTA_ONE | + ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS | + ATMEL_XLCDC_LAYER_DFACTA_ONE; + if (format->has_alpha) + cfg |= ATMEL_XLCDC_LAYER_A0(0xff); + else + cfg |= ATMEL_XLCDC_LAYER_A0(state->base.alpha); + } + } - if (format->has_alpha) - cfg |= ATMEL_HLCDC_LAYER_LAEN; + if (state->disc_h && state->disc_w) { + if (!(dc->is_xlcdc)) + cfg |= ATMEL_HLCDC_LAYER_DISCEN; else - cfg |= ATMEL_HLCDC_LAYER_GAEN | - ATMEL_HLCDC_LAYER_GA(state->base.alpha); + cfg |= ATMEL_XLCDC_LAYER_DISCEN; } - if (state->disc_h && state->disc_w) - cfg |= ATMEL_HLCDC_LAYER_DISCEN; - atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config, cfg); } @@ -441,33 +517,42 @@ static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane, struct atmel_hlcdc_plane_state *state) { const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; struct drm_framebuffer *fb = state->base.fb; u32 sr; int i; - sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); + if (!(dc->is_xlcdc)) + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); + else + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR); for (i = 0; i < state->nplanes; i++) { struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i); state->dscrs[i]->addr = gem->dma_addr + state->offsets[i]; - atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_HEAD(i), - state->dscrs[i]->self); - - if (!(sr & ATMEL_HLCDC_LAYER_EN)) { - atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_ADDR(i), - state->dscrs[i]->addr); + if (!(dc->is_xlcdc)) { atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_CTRL(i), - state->dscrs[i]->ctrl); + ATMEL_HLCDC_LAYER_PLANE_HEAD(i), + state->dscrs[i]->self); + + if (!(sr & ATMEL_HLCDC_LAYER_EN)) { + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_ADDR(i), + state->dscrs[i]->addr); + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_CTRL(i), + state->dscrs[i]->ctrl); + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_PLANE_NEXT(i), + state->dscrs[i]->self); + } + } else { atmel_hlcdc_layer_write_reg(&plane->layer, - ATMEL_HLCDC_LAYER_PLANE_NEXT(i), - state->dscrs[i]->self); + ATMEL_XLCDC_LAYER_PLANE_ADDR(i), + state->dscrs[i]->addr); } - if (desc->layout.xstride[i]) atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.xstride[i], @@ -716,19 +801,31 @@ static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, struct drm_atomic_state *state) { struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); - + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; /* Disable interrupts */ - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR, - 0xffffffff); + if (!(dc->is_xlcdc)) + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR, + 0xffffffff); + else + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IDR, + 0xffffffff); /* Disable the layer */ - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHDR, - ATMEL_HLCDC_LAYER_RST | - ATMEL_HLCDC_LAYER_A2Q | - ATMEL_HLCDC_LAYER_UPDATE); + if (!(dc->is_xlcdc)) + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_HLCDC_LAYER_CHDR, + ATMEL_HLCDC_LAYER_RST | + ATMEL_HLCDC_LAYER_A2Q | + ATMEL_HLCDC_LAYER_UPDATE); + else + atmel_hlcdc_layer_write_reg(&plane->layer, + ATMEL_XLCDC_LAYER_ENR, 0); /* Clear all pending interrupts */ - atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + if (!(dc->is_xlcdc)) + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + else + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); } static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, @@ -739,6 +836,7 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); struct atmel_hlcdc_plane_state *hstate = drm_plane_state_to_atmel_hlcdc_plane_state(new_s); + struct atmel_hlcdc_dc *dc = p->dev->dev_private; u32 sr; if (!new_s->crtc || !new_s->fb) @@ -756,23 +854,46 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, atmel_hlcdc_plane_update_buffers(plane, hstate); atmel_hlcdc_plane_update_disc_area(plane, hstate); - /* Enable the overrun interrupts. */ - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, - ATMEL_HLCDC_LAYER_OVR_IRQ(0) | - ATMEL_HLCDC_LAYER_OVR_IRQ(1) | - ATMEL_HLCDC_LAYER_OVR_IRQ(2)); - - /* Apply the new config at the next SOF event. */ - sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, - ATMEL_HLCDC_LAYER_UPDATE | - (sr & ATMEL_HLCDC_LAYER_EN ? - ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); + if (!(dc->is_xlcdc)) { + /* Enable the overrun interrupts. */ + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, + ATMEL_HLCDC_LAYER_OVR_IRQ(0) | + ATMEL_HLCDC_LAYER_OVR_IRQ(1) | + ATMEL_HLCDC_LAYER_OVR_IRQ(2)); + + /* Apply the new config at the next SOF event. */ + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, + ATMEL_HLCDC_LAYER_UPDATE | + (sr & ATMEL_HLCDC_LAYER_EN ? + ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); + } else { + /* Enable the overrun interrupts. */ + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IER, + ATMEL_XLCDC_LAYER_OVR_IRQ(0) | + ATMEL_XLCDC_LAYER_OVR_IRQ(1) | + ATMEL_XLCDC_LAYER_OVR_IRQ(2)); + + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR, + ATMEL_XLCDC_LAYER_EN); + } + + /* + * Updating XLCDC_xxxCFGx, XLCDC_xxxFBA and XLCDC_xxxEN, + * (where xxx indicates each layer) requires writing one to the + * Update Attribute field for each layer in LCDC_ATTRE register for SAM9X7. + */ + if (dc->is_xlcdc) { + regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDATE | + ATMEL_XLCDC_OVR1_UPDATE | ATMEL_XLCDC_OVR3_UPDATE | + ATMEL_XLCDC_HEO_UPDATE); + } } static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) { const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER || desc->type == ATMEL_HLCDC_CURSOR_LAYER) { @@ -796,20 +917,50 @@ static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) return ret; } - if (desc->layout.csc) { + if (!(dc->is_xlcdc)) { + if (desc->layout.csc) { + /* + * TODO: decare a "yuv-to-rgb-conv-factors" property to let + * userspace modify these factors (using a BLOB property ?). + */ + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc, + 0x4c900091); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 1, + 0x7a5f5090); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 2, + 0x40040890); + } + } else { /* - * TODO: decare a "yuv-to-rgb-conv-factors" property to let - * userspace modify these factors (using a BLOB property ?). + * yuv-to-rgb-conv-factors are now defined from LCDC_HEOCFG16 to + * LCDC_HEOCFG21 registers in SAM9X7. */ - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc, - 0x4c900091); - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc + 1, - 0x7a5f5090); - atmel_hlcdc_layer_write_cfg(&plane->layer, - desc->layout.csc + 2, - 0x40040890); + if (desc->layout.csc) { + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc, + 0x00000488); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 1, + 0x00000648); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 2, + 0x1EA00480); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 3, + 0x00001D28); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 4, + 0x08100480); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 5, + 0x00000000); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.csc + 6, + 0x00000007); + } } return 0; @@ -819,19 +970,31 @@ void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) { const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; u32 isr; + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; - isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + if (!(dc->is_xlcdc)) + isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); + else + isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); /* * There's not much we can do in case of overrun except informing * the user. However, we are in interrupt context here, hence the * use of dev_dbg(). */ - if (isr & - (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) | - ATMEL_HLCDC_LAYER_OVR_IRQ(2))) - dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", - desc->name); + if (!(dc->is_xlcdc)) { + if (isr & + (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) | + ATMEL_HLCDC_LAYER_OVR_IRQ(2))) + dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", + desc->name); + } else { + if (isr & + (ATMEL_XLCDC_LAYER_OVR_IRQ(0) | ATMEL_XLCDC_LAYER_OVR_IRQ(1) | + ATMEL_XLCDC_LAYER_OVR_IRQ(2))) + dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", + desc->name); + } } static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = { From patchwork Tue Jun 13 07:04:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40B0DC77B7A for ; Tue, 13 Jun 2023 07:13:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DEF710E332; Tue, 13 Jun 2023 07:13:20 +0000 (UTC) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5FF2D10E331 for ; Tue, 13 Jun 2023 07:13:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686640398; x=1718176398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T7Y/2YDTllTUUHSl2rDvQC/p9LxvbkgfdDNcPx1ZDwk=; b=LD6GRsxjomvyVg62M9+xTch2efxYrhoEROQQ+DczWbnkqhKF8U5lq9jS 0E/wkh8ZrRFqER23SdELUpgSr8C2B1XVmAToARvZXHEn9Qs+2x1Da4Qtr zyHEJrpU+wd9lqGpzqDobyCvGMmy221tPpkAJAKIdUYmo7PlZ4VKuW56W TyWEWIRqdaScGCUM85G6K1+tRqv640WwaS1/eQm6qopANfDe9QwzDTNCP jH7TQgyrSfROV9Gn6d3nONekts0YfAMyu6fMqKCDRj9SGMONeH1D59rM3 Rqnx38W128NVpbOD4MO1olf6n5XXA7Z0JJtIBmD4jtLGYBuWZGtgYPD/C g==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="217554081" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:06:11 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:06:06 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:05:57 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Subject: [PATCH 7/9] drm: atmel-hlcdc: add DPI mode support for XLCDC Date: Tue, 13 Jun 2023 12:34:24 +0530 Message-ID: <20230613070426.467389-8-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai Manickam KR , Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for Display Pixel Interface (DPI) Compatible Mode support in atmel-hlcdc driver for XLCDC IP along with legacy pixel mapping.DPI mode BIT is configured in LCDC_CFG5 register. Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: update DPI mode bit using is_xlcdc flag] Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 7c9cf7c0c75d..abdece982507 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -30,10 +30,12 @@ * * @base: base CRTC state * @output_mode: RGBXXX output mode + * @dpi: output DPI mode */ struct atmel_hlcdc_crtc_state { struct drm_crtc_state base; unsigned int output_mode; + bool dpi; }; static inline struct atmel_hlcdc_crtc_state * @@ -138,6 +140,8 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); cfg = state->output_mode << 8; + if (crtc->dc->is_xlcdc) + cfg |= state->dpi << 11; if (!crtc->dc->is_xlcdc && (adj->flags & DRM_MODE_FLAG_NVSYNC)) cfg |= ATMEL_HLCDC_VSPOL; @@ -150,7 +154,9 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE | ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY | ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO | - ATMEL_HLCDC_GUARDTIME_MASK | ATMEL_HLCDC_MODE_MASK, + ATMEL_HLCDC_GUARDTIME_MASK | + (crtc->dc->is_xlcdc ? ATMEL_XLCDC_MODE_MASK | + ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), cfg); clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); @@ -344,7 +350,15 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) hstate = drm_crtc_state_to_atmel_hlcdc_crtc_state(state); hstate->output_mode = fls(output_fmts) - 1; - + if (crtc->dc->is_xlcdc) { + /* check if MIPI DPI bit needs to be set */ + if (fls(output_fmts) > 3) { + hstate->output_mode -= 4; + hstate->dpi = true; + } else { + hstate->dpi = false; + } + } return 0; } @@ -448,7 +462,7 @@ static struct drm_crtc_state * atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) { struct atmel_hlcdc_crtc_state *state, *cur; - + struct atmel_hlcdc_crtc *c = drm_crtc_to_atmel_hlcdc_crtc(crtc); if (WARN_ON(!crtc->state)) return NULL; @@ -459,6 +473,8 @@ atmel_hlcdc_crtc_duplicate_state(struct drm_crtc *crtc) cur = drm_crtc_state_to_atmel_hlcdc_crtc_state(crtc->state); state->output_mode = cur->output_mode; + if (c->dc->is_xlcdc) + state->dpi = cur->dpi; return &state->base; } From patchwork Tue Jun 13 07:04:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE4C2C88CB6 for ; Tue, 13 Jun 2023 07:13:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 284AA10E335; Tue, 13 Jun 2023 07:13:26 +0000 (UTC) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE19110E334 for ; Tue, 13 Jun 2023 07:13:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1686640401; x=1718176401; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NtZ1w67xZL59awaoTi+PT78oJSyEe138AbnOfIJ/pYE=; b=ryRegFsdJpVhE0r5eRZU9CcP2qCGg8EjLlCnJD2/cCWA0Jw2OcLfzzN9 2V8UCVUxEswu8jHUaa1ZwZ8hWSDFHqaxEZhOThRMCWm2C/UIRIVwjausN g8FtFwN3BuxjspF/cGbarfhA4ARx7n1JAW2b+6ZVxG6r3au46BzcHR4n/ HFLX53JxEUnr3P03ufOT7kzTnFGAoDZiwGXCh86samNb5Hb6JDKOiewZA cEMUj8dhPym/5HKuP8p54jwhyGARspiGJ9cMbhOaYTx7Hf2SZDOBACTM8 lOOCSuzhc2s1/LOWt2zaFLYymAVYxKIIiEZBai1n7IGyVl0d3ppvTVWxy Q==; X-IronPort-AV: E=Sophos;i="6.00,238,1681196400"; d="scan'208";a="229806934" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Jun 2023 00:06:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 13 Jun 2023 00:06:14 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:06:06 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Subject: [PATCH 8/9] drm: atmel-hlcdc: add vertical and horizontal scaling support for XLCDC Date: Tue, 13 Jun 2023 12:34:25 +0530 Message-ID: <20230613070426.467389-9-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai.ManickamKR@microchip.com, Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" update the LCDC_HEOCFG30 and LCDC_HEOCFG31 registers of XLCDC IP which supports vertical and horizontal scaling with Bilinear and Bicubic co-efficients taps for Chroma and Luma componenets of the Pixel. Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 2 ++ drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 4 ++++ .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 18 ++++++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index fbbd2592efc7..8fcaa4023155 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -536,6 +536,8 @@ static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x7_layers[] = { .general_config = 12, .csc = 16, .scaler_config = 23, + .vxs_config = 30, + .hxs_config = 31, }, .clut_offset = 0x1300, }, diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 804e4d476f2b..9aedfd0f6039 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -264,6 +264,8 @@ * @disc_pos: discard area position register * @disc_size: discard area size register * @csc: color space conversion register + * @vxs_config: vertical scalar filter taps control register + * @hxs_config: horizontal scalar filter taps control register */ struct atmel_hlcdc_layer_cfg_layout { int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES]; @@ -283,6 +285,8 @@ struct atmel_hlcdc_layer_cfg_layout { int disc_pos; int disc_size; int csc; + int vxs_config; + int hxs_config; }; /** diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index fe33476818c4..613382baa553 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -961,6 +961,24 @@ static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) desc->layout.csc + 6, 0x00000007); } + if (desc->layout.vxs_config && desc->layout.hxs_config) { + /* + * Updating vxs.config and hxs.config fixes the + * Green Color Issue in SAM9X7 EGT Video Player App + */ + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.vxs_config, + ATMEL_XLCDC_LAYER_VXSYCFG_ONE | + ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE | + ATMEL_XLCDC_LAYER_VXSCCFG_ONE | + ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE); + atmel_hlcdc_layer_write_cfg(&plane->layer, + desc->layout.hxs_config, + ATMEL_XLCDC_LAYER_HXSYCFG_ONE | + ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE | + ATMEL_XLCDC_LAYER_HXSCCFG_ONE | + ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE); + } } return 0; From patchwork Tue Jun 13 07:04:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13278080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC2ACC77B7A for ; Tue, 13 Jun 2023 07:13:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F63710E032; Tue, 13 Jun 2023 07:13:33 +0000 (UTC) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6A6EF10E032 for ; Tue, 13 Jun 2023 07:13:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; 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Tue, 13 Jun 2023 00:06:23 -0700 Received: from che-lt-i67131.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 13 Jun 2023 00:06:15 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , Subject: [PATCH 9/9] drm: atmel-hlcdc: add support for DSI output formats Date: Tue, 13 Jun 2023 12:34:26 +0530 Message-ID: <20230613070426.467389-10-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230613070426.467389-1-manikandan.m@microchip.com> References: <20230613070426.467389-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Balakrishnan.S@microchip.com, Nayabbasha.Sayed@microchip.com, Balamanikandan.Gunasundar@microchip.com, Manikandan , Varshini.Rajendran@microchip.com, Dharma.B@microchip.com, Durai Manickam KR , Hari.PrasathGE@microchip.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for the following DPI mode if the encoder type is DSI as per the XLCDC IP datasheet: - 16BPPCFG1 - 16BPPCFG2 - 16BPPCFG3 - 18BPPCFG1 - 18BPPCFG2 - 24BPP Signed-off-by: Manikandan Muralidharan [durai.manickamkr@microchip.com: update output format using is_xlcdc flag] Signed-off-by: Durai Manickam KR --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 117 +++++++++++++----- 1 file changed, 86 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index abdece982507..dc8361ebf05b 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -265,11 +265,18 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, } -#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) -#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) -#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) -#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) -#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) +#define ATMEL_HLCDC_RGB444_OUTPUT BIT(0) +#define ATMEL_HLCDC_RGB565_OUTPUT BIT(1) +#define ATMEL_HLCDC_RGB666_OUTPUT BIT(2) +#define ATMEL_HLCDC_RGB888_OUTPUT BIT(3) +#define ATMEL_HLCDC_DPI_RGB565C1_OUTPUT BIT(4) +#define ATMEL_HLCDC_DPI_RGB565C2_OUTPUT BIT(5) +#define ATMEL_HLCDC_DPI_RGB565C3_OUTPUT BIT(6) +#define ATMEL_HLCDC_DPI_RGB666C1_OUTPUT BIT(7) +#define ATMEL_HLCDC_DPI_RGB666C2_OUTPUT BIT(8) +#define ATMEL_HLCDC_DPI_RGB888_OUTPUT BIT(9) +#define ATMEL_HLCDC_OUTPUT_MODE_MASK GENMASK(3, 0) +#define ATMEL_XLCDC_OUTPUT_MODE_MASK GENMASK(9, 0) static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) { @@ -283,37 +290,83 @@ static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) if (!encoder) encoder = connector->encoder; - switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { - case 0: - break; - case MEDIA_BUS_FMT_RGB444_1X12: - return ATMEL_HLCDC_RGB444_OUTPUT; - case MEDIA_BUS_FMT_RGB565_1X16: - return ATMEL_HLCDC_RGB565_OUTPUT; - case MEDIA_BUS_FMT_RGB666_1X18: - return ATMEL_HLCDC_RGB666_OUTPUT; - case MEDIA_BUS_FMT_RGB888_1X24: - return ATMEL_HLCDC_RGB888_OUTPUT; - default: - return -EINVAL; - } - - for (j = 0; j < info->num_bus_formats; j++) { - switch (info->bus_formats[j]) { - case MEDIA_BUS_FMT_RGB444_1X12: - supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT; + if (encoder->encoder_type == DRM_MODE_ENCODER_DSI) { + /* + * atmel-hlcdc to support DSI formats with DSI video pipeline + * when DRM_MODE_ENCODER_DSI type is set by + * connector driver component. + */ + switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { + case 0: break; case MEDIA_BUS_FMT_RGB565_1X16: - supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB565C1_OUTPUT; case MEDIA_BUS_FMT_RGB666_1X18: - supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB666C1_OUTPUT; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + return ATMEL_HLCDC_DPI_RGB666C2_OUTPUT; case MEDIA_BUS_FMT_RGB888_1X24: - supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT; - break; + return ATMEL_HLCDC_DPI_RGB888_OUTPUT; default: + return -EINVAL; + } + + for (j = 0; j < info->num_bus_formats; j++) { + switch (info->bus_formats[j]) { + case MEDIA_BUS_FMT_RGB565_1X16: + supported_fmts |= + ATMEL_HLCDC_DPI_RGB565C1_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + supported_fmts |= + ATMEL_HLCDC_DPI_RGB666C1_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + supported_fmts |= + ATMEL_HLCDC_DPI_RGB666C2_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + supported_fmts |= + ATMEL_HLCDC_DPI_RGB888_OUTPUT; + break; + default: + break; + } + } + + } else { + switch (atmel_hlcdc_encoder_get_bus_fmt(encoder)) { + case 0: break; + case MEDIA_BUS_FMT_RGB444_1X12: + return ATMEL_HLCDC_RGB444_OUTPUT; + case MEDIA_BUS_FMT_RGB565_1X16: + return ATMEL_HLCDC_RGB565_OUTPUT; + case MEDIA_BUS_FMT_RGB666_1X18: + return ATMEL_HLCDC_RGB666_OUTPUT; + case MEDIA_BUS_FMT_RGB888_1X24: + return ATMEL_HLCDC_RGB888_OUTPUT; + default: + return -EINVAL; + } + + for (j = 0; j < info->num_bus_formats; j++) { + switch (info->bus_formats[j]) { + case MEDIA_BUS_FMT_RGB444_1X12: + supported_fmts |= ATMEL_HLCDC_RGB444_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB565_1X16: + supported_fmts |= ATMEL_HLCDC_RGB565_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + supported_fmts |= ATMEL_HLCDC_RGB666_OUTPUT; + break; + case MEDIA_BUS_FMT_RGB888_1X24: + supported_fmts |= ATMEL_HLCDC_RGB888_OUTPUT; + break; + default: + break; + } } } @@ -322,7 +375,7 @@ static int atmel_hlcdc_connector_output_mode(struct drm_connector_state *state) static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) { - unsigned int output_fmts = ATMEL_HLCDC_OUTPUT_MODE_MASK; + unsigned int output_fmts; struct atmel_hlcdc_crtc_state *hstate; struct drm_connector_state *cstate; struct drm_connector *connector; @@ -330,6 +383,8 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) int i; crtc = drm_crtc_to_atmel_hlcdc_crtc(state->crtc); + output_fmts = crtc->dc->is_xlcdc ? ATMEL_XLCDC_OUTPUT_MODE_MASK : + ATMEL_HLCDC_OUTPUT_MODE_MASK; for_each_new_connector_in_state(state->state, connector, cstate, i) { unsigned int supported_fmts = 0;