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Tue, 13 Jun 2023 14:12:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EDD2.mail.protection.outlook.com (10.167.241.206) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.23 via Frontend Transport; Tue, 13 Jun 2023 14:12:38 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Tue, 13 Jun 2023 09:12:35 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , Yazen Ghannam Subject: [PATCH 1/3] x86/MCE/AMD: Split amd_mce_is_memory_error() Date: Tue, 13 Jun 2023 09:11:40 -0500 Message-ID: <20230613141142.36801-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613141142.36801-1-yazen.ghannam@amd.com> References: <20230613141142.36801-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|SA1PR12MB8742:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c1c540b-b785-49ae-0ac5-08db6c183e3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2023 14:12:38.1100 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c1c540b-b785-49ae-0ac5-08db6c183e3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8742 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define helper functions for legacy and SMCA systems in order to reuse individual checks in later changes. Describe what each function is checking for, and correct the XEC bitmask for SMCA. No functional change intended. Signed-off-by: Yazen Ghannam Reviewed-by: Shuai Xue --- arch/x86/kernel/cpu/mce/amd.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 5e74610b39e7..1ccfb0c9257f 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -713,17 +713,37 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) deferred_error_interrupt_enable(c); } -bool amd_mce_is_memory_error(struct mce *m) +/* + * DRAM ECC errors are reported in the Northbridge (bank 4) with + * Extended Error Code 8. + */ +static bool legacy_mce_is_memory_error(struct mce *m) +{ + return m->bank == 4 && XEC(m->status, 0x1f) == 8; +} + +/* + * DRAM ECC errors are reported in Unified Memory Controllers with + * Extended Error Code 0. + */ +static bool smca_mce_is_memory_error(struct mce *m) { enum smca_bank_types bank_type; - /* ErrCodeExt[20:16] */ - u8 xec = (m->status >> 16) & 0x1f; + + if (XEC(m->status, 0x3f)) + return false; bank_type = smca_get_bank_type(m->extcpu, m->bank); + + return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2; +} + +bool amd_mce_is_memory_error(struct mce *m) +{ if (mce_flags.smca) - return (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2) && xec == 0x0; + return smca_mce_is_memory_error(m); - return m->bank == 4 && xec == 0x8; + return legacy_mce_is_memory_error(m); } static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) From patchwork Tue Jun 13 14:11:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13278877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8A3EEB64D0 for ; Tue, 13 Jun 2023 14:13:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242670AbjFMONI (ORCPT ); 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Tue, 13 Jun 2023 09:12:36 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , Yazen Ghannam Subject: [PATCH 2/3] x86/mce: Define amd_mce_usable_address() Date: Tue, 13 Jun 2023 09:11:41 -0500 Message-ID: <20230613141142.36801-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613141142.36801-1-yazen.ghannam@amd.com> References: <20230613141142.36801-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|PH7PR12MB8156:EE_ X-MS-Office365-Filtering-Correlation-Id: d4097d72-9aac-47d9-b85b-08db6c183e8a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fYpa3JzSgr4HAOSTtVq44TNA5cNBwje1LLqM/uvhe/jBPBA2Pxc4IMcToM/U3LsVdRjlXqLSV9x1QeC8j6+Qu059bAS9on4cAWyj7SVR2xKj7EehmBqRVxvdYKofEwDASXklHivZ94mNIinbpTK8Tv44gyK7WMQEunNW8yfak1JxB/JvEu+U+1Z/cAy4VHjHH5jBhSXevHed0dU7JYzfzgp7Ww0+MWavPu1/auD18LXnIGTINTU9iRuGNkXsDTOKzT7r4JhYxVpw3N6o2ggEiSSWr2huqyEiuqhaCwZ88QvNVq5uqzw8YoDrTBhOoopUAnIe+KjmTptC9O30U8BRI2DUfSsauoxJCzjO+a4T4k3aOKvGhmS+Di/VYcnWiYSUA1ozIzY+NaJ5vrArSh/+4ioKnkiAruJMyT+YHLMhiEeh0/lMYn+8CbWP6tndFx5Ya8mkJYmixVdR4I0i72BAvv8GuLLg5pnrn1HsASxy2z+GRAnyJ8NDrXILDotAeEl556q7bG9Mbx6aworipHTkzBUImdKkQ+uWAmldgVLV+h3UFGR3tv8yY/ZkvDOFxxKPCeMU3gP19OZ7EO6AzXi8URq4Tr8EMepZIzwbgTDLlM1/rFPwn4zo+kg7gXws/2mdy97H805/EBqbAXpsdwQICESjvc3BOKgmDjVLUauAnwPb+QwOuH9MWu1EEz3bGF9k4eUCf0LS0cEz3msj7GEboMpdLRupp5hmyjr74X1XUXZ2oEJ6FGkYQyoP7VfUrsVHFqnHLhjVllZ/BrMl9oHdXQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199021)(46966006)(40470700004)(36840700001)(7696005)(316002)(40460700003)(41300700001)(336012)(83380400001)(426003)(86362001)(82310400005)(36860700001)(2616005)(186003)(26005)(1076003)(44832011)(47076005)(2906002)(16526019)(82740400003)(81166007)(40480700001)(356005)(5660300002)(36756003)(8936002)(8676002)(70206006)(70586007)(478600001)(54906003)(6666004)(4326008)(6916009)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2023 14:12:38.6100 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4097d72-9aac-47d9-b85b-08db6c183e8a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8156 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Currently, all valid MCA_ADDR values are assumed to be usable on AMD systems. However, this is not correct in most cases. Notifiers expecting usable addresses may then operate on inappropriate values. Define a helper function to do AMD-specific checks for a usable memory address. List out all known cases. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 38 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mce/core.c | 3 +++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 43 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 1ccfb0c9257f..ca79fa10b844 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -746,6 +746,44 @@ bool amd_mce_is_memory_error(struct mce *m) return legacy_mce_is_memory_error(m); } +/* + * AMD systems do not have an explicit indicator that the value in MCA_ADDR is + * a system physical address. Therefore individual cases need to be detected. + * Future cases and checks will be added as needed. + * + * 1) General case + * a) Assume address is not usable. + * 2) "Poison" errors + * a) Indicated by MCA_STATUS[43]: POISON. Defined for all banks except legacy + * Northbridge (bank 4). + * b) Refers to poison consumption in the Core. Does not include "no action", + * "action optional", or "deferred" error severities. + * c) Will include a usuable address so that immediate action can be taken. + * 3) Northbridge DRAM ECC errors + * a) Reported in legacy bank 4 with XEC 8. + * b) MCA_STATUS[43] is *not* defined as POISON in legacy bank 4. Therefore, + * this bit should not be checked. + * + * NOTE: SMCA UMC memory errors fall into case #1. + */ +bool amd_mce_usable_address(struct mce *m) +{ + /* Check special Northbridge case first. */ + if (!mce_flags.smca) { + if (legacy_mce_is_memory_error(m)) + return true; + else if (m->bank == 4) + return false; + } + + /* Check Poison bit for all other bank types. */ + if (m->status & MCI_STATUS_POISON) + return true; + + /* Assume address is not usable for all others. */ + return false; +} + static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) { struct mce m; diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 89e2aab5d34d..859ce20dd730 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -464,6 +464,9 @@ int mce_usable_address(struct mce *m) if (!(m->status & MCI_STATUS_ADDRV)) return 0; + if (m->cpuvendor == X86_VENDOR_AMD) + return amd_mce_usable_address(m); + /* Checks after this one are Intel/Zhaoxin-specific: */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index d2412ce2d312..0d4c5b83ed93 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -207,6 +207,7 @@ extern bool filter_mce(struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); +bool amd_mce_usable_address(struct mce *m); /* * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits @@ -234,6 +235,7 @@ static __always_inline void smca_extract_err_addr(struct mce *m) #else static inline bool amd_filter_mce(struct mce *m) { return false; } +static inline bool amd_mce_usable_address(struct mce *m) { return false; } static inline void smca_extract_err_addr(struct mce *m) { } #endif From patchwork Tue Jun 13 14:11:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13278878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDD1DEB64D8 for ; Tue, 13 Jun 2023 14:13:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242463AbjFMONX (ORCPT ); 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Tue, 13 Jun 2023 09:12:37 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , Yazen Ghannam Subject: [PATCH 3/3] x86/mce: Fixup mce_usable_address() Date: Tue, 13 Jun 2023 09:11:42 -0500 Message-ID: <20230613141142.36801-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230613141142.36801-1-yazen.ghannam@amd.com> References: <20230613141142.36801-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD2:EE_|PH7PR12MB6657:EE_ X-MS-Office365-Filtering-Correlation-Id: eff67e79-7c29-47ca-82f6-08db6c183fb9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iWmorLm9h0RpcA3WaU66TsHRwsmipw1dHH3kL0jk9/Zmb64a9r2/IaH2HWyLEt+xLujDj2W0xB3ruSHhXw/bXslRW5BYM523AxSdxv2ZbcC/WhQ+jZWT+trXpEd/8kbUfGs98pIP0KtZ0KdlPzf19mhIKE8nTQ+6PofYkJzg0cp2SDj2sVzZ3+41MTZiUxy1nvJCwCk3CD8MQov9NLB19U8/QAuxlclCin1LoUDnQ7yqNm2UKk1RRiTdiFjrbebfO6MDi3TRCRxTa1M9etfHP4WHbxT3yqcjJVQAX9I0uVcH/QCDtpkkttI4WATSsWQAfTyHiKuLVMjn4p8mEZUlQ8z+h1/iKI4ev5Cwl/77+Vj6h3Exr85AJ1Mdg3G+3hNIlRhFPbjKm6gabQobctBu37H+1w6GyYLiREYGQWZoFT8KrptbUuSJIepoCqNfYPamyLu1YMMKN8vEA9HviafrIRzuJMtsya9lyQ+4pR0CxAcl9cDyKlclZ3xuCbmy+QBlQOc74GCmhIIwHsZKqmFeZsz3tMvWGGm4G1GKrqv5Sd01FDY8vtXsgyLswVGs8ENZ3VbwejeRb6sk9aoY38Fo1iRVSD5+EmEzjMz3MAnKsG/5Dk6Fd22XiPUPE5jI4TDscr+dw/R580n0xohL7A2T5z8gxorN927B63C6rXKyU0iQB1AGm02WJSP6HfSkf6235HOieQJeRV+Nkz79glSmBFed8bAvbSsiIHmUMDkz/3MuZswFMQ7T0j9SmEocXJzvxKeZCT/laW2JQdn0H186Tw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199021)(40470700004)(36840700001)(46966006)(8936002)(8676002)(44832011)(5660300002)(4326008)(70586007)(70206006)(6916009)(316002)(54906003)(2906002)(41300700001)(36860700001)(40460700003)(6666004)(478600001)(7696005)(356005)(81166007)(40480700001)(426003)(336012)(36756003)(186003)(16526019)(83380400001)(1076003)(47076005)(2616005)(26005)(82740400003)(86362001)(82310400005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2023 14:12:40.6100 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eff67e79-7c29-47ca-82f6-08db6c183fb9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6657 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move Intel-specific checks into a helper function. Explicitly use "bool" for return type. No functional change intended. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/core.c | 33 +++++++++--------------------- arch/x86/kernel/cpu/mce/intel.c | 20 ++++++++++++++++++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 4 files changed, 33 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 180b1cbfcc4e..6de6e1d95952 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -245,7 +245,7 @@ static inline void cmci_recheck(void) {} int mce_available(struct cpuinfo_x86 *c); bool mce_is_memory_error(struct mce *m); bool mce_is_correctable(struct mce *m); -int mce_usable_address(struct mce *m); +bool mce_usable_address(struct mce *m); DECLARE_PER_CPU(unsigned, mce_exception_count); DECLARE_PER_CPU(unsigned, mce_poll_count); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 859ce20dd730..c17e2b54853b 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -453,35 +453,22 @@ static void mce_irq_work_cb(struct irq_work *entry) mce_schedule_work(); } -/* - * Check if the address reported by the CPU is in a format we can parse. - * It would be possible to add code for most other cases, but all would - * be somewhat complicated (e.g. segment offset would require an instruction - * parser). So only support physical addresses up to page granularity for now. - */ -int mce_usable_address(struct mce *m) +bool mce_usable_address(struct mce *m) { if (!(m->status & MCI_STATUS_ADDRV)) - return 0; + return false; - if (m->cpuvendor == X86_VENDOR_AMD) + switch (m->cpuvendor) { + case X86_VENDOR_AMD: return amd_mce_usable_address(m); - /* Checks after this one are Intel/Zhaoxin-specific: */ - if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && - boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) - return 1; - - if (!(m->status & MCI_STATUS_MISCV)) - return 0; - - if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) - return 0; - - if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) - return 0; + case X86_VENDOR_INTEL: + case X86_VENDOR_ZHAOXIN: + return intel_mce_usable_address(m); - return 1; + default: + return true; + } } EXPORT_SYMBOL_GPL(mce_usable_address); diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 95275a5e57e0..56ecf128a534 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -519,3 +519,23 @@ bool intel_filter_mce(struct mce *m) return false; } + +/* + * Check if the address reported by the CPU is in a format we can parse. + * It would be possible to add code for most other cases, but all would + * be somewhat complicated (e.g. segment offset would require an instruction + * parser). So only support physical addresses up to page granularity for now. + */ +bool intel_mce_usable_address(struct mce *m) +{ + if (!(m->status & MCI_STATUS_MISCV)) + return false; + + if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) + return false; + + if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) + return false; + + return true; +} diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 0d4c5b83ed93..962b3134991d 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -49,6 +49,7 @@ void intel_init_cmci(void); void intel_init_lmce(void); void intel_clear_lmce(void); bool intel_filter_mce(struct mce *m); +bool intel_mce_usable_address(struct mce *m); #else # define cmci_intel_adjust_timer mce_adjust_timer_default static inline bool mce_intel_cmci_poll(void) { return false; } @@ -58,6 +59,7 @@ static inline void intel_init_cmci(void) { } static inline void intel_init_lmce(void) { } static inline void intel_clear_lmce(void) { } static inline bool intel_filter_mce(struct mce *m) { return false; } +static inline bool intel_mce_usable_address(struct mce *m) { return false; } #endif void mce_timer_kick(unsigned long interval);