From patchwork Thu Jun 15 07:07:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 13280801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E9A6EB64DB for ; Thu, 15 Jun 2023 07:10:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244633AbjFOHKY (ORCPT ); Thu, 15 Jun 2023 03:10:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244632AbjFOHJk (ORCPT ); Thu, 15 Jun 2023 03:09:40 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B41D10D8; Thu, 15 Jun 2023 00:08:15 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35F5LM77007464; Thu, 15 Jun 2023 07:08:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=bLNHzr8/HqOIp+2UTEW26YdDjjwket4zHoeu/hL6Cnw=; b=Z1ayBZoXcfGo8eJNYql9iYYHjDiIURbdRLFi6emN3KrMLPfUVoo2X3aEZg0Z3x6OjiMG BFGA6MTkvh+SOn9vqW2vjwkOqYyjkhrXiOuu51a0UGr9fG8pwAHVjVwspzFTeSVPyANM 64mXAytsLFCveshvErh39Wb25Kr+jjmxmY98Nca2YIGG86SBXj4g0RAgCB6VOKcZaCnP 2YwZa7FvURMBx+rmN0LU10ca/hIc7hrnGkGXy6NVaUnuI3dO9MMh4Wsl95gQrV5VXGA7 kHK06gCiBjUqo5cKBkvHoOiREd05NdM2zLsa1WbMgI4l4tZuA4IkhZBTSqxYuRVzDcQi cA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r78c7ast0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 07:08:12 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35F78B4J027469 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 07:08:11 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 15 Jun 2023 00:08:06 -0700 From: Praveen Talari To: , , , , , , , , , CC: , , , , Praveen Talari Subject: [PATCH v2 1/3] soc: qcom: geni-se: Add SPI SLAVE mode support for GENI based QuPv3 Date: Thu, 15 Jun 2023 12:37:04 +0530 Message-ID: <20230615070706.18322-2-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230615070706.18322-1-quic_ptalari@quicinc.com> References: <20230615070706.18322-1-quic_ptalari@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: i__Ik9VJ41aOM06jrn4pOiIYZvD6XJOk X-Proofpoint-ORIG-GUID: i__Ik9VJ41aOM06jrn4pOiIYZvD6XJOk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-15_04,2023-06-14_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 suspectscore=0 clxscore=1015 adultscore=0 phishscore=0 bulkscore=0 mlxlogscore=913 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306150058 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add slave mode support related registers and masks. Signed-off-by: Praveen Talari --- v1 -> v2: - modified commit message --- --- include/linux/soc/qcom/geni-se.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 821a19135bb6..29e06905bc1f 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -35,6 +35,7 @@ enum geni_se_protocol_type { GENI_SE_UART, GENI_SE_I2C, GENI_SE_I3C, + GENI_SE_SPI_SLAVE, }; struct geni_wrapper; @@ -73,12 +74,14 @@ struct geni_se { /* Common SE registers */ #define GENI_FORCE_DEFAULT_REG 0x20 +#define GENI_OUTPUT_CTRL 0x24 #define SE_GENI_STATUS 0x40 #define GENI_SER_M_CLK_CFG 0x48 #define GENI_SER_S_CLK_CFG 0x4c #define GENI_IF_DISABLE_RO 0x64 #define GENI_FW_REVISION_RO 0x68 #define SE_GENI_CLK_SEL 0x7c +#define SE_GENI_CFG_SEQ_START 0x84 #define SE_GENI_DMA_MODE_EN 0x258 #define SE_GENI_M_CMD0 0x600 #define SE_GENI_M_CMD_CTRL_REG 0x604 @@ -111,6 +114,9 @@ struct geni_se { /* GENI_FORCE_DEFAULT_REG fields */ #define FORCE_DEFAULT BIT(0) +/* GENI_OUTPUT_CTRL fields */ +#define GENI_IO_MUX_0_EN BIT(0) + /* GENI_STATUS fields */ #define M_GENI_CMD_ACTIVE BIT(0) #define S_GENI_CMD_ACTIVE BIT(12) @@ -130,6 +136,9 @@ struct geni_se { /* GENI_CLK_SEL fields */ #define CLK_SEL_MSK GENMASK(2, 0) +/* SE_GENI_CFG_SEQ_START fields */ +#define START_TRIGGER BIT(0) + /* SE_GENI_DMA_MODE_EN */ #define GENI_DMA_MODE_EN BIT(0) From patchwork Thu Jun 15 07:07:05 2023 Content-Type: text/plain; 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Thu, 15 Jun 2023 07:08:20 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 15 Jun 2023 00:08:13 -0700 From: Praveen Talari To: , , , , , , , , , CC: , , , , Praveen Talari Subject: [PATCH v2 2/3] spi: dt-bindings: qcom,spi-geni-qcom: Add SPI SLAVE mode support for GENI based QuPv3 Date: Thu, 15 Jun 2023 12:37:05 +0530 Message-ID: <20230615070706.18322-3-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230615070706.18322-1-quic_ptalari@quicinc.com> References: <20230615070706.18322-1-quic_ptalari@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5CExKcrIZJrZ0vbJC2bQo4Cqe5nVby8H X-Proofpoint-ORIG-GUID: 5CExKcrIZJrZ0vbJC2bQo4Cqe5nVby8H X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-15_03,2023-06-14_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=931 impostorscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306150058 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Set this property to configure QUPV3 as SPI slave controller. Signed-off-by: Praveen Talari --- Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml index 2e20ca313ec1..cdd6d19876d3 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -66,6 +66,8 @@ properties: reg: maxItems: 1 + qcom,slv-ctrl: + required: - compatible - clocks From patchwork Thu Jun 15 07:07:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Talari X-Patchwork-Id: 13280803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59640EB64D9 for ; Thu, 15 Jun 2023 07:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243483AbjFOHKr (ORCPT ); Thu, 15 Jun 2023 03:10:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244247AbjFOHJr (ORCPT ); Thu, 15 Jun 2023 03:09:47 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04AA22967; Thu, 15 Jun 2023 00:08:32 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35F54l77030983; Thu, 15 Jun 2023 07:08:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=ic3w1UpqYpNpJ2vCRkBkIFvarcDVy7vffcczY7GxgEs=; b=Mzfmbh4CucLjYXQ98oRcMhqI67YmzUwFhM7mOrwnYg3lqyTgdwKzTcllD/KeaVtVWLyN 497C4pvlsEtk2kqD5keZT/aJu8bqJYZoBO6zBTvfWSQcnHkfK6lYGOVm6nYzi98VF6MH dH5y/mQDC5O1vnDDUXHOib0jSiyo0osFKkTBaumrokE4Kvn3HFcodj1jT/VOLjs9O20s t+8fJx5Aq7r/treXm8Ae3cGk2ocrsd0DZ9wihkbEjijrLMWmL5OpANGD0O1wPPFjf1FM vwKNwuC4oTaI8lvhyk2EXBw43yvIoiImMelFJDlQmBJXhFSLIca7nMY0z9dyeUeG/Tgx Mg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r7p4q8r95-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 07:08:29 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35F78S8X027982 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Jun 2023 07:08:28 GMT Received: from hu-ptalari-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 15 Jun 2023 00:08:23 -0700 From: Praveen Talari To: , , , , , , , , , CC: , , , , Praveen Talari Subject: [PATCH v2 3/3] spi: spi-geni-qcom: Add SPI SLAVE mode support for GENI based QuPv3 Date: Thu, 15 Jun 2023 12:37:06 +0530 Message-ID: <20230615070706.18322-4-quic_ptalari@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230615070706.18322-1-quic_ptalari@quicinc.com> References: <20230615070706.18322-1-quic_ptalari@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LRyhNIzo0UIydeqIt4EfzVSJZ5LEuYhG X-Proofpoint-ORIG-GUID: LRyhNIzo0UIydeqIt4EfzVSJZ5LEuYhG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-15_04,2023-06-14_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306150058 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently spi geni driver supports only master mode operation. Add slave mode support to GENI based QuPv3. Signed-off-by: Praveen Talari --- v1 -> v2 - modified the commit message - added the code changes for code comments --- --- drivers/spi/spi-geni-qcom.c | 57 +++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 206cc04bb1ed..2170bd6b7eef 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -52,6 +53,9 @@ #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10) #define SPI_CS_CLK_DELAY_SHFT 10 +#define SE_SPI_SLAVE_EN (0x2BC) +#define SPI_SLAVE_EN BIT(0) + /* M_CMD OP codes for SPI */ #define SPI_TX_ONLY 1 #define SPI_RX_ONLY 2 @@ -99,6 +103,24 @@ struct spi_geni_master { int cur_xfer_mode; }; +static struct spi_master *get_spi_master(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct spi_master *spi = platform_get_drvdata(pdev); + + return spi; +} + +static void spi_slv_setup(struct spi_geni_master *mas) +{ + struct geni_se *se = &mas->se; + + writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); + writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); + writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); + dev_dbg(mas->dev, "spi slave setup done\n"); +} + static int get_spi_clk_cfg(unsigned int speed_hz, struct spi_geni_master *mas, unsigned int *clk_idx, @@ -140,12 +162,18 @@ static void handle_se_timeout(struct spi_master *spi, const struct spi_transfer *xfer; spin_lock_irq(&mas->lock); - reinit_completion(&mas->cancel_done); if (mas->cur_xfer_mode == GENI_SE_FIFO) writel(0, se->base + SE_GENI_TX_WATERMARK_REG); xfer = mas->cur_xfer; mas->cur_xfer = NULL; + + if (spi->slave) { + spin_unlock_irq(&mas->lock); + goto unmap_if_dma; + } + + reinit_completion(&mas->cancel_done); geni_se_cancel_m_cmd(se); spin_unlock_irq(&mas->lock); @@ -542,6 +570,10 @@ static bool geni_can_dma(struct spi_controller *ctlr, if (mas->cur_xfer_mode == GENI_GPI_DMA) return true; + /* Set DMA mode for SPI slave. */ + if (ctlr->slave) + return true; + len = get_xfer_len_in_words(xfer, mas); fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word; @@ -619,6 +651,7 @@ static void spi_geni_release_dma_chan(struct spi_geni_master *mas) static int spi_geni_init(struct spi_geni_master *mas) { + struct spi_master *spi = get_spi_master(mas->dev); struct geni_se *se = &mas->se; unsigned int proto, major, minor, ver; u32 spi_tx_cfg, fifo_disable; @@ -627,7 +660,14 @@ static int spi_geni_init(struct spi_geni_master *mas) pm_runtime_get_sync(mas->dev); proto = geni_se_read_proto(se); - if (proto != GENI_SE_SPI) { + + if (spi->slave) { + if (proto != GENI_SE_SPI_SLAVE) { + dev_err(mas->dev, "Invalid proto %d\n", proto); + goto out_pm; + } + spi_slv_setup(mas); + } else if (proto != GENI_SE_SPI) { dev_err(mas->dev, "Invalid proto %d\n", proto); goto out_pm; } @@ -677,9 +717,11 @@ static int spi_geni_init(struct spi_geni_master *mas) } /* We always control CS manually */ - spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); - spi_tx_cfg &= ~CS_TOGGLE; - writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); + if (!spi->slave) { + spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); + spi_tx_cfg &= ~CS_TOGGLE; + writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); + } out_pm: pm_runtime_put(mas->dev); @@ -1072,6 +1114,9 @@ static int spi_geni_probe(struct platform_device *pdev) pm_runtime_set_autosuspend_delay(&pdev->dev, 250); pm_runtime_enable(dev); + if (device_property_read_bool(&pdev->dev, "qcom,slv-ctrl")) + spi->slave = true; + ret = geni_icc_get(&mas->se, NULL); if (ret) goto spi_geni_probe_runtime_disable; @@ -1092,7 +1137,7 @@ static int spi_geni_probe(struct platform_device *pdev) * for dma (gsi) mode, the gsi will set cs based on params passed in * TRE */ - if (mas->cur_xfer_mode == GENI_SE_FIFO) + if (!spi->slave && mas->cur_xfer_mode == GENI_SE_FIFO) spi->set_cs = spi_geni_set_cs; ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);