From patchwork Thu Jun 15 15:48:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13281438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E80EEB64DC for ; Thu, 15 Jun 2023 15:48:57 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.549715.858401 (Exim 4.92) (envelope-from ) id 1q9pDG-0006Rq-IA; Thu, 15 Jun 2023 15:48:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 549715.858401; Thu, 15 Jun 2023 15:48:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDG-0006Rj-E0; Thu, 15 Jun 2023 15:48:42 +0000 Received: by outflank-mailman (input) for mailman id 549715; Thu, 15 Jun 2023 15:48:40 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDE-0006RS-Kd for xen-devel@lists.xenproject.org; Thu, 15 Jun 2023 15:48:40 +0000 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [2a00:1450:4864:20::32f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 18e765e1-0b94-11ee-b232-6b7b168915f2; Thu, 15 Jun 2023 17:48:39 +0200 (CEST) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f7fcdc7f7fso7359415e9.0 for ; Thu, 15 Jun 2023 08:48:39 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id e10-20020a056000194a00b0030497b3224bsm21374699wry.64.2023.06.15.08.48.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 08:48:38 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 18e765e1-0b94-11ee-b232-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1686844119; x=1689436119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lhal1etJcoQVv2Xj28gXUSWBqPiytpkGg3ZC25OkTWA=; b=CJKdztpwLwg32RhJ+fc1jM+0mM9Fs37dYwmugnDGjfuYVNyiVEjIn6s/GpP6t1BWuz I4n7Ve2H+GU1HlVDbkcd7/8KgNRpkYRuN7ZvUOqDeMW0DGTc2jOhnO69XwGF+g6SpSpu LrLDwGG1DB+o49pWoHInDSRqHyhdfexDUOj7o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686844119; x=1689436119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lhal1etJcoQVv2Xj28gXUSWBqPiytpkGg3ZC25OkTWA=; b=TmYzwuLiPq4qF60dlx2kjgX3zCG4/yVvgr4Oe24aWcW830Sn8NGbhI+O4u3X2rg3wg aRsihOMPTsPjlc8Cdh9pCRKrKkwnKiHuj/cXuOn3UtNyzCPBirJ9uJJWWJFofY1Xux2r J0+eHphD8vmYblzRKkody8qnLLTKSWgXO6RCbNpRUpIyI9nLG03fTYph13HOGo+DsZa+ QekI8vi6v6vMVzSwS0eETjQ6jiOHgQkK8h9PavXcY5PQqqUozOLE7xVuU5ct+Vm2iXqd iSjRvkt+0joDUwiqxd9n1DzXPHBa2KBLBXMNympYHOA/2dLErBrhLxfDKBAzYUrF40fb ly3g== X-Gm-Message-State: AC+VfDxMkHB9boxkFJYVDW5wrf8bkWjsHsOnAYN0KSxDhDxQigoct0DR 7w9LdsWY0jD+X2+zUiD5DgU9Okn9qLMLKgtdOYU= X-Google-Smtp-Source: ACHHUZ5pk6DdQICbIzSsGjHZ33b6KNwddueizS4fOfbWOZhYaSWZLU0xq3PVlUBAFWdH0aoj2vDItg== X-Received: by 2002:a5d:4687:0:b0:30f:ba3a:85c5 with SMTP id u7-20020a5d4687000000b0030fba3a85c5mr4532927wrq.25.1686844119084; Thu, 15 Jun 2023 08:48:39 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v3 1/5] x86/microcode: Allow reading microcode revision even if it can't be updated Date: Thu, 15 Jun 2023 16:48:30 +0100 Message-Id: <20230615154834.959-2-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615154834.959-1-alejandro.vallejo@cloud.com> References: <20230615154834.959-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 The code currently assumes all microcode handlers are set or none are. That won't be the case in a future patch, as apply_microcode() may not be set while the others are. Hence, this patch allows reading the microcode revision even if updating it is unavailable. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v3: * Hunks taken from v2/patch4 (Jan) --- xen/arch/x86/cpu/microcode/core.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index e65af4b82e..df7e1df870 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -750,11 +750,12 @@ __initcall(microcode_init); /* Load a cached update to current cpu */ int microcode_update_one(void) { + if ( ucode_ops.collect_cpu_info ) + alternative_vcall(ucode_ops.collect_cpu_info); + if ( !ucode_ops.apply_microcode ) return -EOPNOTSUPP; - alternative_vcall(ucode_ops.collect_cpu_info); - return microcode_update_cpu(NULL); } @@ -860,6 +861,9 @@ int __init early_microcode_init(unsigned long *module_map, break; } + if ( ucode_ops.collect_cpu_info ) + ucode_ops.collect_cpu_info(); + if ( !ucode_ops.apply_microcode ) { printk(XENLOG_WARNING "Microcode loading not available\n"); @@ -868,8 +872,6 @@ int __init early_microcode_init(unsigned long *module_map, microcode_grab_module(module_map, mbi); - ucode_ops.collect_cpu_info(); - if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); From patchwork Thu Jun 15 15:48:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13281439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86571C0015E for ; Thu, 15 Jun 2023 15:48:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.549717.858410 (Exim 4.92) (envelope-from ) id 1q9pDH-0006b7-2k; Thu, 15 Jun 2023 15:48:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 549717.858410; Thu, 15 Jun 2023 15:48:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDG-0006a1-Vg; Thu, 15 Jun 2023 15:48:42 +0000 Received: by outflank-mailman (input) for mailman id 549717; Thu, 15 Jun 2023 15:48:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDG-0006RY-29 for xen-devel@lists.xenproject.org; Thu, 15 Jun 2023 15:48:42 +0000 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [2a00:1450:4864:20::429]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 194a138e-0b94-11ee-8611-37d641c3527e; Thu, 15 Jun 2023 17:48:40 +0200 (CEST) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-307d20548adso5971786f8f.0 for ; Thu, 15 Jun 2023 08:48:40 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id e10-20020a056000194a00b0030497b3224bsm21374699wry.64.2023.06.15.08.48.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 08:48:39 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 194a138e-0b94-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1686844119; x=1689436119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hW/Gx0/gWuVvgcbydVmma7SPTfd/FqCS3V8cKgHysUU=; b=euaZ9xVkCiDKzfJx4HtgNdKwXIAAMf/7Yr0O8yib05CeCA4cKaMQ3innKj8xLI5li+ oggIbJRLorHhk910Vnv6+EjP36br8jWjjeYd6ZO8SskaPuOrRtq4lZwcnPxs2KA84vt5 gKsv/9J8B04YWqs3b4wLLKnuw4QD6bln6oL+k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686844119; x=1689436119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hW/Gx0/gWuVvgcbydVmma7SPTfd/FqCS3V8cKgHysUU=; b=UbrIV8S/Dr/CKWZ4Xwsia0aR05tevhdYoe/4HikpyX6yHHwLUdW9TDpkzUUmb7FS8s V/gUW6b6GK2inP9Aff03SbEzyqtTA2yHHtGTCCUjtaSf5h/v6UOo66mIoaqSOtKoKsbL 7/Dano0JChBvjPeMPRNq3B7rQtZG9ASfoObGe1zSbGUiacPjXyTCjWrPyxoZZlVLvZFu 2ZAofYiec0hz/n/8Vd6pShqeA/1CL25vVISu1xv7VZfgotBXZtMeVwzju4rYUdNL5yj9 mcr3FpmhY8cG+wrgyrjK85BmG1VkuOZ5xojirzpR6i0i/wZd46grPf9q+19F9AKLCGbq /rFA== X-Gm-Message-State: AC+VfDyDaSb6mjwLJ1yvWK4FfizmwFEB1U8u1doQTKfVk8TpstpDuOxa +ImzMbenyKkRFWbjNn7cYLf7luJLSxmNsRI9uTI= X-Google-Smtp-Source: ACHHUZ4Z9FQLS5JRGxg0W/2DYdAKIjM0uoPCaHcxYEAGtC3t9TVrbUiMZmdnhBXDUnQSiJpPEC+6eQ== X-Received: by 2002:a5d:4e05:0:b0:304:8149:239b with SMTP id p5-20020a5d4e05000000b003048149239bmr10956632wrt.50.1686844119748; Thu, 15 Jun 2023 08:48:39 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v3 2/5] x86/microcode: Create per-vendor microcode_ops builders Date: Thu, 15 Jun 2023 16:48:31 +0100 Message-Id: <20230615154834.959-3-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615154834.959-1-alejandro.vallejo@cloud.com> References: <20230615154834.959-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Replace the ucode_ops assignments in core.c for per-vendor calls. This is in preparation for another patch that adds Intel-specific conditions. While moving the code around, also remove the family check on Intel, as microcode loading is present on every Intel 64 machine. Signed-off-by: Alejandro Vallejo --- v3: * Subsumes v2/patch1 * Removes previous long comment on rationale for skipping family checks (Jan/Andrew) * Isolates vendor-specific code in ${VENDOR}.c (Jan, from v2/patch4) --- xen/arch/x86/cpu/microcode/amd.c | 16 ++++++++++------ xen/arch/x86/cpu/microcode/core.c | 10 +++------- xen/arch/x86/cpu/microcode/intel.c | 13 +++++++------ xen/arch/x86/cpu/microcode/private.h | 19 ++++++++++++++++++- 4 files changed, 38 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/amd.c index a9a5557835..7c9f311454 100644 --- a/xen/arch/x86/cpu/microcode/amd.c +++ b/xen/arch/x86/cpu/microcode/amd.c @@ -432,9 +432,13 @@ static struct microcode_patch *cf_check cpu_request_microcode( return patch; } -const struct microcode_ops __initconst_cf_clobber amd_ucode_ops = { - .cpu_request_microcode = cpu_request_microcode, - .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode, - .compare_patch = compare_patch, -}; +void __init amd_get_ucode_ops(struct microcode_ops *ops) +{ + if ( boot_cpu_data.x86 < 0x10 ) + return; + + ops->cpu_request_microcode = cpu_request_microcode; + ops->collect_cpu_info = collect_cpu_info; + ops->apply_microcode = apply_microcode; + ops->compare_patch = compare_patch; +} diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index df7e1df870..530e3e8267 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -845,19 +845,15 @@ static int __init early_microcode_update_cpu(void) int __init early_microcode_init(unsigned long *module_map, const struct multiboot_info *mbi) { - const struct cpuinfo_x86 *c = &boot_cpu_data; int rc = 0; - switch ( c->x86_vendor ) + switch ( boot_cpu_data.x86_vendor ) { case X86_VENDOR_AMD: - if ( c->x86 >= 0x10 ) - ucode_ops = amd_ucode_ops; + amd_get_ucode_ops(&ucode_ops); break; - case X86_VENDOR_INTEL: - if ( c->x86 >= 6 ) - ucode_ops = intel_ucode_ops; + intel_get_ucode_ops(&ucode_ops); break; } diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c index 8d4d6574aa..a99e402b98 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -385,9 +385,10 @@ static struct microcode_patch *cf_check cpu_request_microcode( return patch; } -const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = { - .cpu_request_microcode = cpu_request_microcode, - .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode, - .compare_patch = compare_patch, -}; +void __init intel_get_ucode_ops(struct microcode_ops *ops) +{ + ops->cpu_request_microcode = cpu_request_microcode; + ops->collect_cpu_info = collect_cpu_info; + ops->apply_microcode = apply_microcode; + ops->compare_patch = compare_patch; +} diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microcode/private.h index 626aeb4d08..13f0c7fb8e 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -60,6 +60,23 @@ struct microcode_ops { const struct microcode_patch *new, const struct microcode_patch *old); }; -extern const struct microcode_ops amd_ucode_ops, intel_ucode_ops; +/** + * Retrieve the vendor-specific microcode management handlers + * + * Note that this is not an static set of handlers and may change from + * system to system depending on the presence of certain runtime features. + * even for the same + * + * - If the system has no microcode facilities, no handler is set. + * - If the system has unrestricted microcode facilities, all handlers + * are set + * - If the system has microcode facilities, but they can't be used to + * update the revision, then all handlers except for apply_microcode() + * are set + * + * @param[out] ops Set of vendor-specific microcode handlers to overwrite + */ +void intel_get_ucode_ops(struct microcode_ops *ops); +void amd_get_ucode_ops(struct microcode_ops *ops); #endif /* ASM_X86_MICROCODE_PRIVATE_H */ From patchwork Thu Jun 15 15:48:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13281437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19FADC3DA40 for ; Thu, 15 Jun 2023 15:48:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.549719.858436 (Exim 4.92) (envelope-from ) id 1q9pDI-0007Eo-Tm; Thu, 15 Jun 2023 15:48:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 549719.858436; Thu, 15 Jun 2023 15:48:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDI-0007Dv-Nj; Thu, 15 Jun 2023 15:48:44 +0000 Received: by outflank-mailman (input) for mailman id 549719; Thu, 15 Jun 2023 15:48:43 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDH-0006RY-2C for xen-devel@lists.xenproject.org; Thu, 15 Jun 2023 15:48:43 +0000 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [2a00:1450:4864:20::429]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 19d816cf-0b94-11ee-8611-37d641c3527e; Thu, 15 Jun 2023 17:48:41 +0200 (CEST) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-30aea656e36so5973964f8f.1 for ; Thu, 15 Jun 2023 08:48:41 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id e10-20020a056000194a00b0030497b3224bsm21374699wry.64.2023.06.15.08.48.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 08:48:39 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 19d816cf-0b94-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1686844120; x=1689436120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WnBLCpBRw4FnACMA6JimLolA7wsQAmylgXv84AWmx3g=; b=EOe8C24/Hha9iJPhezP4egK6yCdGlX22P+KZyztDJ1gAfauTk3KiSU/GAMWBWK/1OZ 7qTMvvNL+03KOvJ8cUg3QS2mBasXeHqgaak5RsqyPmUdu4PDFgdfTAYKPg/rn1y6Q8T0 oXdfp8NqNEcWCUGVNavjXvUlL2XvW+Tvy40SI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686844120; x=1689436120; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WnBLCpBRw4FnACMA6JimLolA7wsQAmylgXv84AWmx3g=; b=l8Yk9n1mYWfU6h3/M0xYvpmo5Vq1po8xKr/8PApokvmlCjOQG7jUm+iOAbeFxtd2rz Bg7DFDuGFgzYh8wASVzriuLzkx0v9MeHAPanT1v8EkRW8FH7SuMhmt30SdP9Yh/48o+o zRatikvZ0e7jdrSL/eWBNhDrVtpwIaHIq2OisXMx7cwNXK5vrd/0z/KdZjfgq/lBJG17 l83jXb21Sonj4L8qr2xo4aGgybiaFCF0g9lTxMKVWzbiZbu/QPUYEDCvuu12cv8vfwgZ yAOnGq1avEyAyqVnkH6tVdO0ivYUDVCdyqfrjWEMJ87u3qUyREILitEvgm1ZPVXJSLp+ d98g== X-Gm-Message-State: AC+VfDx7kOvAbbKsf4lVySchq8UfQDyv9Y8N1JvHaoyFQrKlWkSMhdYN RonMDNSyVOy5nHFNj7ahqYp0tJBa2OMSHZb33Oc= X-Google-Smtp-Source: ACHHUZ7xfYEs4frXBMKRcOHNEZ4p3qSPH+O9sVU0knfUAn3HS5x+N+3ZXdmYbnu/CAb/i7aBM0xL7g== X-Received: by 2002:adf:eb8d:0:b0:309:1532:8287 with SMTP id t13-20020adfeb8d000000b0030915328287mr11785575wrn.19.1686844120373; Thu, 15 Jun 2023 08:48:40 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v3 3/5] x86/microcode: Ignore microcode loading interface for revision = -1 Date: Thu, 15 Jun 2023 16:48:32 +0100 Message-Id: <20230615154834.959-4-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615154834.959-1-alejandro.vallejo@cloud.com> References: <20230615154834.959-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Some hypervisors report ~0 as the microcode revision to mean "don't issue microcode updates". Ignore the microcode loading interface in that case. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v3: * Moved from v2/patch3 (Andrew) --- xen/arch/x86/cpu/microcode/core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 530e3e8267..1554fa38eb 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -860,6 +860,14 @@ int __init early_microcode_init(unsigned long *module_map, if ( ucode_ops.collect_cpu_info ) ucode_ops.collect_cpu_info(); + /* + * Some hypervisors deliberately report a microcode revision of -1 to + * mean that they will not accept microcode updates. We take the hint + * and ignore the microcode interface in that case. + */ + if ( this_cpu(cpu_sig).rev == ~0 ) + ucode_ops.apply_microcode = NULL; + if ( !ucode_ops.apply_microcode ) { printk(XENLOG_WARNING "Microcode loading not available\n"); From patchwork Thu Jun 15 15:48:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13281434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF53EEB64D9 for ; Thu, 15 Jun 2023 15:48:57 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.549718.858431 (Exim 4.92) (envelope-from ) id 1q9pDI-000799-Gf; Thu, 15 Jun 2023 15:48:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 549718.858431; Thu, 15 Jun 2023 15:48:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDI-00077B-BT; Thu, 15 Jun 2023 15:48:44 +0000 Received: by outflank-mailman (input) for mailman id 549718; Thu, 15 Jun 2023 15:48:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDG-0006RS-HC for xen-devel@lists.xenproject.org; Thu, 15 Jun 2023 15:48:42 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1a3a6748-0b94-11ee-b232-6b7b168915f2; Thu, 15 Jun 2023 17:48:41 +0200 (CEST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f8d176396bso19742675e9.2 for ; Thu, 15 Jun 2023 08:48:41 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id e10-20020a056000194a00b0030497b3224bsm21374699wry.64.2023.06.15.08.48.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 08:48:40 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1a3a6748-0b94-11ee-b232-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1686844121; x=1689436121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PygkzDMarvKkBrBEGn4BWQS9IKMe1k1LLgAi19GYhP8=; b=HPzd4Zyex9as+U9ydNDI3tGQtwRCTB7c7d5MjHU1IH8Z7jJhGrRWMjIL7+bYYRmPZi 2/FVV3+PCcnsuD4nA9pUUZsazPWwBkfMA/NyyuLkbZLgWUjkwPp2kJke7eW5lmbkBPvr 9KVvJBUONVVNh0pyhy8zuMWPCpTfUYh2u/Ubk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686844121; x=1689436121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PygkzDMarvKkBrBEGn4BWQS9IKMe1k1LLgAi19GYhP8=; b=X/Krc+wz3zqFs9MHSjFlwCKPF5DQ0pGE45nsl7nBR1+R8T8QsSuN1zuyrkVlZmP2ZA r6AE6PrxpbSoX6E6Bh5pTBTvTsL4fOXvEXF9kcJ4I5HC6CoBM49FS3aObEZnnecNeIkq qw2RR9M4J1bCAU/sqNzRQIqQZhPq2zlhCN5BUxbx0EbVV71Wj0FkyPMZ3Mdh66mzd/mB YdQuLPVf6ZEbuq/29G+zCd86+sVODiOIiFwBc/GExDBUvqPtlU/BGekpqMho0/c5irHb m2HNhvx/eNIcuLfap0KIfi/ZBEZ6i58sucGO037LlzRamF6eqiRWCmd0Htm7DHkD9U7V e8Uw== X-Gm-Message-State: AC+VfDxaGYxmAhKomM9SgnlLQ8rMBNqNtKDprWU0DVomBWPBfshKZvB/ K5Y0633ZclIfaqlebGIwWwPo0jBv5EIv5jcs/AM= X-Google-Smtp-Source: ACHHUZ7u+G2JRXo+ew0FlGXSbGfZJGVxMwXLRreh9PhyU0vbxEMYOMEJcEb2FgtgArGvvYTQMrt1/w== X-Received: by 2002:a5d:6b0f:0:b0:311:17ae:ddbf with SMTP id v15-20020a5d6b0f000000b0031117aeddbfmr1615595wrw.51.1686844121294; Thu, 15 Jun 2023 08:48:41 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v3 4/5] x86: Read MSR_ARCH_CAPS immediately after early_microcode_init() Date: Thu, 15 Jun 2023 16:48:33 +0100 Message-Id: <20230615154834.959-5-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615154834.959-1-alejandro.vallejo@cloud.com> References: <20230615154834.959-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Move MSR_ARCH_CAPS read code from tsx_init() to immediately after the early microcode update. This helps keep the reload closer to its cause and is the earliest point we can read it, as it might be exposed only after a microcode update. Signed-off-by: Alejandro Vallejo --- v3: * Replaces v2/patch2. Moved after the "rev == ~0" check (Andrew) --- xen/arch/x86/cpu/microcode/core.c | 13 +++++++++++++ xen/arch/x86/tsx.c | 15 +++------------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 1554fa38eb..ef3c94018c 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -879,5 +879,18 @@ int __init early_microcode_init(unsigned long *module_map, if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); + /* + * We might have exposed MSR_ARCH_CAPS after the microcode update. + * Reload relevant fields in boot_cpu_data if so because they are + * needed in tsx_init() + */ + if ( boot_cpu_data.cpuid_level >= 7 ) + boot_cpu_data.x86_capability[FEATURESET_7d0] + = cpuid_count_edx(7, 0); + if ( cpu_has_arch_caps ) + rdmsr(MSR_ARCH_CAPABILITIES, + boot_cpu_data.x86_capability[FEATURESET_m10Al], + boot_cpu_data.x86_capability[FEATURESET_m10Ah]); + return rc; } diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 80c6f4cedd..11e9471180 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -39,9 +39,9 @@ void tsx_init(void) static bool __read_mostly once; /* - * This function is first called between microcode being loaded, and CPUID - * being scanned generally. Read into boot_cpu_data.x86_capability[] for - * the cpu_has_* bits we care about using here. + * This function is first called between microcode being loaded, and + * CPUID being scanned generally. early_microcode_init() has already + * prepared the feature bits needed here after the microcode update. */ if ( unlikely(!once) ) { @@ -49,15 +49,6 @@ void tsx_init(void) once = true; - if ( boot_cpu_data.cpuid_level >= 7 ) - boot_cpu_data.x86_capability[FEATURESET_7d0] - = cpuid_count_edx(7, 0); - - if ( cpu_has_arch_caps ) - rdmsr(MSR_ARCH_CAPABILITIES, - boot_cpu_data.x86_capability[FEATURESET_m10Al], - boot_cpu_data.x86_capability[FEATURESET_m10Ah]); - has_rtm_always_abort = cpu_has_rtm_always_abort; if ( cpu_has_tsx_ctrl && cpu_has_srbds_ctrl ) From patchwork Thu Jun 15 15:48:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13281436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DFEDEB64DA for ; Thu, 15 Jun 2023 15:48:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.549720.858442 (Exim 4.92) (envelope-from ) id 1q9pDJ-0007LR-9L; Thu, 15 Jun 2023 15:48:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 549720.858442; Thu, 15 Jun 2023 15:48:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDJ-0007Jo-2O; Thu, 15 Jun 2023 15:48:45 +0000 Received: by outflank-mailman (input) for mailman id 549720; Thu, 15 Jun 2023 15:48:43 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1q9pDH-0006RS-8t for xen-devel@lists.xenproject.org; Thu, 15 Jun 2023 15:48:43 +0000 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [2a00:1450:4864:20::22e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1aaf2a78-0b94-11ee-b232-6b7b168915f2; Thu, 15 Jun 2023 17:48:42 +0200 (CEST) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2b448470602so10251061fa.2 for ; Thu, 15 Jun 2023 08:48:42 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id e10-20020a056000194a00b0030497b3224bsm21374699wry.64.2023.06.15.08.48.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jun 2023 08:48:41 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1aaf2a78-0b94-11ee-b232-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1686844122; x=1689436122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tFauoCPb3uFIKLyQY0yOuojLsuuCte23s4sWaojZ6LI=; b=MThFwTc94JwI5fxtNvYJ5ouIYUb2vHHDV8sdWVrIQanhRfWjHdjci5JVvYOmLzjcoB 50PteWgdEk1gvPqv7zG2u7FjF+01RWxYpoc+YgjamHzTq8oFZZJnWnRxY22mOvzfD7Fw bfC5yb8OkuLdhpa7D6SbhqSTdZGvgFNdQEgf0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686844122; x=1689436122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tFauoCPb3uFIKLyQY0yOuojLsuuCte23s4sWaojZ6LI=; b=dWXaq85pRiGnGmOFUzV2KbIUJgSWLlkpBE5kb4sRYRIF3cd9k7bbApyxZGgx/Jo1bB MRScApYOKW2mK7+W5gDPCIvnLCBMxDP8r7oI3/EKiOpBNagCkioplyWfwPPstWlp7Cyt 5NyPj/IFJF2cjJeFf4gKGs/o88RW9qpQcG3LdRsBY28oXp0RKLKu69CbiI7eDByQ+TJP N9uwprN47cmZAcDNbw+jn8g28z6wtLUnbM/XeJAXN68AJvafBhsu3UHkXYVCanRaPbG3 5Ly9U7EFthmK+HFLF5tioAzEUeERLaPIlLkW0QjUWzo2X1lOVbPGe673uct5uXXji3A3 1VlA== X-Gm-Message-State: AC+VfDyZYwHXr/TXk6toREtMrYReDzuTjf+kVxuLqo+gp5lDDFL+eD1+ JC0AnCD4+ccvjtJgpOJ69yHxeAHfntDTjJnUR90= X-Google-Smtp-Source: ACHHUZ6+qEDZ5JtKp1AuzwFXFhPE0BDozyeWFnxRya3nBahP7ijDZCpAjwzP+C8q210kec3UuBXPMA== X-Received: by 2002:ac2:5b46:0:b0:4f6:2317:f387 with SMTP id i6-20020ac25b46000000b004f62317f387mr9179734lfp.35.1686844122040; Thu, 15 Jun 2023 08:48:42 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v3 5/5] x86/microcode: Disable microcode update handler if DIS_MCU_UPDATE is set Date: Thu, 15 Jun 2023 16:48:34 +0100 Message-Id: <20230615154834.959-6-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615154834.959-1-alejandro.vallejo@cloud.com> References: <20230615154834.959-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 If IA32_MSR_MCU_CONTROL exists then it's possible a CPU may be unable to perform microcode updates. This is controlled through the DIS_MCU_LOAD bit and is intended for baremetal clouds where the owner may not trust the tenant to choose the microcode version in use. If we notice that bit being set then simply disable the "apply_microcode" handler so we can't even try to perform update (as it's known to be silently dropped). Signed-off-by: Alejandro Vallejo --- v3: * Removed microcode_update_one() hunk (Jan, from v2/patch4) * Read MSR_ARCH_CAPS in early_cpu_init(), missing in v2/patch4 (Andy) * Moved the MSR_ARCH_CAPS after-update read (it's on v3/p3 now) * Logic previouslyin this_cpu_can_install_update() is now integrated in intel_get_ucode_ops() (Jan, from v2/p4) --- xen/arch/x86/cpu/common.c | 5 +++++ xen/arch/x86/cpu/microcode/intel.c | 14 ++++++++++++++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 5 +++++ 4 files changed, 25 insertions(+) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index cfcdaace12..2f895e7c7c 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -352,6 +352,11 @@ void __init early_cpu_init(void) &c->x86_capability[FEATURESET_7c0], &c->x86_capability[FEATURESET_7d0]); + if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) + rdmsr(MSR_ARCH_CAPABILITIES, + c->x86_capability[FEATURESET_m10Al], + c->x86_capability[FEATURESET_m10Ah]); + if (max_subleaf >= 1) cpuid_count(7, 1, &eax, &ebx, &ecx, &c->x86_capability[FEATURESET_7d1]); diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c index a99e402b98..abcfdc460d 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -387,8 +387,22 @@ static struct microcode_patch *cf_check cpu_request_microcode( void __init intel_get_ucode_ops(struct microcode_ops *ops) { + uint64_t mcu_ctrl; + ops->cpu_request_microcode = cpu_request_microcode; ops->collect_cpu_info = collect_cpu_info; ops->apply_microcode = apply_microcode; ops->compare_patch = compare_patch; + + if ( cpu_has_mcu_ctrl ) + { + rdmsrl(MSR_MCU_CONTROL, mcu_ctrl); + /* + * If DIS_MCU_LOAD is set applying microcode updates won't work. We + * can still query the current version and things like that, so + * we'll leave the other handlers in place. + */ + if ( mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD ) + ops->apply_microcode = NULL; + } } diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index ace31e3b1f..0118171d7e 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -192,6 +192,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_NO) #define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) #define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO) +#define cpu_has_mcu_ctrl boot_cpu_has(X86_FEATURE_MCU_CTRL) #define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR) /* Synthesized. */ diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 2749e433d2..5c1350b5f9 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -165,6 +165,11 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) +#define MSR_MCU_CONTROL 0x00001406 +#define MCU_CONTROL_LOCK (_AC(1, ULL) << 0) +#define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1) +#define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2) + #define MSR_UARCH_MISC_CTRL 0x00001b01 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)