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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow access the TCR2_ELx register which provides extended translation controls similar to TCR_ELx. Initialise these registers to a value of 0. Signed-off-by: Joey Gouly --- arch/aarch64/include/asm/cpu.h | 8 ++++++++ arch/aarch64/init.c | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 89a8f78..0213d53 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -17,6 +17,9 @@ #define CURRENTEL_EL2 (2 << 2) #define CURRENTEL_EL1 (1 << 2) +#define TCR2_EL2 s3_4_c2_c0_3 +#define TCR2_EL1 s3_0_c2_c0_3 + /* * RES1 bit definitions definitions as of ARM DDI 0487G.b * @@ -51,6 +54,7 @@ #define SCR_EL3_TME BIT(34) #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) +#define SCR_EL3_TCR2EN BIT(43) #define HCR_EL2_RES1 BIT(1) @@ -73,6 +77,8 @@ #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) +#define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) + #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) #define ID_AA64PFR0_EL1_SVE BITS(35, 32) @@ -122,6 +128,8 @@ #define ID_AA64ISAR2_EL1 s3_0_c0_c6_2 +#define ID_AA64MMFR3_EL1 s3_0_c0_c7_3 + #define SCTLR_EL1_CP15BEN (1 << 5) #ifdef KERNEL_32 diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 471e234..e09e050 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -64,6 +64,12 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR1_EL1, HCX)) scr |= SCR_EL3_HXEn; + if (mrs_field(ID_AA64MMFR3_EL1, TCRX)) { + scr |= SCR_EL3_TCR2EN; + msr(TCR2_EL2, 0); + msr(TCR2_EL1, 0); + } + if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2) scr |= SCR_EL3_ATA; From patchwork Fri Jun 16 16:00:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joey Gouly X-Patchwork-Id: 13282930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0280EB64D8 for ; Fri, 16 Jun 2023 16:01:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 16 Jun 2023 16:00:53 +0000 From: Joey Gouly To: , Mark Rutland CC: , Joey Gouly Subject: [PATCH v2 2/2] aarch64: enable Permission Indirection Extension Date: Fri, 16 Jun 2023 17:00:36 +0100 Message-ID: <20230616160036.3825473-2-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230616160036.3825473-1-joey.gouly@arm.com> References: <20230616160036.3825473-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT065:EE_|DB8PR08MB5451:EE_|DBAEUR03FT028:EE_|AM7PR08MB5397:EE_ X-MS-Office365-Filtering-Correlation-Id: 86bbf7e7-7328-4088-23d9-08db6e82e314 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: ObpcbmWuaDzvyd1sSfZN1Zz0FLxO3DdAFWL4G2X8lkTmAXHuGaP0xqj7fnUVCUfFOBr9J4k2m5KBXfFy7jpuMmu8nsqcOdmPBh9K6aqmhvblxSEwUKCR684XR+U+sIJancvYshISr6kbMcf2X8JTAGqOZyOOdpa9XDcfykTB5QY/fC0PQRX5glkbfF+FCoYWwQNBs0HnJhpVO9FJul7paCstbeJ5pxo0oOHVJTn+rwQiZ0D1PL/S2MO6K/xsaE2pl+J77dV9YXBTjSVlSTgHseMWsXBHTbaKNW7Ya1xzaV3hA+IV46VBnYIV2Y08NsEgopxKgQsWsa5pJgUuZFgmNJ8GDk/Daw394BF7BDsjjRBGcQSKa+K/60tuMfQnbylLhm3EQwp34Z1YONBRXPuN+WTJgVZJ2XoxzY8NLRqe0y/P40Ru6KgAto8sWErZgpN+9PFo2w6+RYnquhTXnyi1wIch6zMG/OS9Y3G+tcO0ZIZHySElkZ0scPRC03iqaekMRYF9SHR8SXognCkUwIvFAW9LzdROZXsxzHyD8nUxN1NHpT11fv18rYd/8UigfegvTNI7MO2StUHNRToKL2tS7cBVuLKO7Oh8A0SkibtPZgc9pkwh+9po4wZIG67j/vDB0ikFHCmt7o+5EQUHjVkNbjigemSa+l/4Kj4ukfXNNeuKkyxrDtqpytwElYHP6H4icEGULG/WVxOWd3n8kKH8o9hMyyv3ntm0S2FCiIb3KTY5CbeHbkn/GxLHDmpPTikpN4PU1vRFMom5/4NwW40r2A== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(346002)(136003)(376002)(396003)(451199021)(46966006)(40470700004)(36840700001)(86362001)(82310400005)(36756003)(40460700003)(40480700001)(2906002)(26005)(44832011)(1076003)(5660300002)(186003)(36860700001)(426003)(336012)(47076005)(2616005)(83380400001)(70586007)(478600001)(54906003)(110136005)(70206006)(8676002)(8936002)(41300700001)(6666004)(4326008)(6636002)(7696005)(316002)(82740400003)(356005)(81166007)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Joey Gouly --- arch/aarch64/include/asm/cpu.h | 5 +++++ arch/aarch64/init.c | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 0213d53..d1f8fd9 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -55,6 +55,7 @@ #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) #define SCR_EL3_TCR2EN BIT(43) +#define SCR_EL3_PIEN BIT(45) #define HCR_EL2_RES1 BIT(1) @@ -78,6 +79,10 @@ #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) #define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) +#define ID_AA64MMFR3_EL1_S1PIE BITS(11, 8) +#define ID_AA64MMFR3_EL1_S2PIE BITS(15, 12) +#define ID_AA64MMFR3_EL1_S1POE BITS(19, 16) +#define ID_AA64MMFR3_EL1_S2POE BITS(23, 20) #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index e09e050..c4e91e4 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -42,6 +42,16 @@ static inline bool cpu_has_pauth(void) (mrs(ID_AA64ISAR2_EL1) & isar2_pauth); } +static inline bool cpu_has_permission_indirection(void) +{ + const unsigned long mask = ID_AA64MMFR3_EL1_S1PIE | + ID_AA64MMFR3_EL1_S2PIE | + ID_AA64MMFR3_EL1_S1POE | + ID_AA64MMFR3_EL1_S2POE; + + return mrs(ID_AA64MMFR3_EL1) & mask; +} + void cpu_init_el3(void) { unsigned long scr = SCR_EL3_RES1 | SCR_EL3_NS | SCR_EL3_HCE; @@ -70,6 +80,9 @@ void cpu_init_el3(void) msr(TCR2_EL1, 0); } + if (cpu_has_permission_indirection()) + scr |= SCR_EL3_PIEN; + if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2) scr |= SCR_EL3_ATA;