From patchwork Mon Jun 19 17:01:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13284838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D05DDEB64D9 for ; Mon, 19 Jun 2023 17:01:41 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551242.860680 (Exim 4.92) (envelope-from ) id 1qBIFm-0003PW-GU; Mon, 19 Jun 2023 17:01:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551242.860680; Mon, 19 Jun 2023 17:01:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFm-0003PP-CK; Mon, 19 Jun 2023 17:01:22 +0000 Received: by outflank-mailman (input) for mailman id 551242; Mon, 19 Jun 2023 17:01:20 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFk-0003Kd-Ox for xen-devel@lists.xenproject.org; Mon, 19 Jun 2023 17:01:20 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFk-0002e2-Am; Mon, 19 Jun 2023 17:01:20 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qBIFk-00079R-1n; Mon, 19 Jun 2023 17:01:20 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=f0Msc+xsVYLFDQx2YMgcMthu7/P+yNsRuDofE8DHCTI=; b=2hI+1r6bez1izKN5mYzfSlrs/9 m1HXM0JjawBY4PuhMeUvfOEFjgIIFJuYB1O57140gBQ0NU3z58+ibu68aAopE3zL7Jx2Uid1hxPBw h9N824YNpqhoNfnbNMN3dKj29TSlSGl0PxoJKS6dg0rIBgtM00UPuDwdtvxcW1VpFalk=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 1/7] xen/arm32: head: Add missing isb in setup_fixmap() Date: Mon, 19 Jun 2023 18:01:09 +0100 Message-Id: <20230619170115.81398-2-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619170115.81398-1-julien@xen.org> References: <20230619170115.81398-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Per the Arm Arm (ARM DDI 0406C.d A3.8.3): "The DMB and DSB memory barriers affect reads and writes to the memory system generated by load/store instructions and data or unified cache maintenance operations being executed by the processor. Instruction fetches or accesses caused by a hardware translation table access are not explicit accesses." In setup_fixmap(), we write the fixmap area and may be used soon after, for instance, to write to the UART. IOW, there could be hardware translation table access. So we need to ensure the 'dsb' has completed before continuing. Therefore add an 'isb'. Fixes: e79999e587d7 ("xen/arm32: head: Remove 1:1 mapping as soon as it is not used") Signed-off-by: Julien Grall Reviewed-by: Henry Wang Tested-by: Henry Wang Reviewed-by: Luca Fancellu Reviewed-by: Bertrand Marquis --- xen/arch/arm/arm32/head.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index f9f7be9588b1..6ca3329138e3 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -751,6 +751,11 @@ setup_fixmap: create_table_entry boot_second, xen_fixmap, r0, 2 /* Ensure any page table updates made above have occurred. */ dsb nshst + /* + * The fixmap area will be used soon after. So ensure no hardware + * translation happens before the dsb completes. + */ + isb mov pc, lr ENDPROC(setup_fixmap) From patchwork Mon Jun 19 17:01:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13284836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72B89EB64DB for ; Mon, 19 Jun 2023 17:01:37 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551243.860690 (Exim 4.92) (envelope-from ) id 1qBIFn-0003fM-N4; Mon, 19 Jun 2023 17:01:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551243.860690; Mon, 19 Jun 2023 17:01:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFn-0003fD-Jy; Mon, 19 Jun 2023 17:01:23 +0000 Received: by outflank-mailman (input) for mailman id 551243; Mon, 19 Jun 2023 17:01:21 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFl-0003PJ-SG for xen-devel@lists.xenproject.org; Mon, 19 Jun 2023 17:01:21 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFl-0002e8-I0; Mon, 19 Jun 2023 17:01:21 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qBIFl-00079R-AP; Mon, 19 Jun 2023 17:01:21 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=XCDJIqgFhmZ0JxJIz/CX3QdAY7V9+R7dcjMnAbPAVAE=; b=b7G86f2/m0YHDlxFFdfMktxZJS FuYmVBB/wK3s2CWthe5OwcpPFpnf6QsPtkDVNK5eW7hAjBWdSCsMq6Tpt/6tLCKvbGYW8eKB2rB1D 2ivqbwODXI6tEjaLVcaRFhYXb//cySMhPkad7kRm3RFV8TX2sUd+U0GrOHqYw8bJKg/o=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 2/7] xen/arm32: head: Add mising isb in switch_to_runtime_mapping() Date: Mon, 19 Jun 2023 18:01:10 +0100 Message-Id: <20230619170115.81398-3-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619170115.81398-1-julien@xen.org> References: <20230619170115.81398-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Per the Arm Arm (ARM DDI 0406C.d A3.8.3): "The DMB and DSB memory barriers affect reads and writes to the memory system generated by load/store instructions and data or unified cache maintenance operations being executed by the processor. Instruction fetches or accesses caused by a hardware translation table access are not explicit accesses." The function switch_to_runtime_mapping() is responsible to map the Xen at its runtime address if we were using the temporary area before jumping returning using a runtime address. So we need to ensure the 'dsb' has completed before continuing. Therefore add an 'isb'. Fixes: fbd9b5fb4c26 ("xen/arm32: head: Remove restriction where to load Xen") Signed-off-by: Julien Grall Reviewed-by: Henry Wang Tested-by: Henry Wang Reviewed-by: Luca Fancellu Reviewed-by: Bertrand Marquis --- xen/arch/arm/arm32/head.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 6ca3329138e3..b942e7e54d08 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -656,6 +656,11 @@ switch_to_runtime_mapping: /* Ensure any page table updates are visible before continuing */ dsb nsh + /* + * The function will return on the runtime mapping. So we want + * to prevent instruction fetch before the dsb completes. + */ + isb ready_to_switch: mov pc, lr From patchwork Mon Jun 19 17:01:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13284840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFD2FEB64DA for ; Mon, 19 Jun 2023 17:01:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551244.860700 (Exim 4.92) (envelope-from ) id 1qBIFo-0003vI-UP; Mon, 19 Jun 2023 17:01:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551244.860700; Mon, 19 Jun 2023 17:01:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFo-0003v5-RT; Mon, 19 Jun 2023 17:01:24 +0000 Received: by outflank-mailman (input) for mailman id 551244; Mon, 19 Jun 2023 17:01:23 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFn-0003a0-1I for xen-devel@lists.xenproject.org; Mon, 19 Jun 2023 17:01:23 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFm-0002eQ-Qi; Mon, 19 Jun 2023 17:01:22 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qBIFm-00079R-J2; Mon, 19 Jun 2023 17:01:22 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=AZgk+a7RNDOh2A2w6FC7dZLd0kw2EJlcWOaKZ6/xmw4=; b=oWFRU/Nui2FPz+c6D8HfjYv9kE 7UJr+ZMGk3FwaAhChv7+Jq/tFDBMGBl2OcdiB8lxzE9UJCT6/oUAksDrG7MNcwjJH6+ln8uRXwIjt i6zkzSAJOyqElzd0VyznmD9T3w5n3F2zG3yIUDgh2XSR7nj0cbOitDGgT4u8bXa5WEqI=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 3/7] xen/arm64: head: Add missing isb in setup_fixmap() Date: Mon, 19 Jun 2023 18:01:11 +0100 Message-Id: <20230619170115.81398-4-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619170115.81398-1-julien@xen.org> References: <20230619170115.81398-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall On older version of the Arm Arm (ARM DDI 0487E.a, B2-125) there were the following paragraph: "DMB and DSB instructions affect reads and writes to the memory system generated by Load/Store instructions and data or unified cache maintenance instructions being executed by the PE. Instruction fetches or accesses caused by a hardware translation table access are not explicit accesses." Newer revision (e.g. ARM DDI 0487J.a) doesn't have the second sentence (it might be somewhere else in the Arm Arm). But the interpretation is not much different. In setup_fixmap(), we write the fixmap area and may be used soon after, for instance, to write to the UART. IOW, there could be hardware translation table access. So we need to ensure the 'dsb' has completed before continuing. Therefore add an 'isb'. Fixes: 2b11c3646105 ("xen/arm64: head: Remove 1:1 mapping as soon as it is not used") Signed-off-by: Julien Grall Reviewed-by: Henry Wang Tested-by: Henry Wang Reviewed-by: Luca Fancellu Reviewed-by: Michal Orzel Reviewed-by: Bertrand Marquis --- xen/arch/arm/arm64/head.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index f37133cf7ccd..4ea64e70997b 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -769,6 +769,11 @@ setup_fixmap: create_table_entry boot_second, xen_fixmap, x0, 2, x1, x2, x3 /* Ensure any page table updates made above have occurred. */ dsb nshst + /* + * The fixmap area will be used soon after. So ensure no hardware + * translation happens before the dsb completes. + */ + isb ret ENDPROC(setup_fixmap) From patchwork Mon Jun 19 17:01:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13284835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0C2DEB64DA for ; Mon, 19 Jun 2023 17:01:35 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551245.860705 (Exim 4.92) (envelope-from ) id 1qBIFp-0003yw-A1; Mon, 19 Jun 2023 17:01:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551245.860705; Mon, 19 Jun 2023 17:01:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFp-0003yR-3b; Mon, 19 Jun 2023 17:01:25 +0000 Received: by outflank-mailman (input) for mailman id 551245; Mon, 19 Jun 2023 17:01:24 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFo-0003qc-Bf for xen-devel@lists.xenproject.org; Mon, 19 Jun 2023 17:01:24 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFo-0002eo-42; Mon, 19 Jun 2023 17:01:24 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qBIFn-00079R-Rf; Mon, 19 Jun 2023 17:01:24 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=SH8S9cGEeNkU74yrhDG+H2R2qeyKdQ/sIjdnJLK2qzg=; b=o3jppnO3+Xh0lCKXkbanOMK5CC 0nCAYBYCBY5nm9HJj9yP4/yILVsRX56mIwBZAgRM36foyDYC7ZvjLIevSsbXWtmcGf8Q3xRF1tJfP /ihkAa+LZFlsUK9jFAC3ikARzweed4ExmVKuiqhgJNysd6dRmPS8Un3WVyxxX6jaTHLU=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 4/7] xen/arm: page: Consolidate write_pte() and clarify the documentation Date: Mon, 19 Jun 2023 18:01:12 +0100 Message-Id: <20230619170115.81398-5-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619170115.81398-1-julien@xen.org> References: <20230619170115.81398-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall The implementation of write_pte() is pretty much the same on arm32 and arm64. So it would be good to consolidate it as this would help to clarify the requirements when using the helper. Take the opportunity to switch from assembly to call macros. Note there is a difference on arm32 because the option was not specified. But this meant 'sy' (system wide). Futhermore, the requirements for the ISB is incomplete. Per the Arm Arm, (Armv7 DDI406C.d A3.8.3 and Armv8 DDI 0487J.a B2.3.12), DSB will only affect explicit accesses. So an ISB is necessary after DSB to ensure the completion. Having an ISB after each update to the page-tables is probably too much, so let the caller add the instruction when it is convenient. Lastly, the barrier in write_pte() may be too restrictive but I haven't yet find the proper section(s) in the Arm Arm. Signed-off-by: Julien Grall ---- I am a bit split on whether we should add an ISB in write_pte(). It would make easier for the developper, but would likely force a pipeline flush too often. It might also be possible to drop the ISB (and even DSB) when updating stage-2 PTE (Linux already does it, see 120798d2e7d1). But I am not sure this is worth it in Xen. Reviewed-by: Henry Wang Tested-by: Henry Wang Reviewed-by: Bertrand Marquis --- xen/arch/arm/include/asm/arm32/page.h | 16 ---------------- xen/arch/arm/include/asm/arm64/page.h | 11 ----------- xen/arch/arm/include/asm/page.h | 17 +++++++++++++++++ 3 files changed, 17 insertions(+), 27 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/page.h b/xen/arch/arm/include/asm/arm32/page.h index 715a9e4fef48..6d1ff0636ce3 100644 --- a/xen/arch/arm/include/asm/arm32/page.h +++ b/xen/arch/arm/include/asm/arm32/page.h @@ -3,22 +3,6 @@ #ifndef __ASSEMBLY__ -/* Write a pagetable entry. - * - * If the table entry is changing a text mapping, it is responsibility - * of the caller to issue an ISB after write_pte. - */ -static inline void write_pte(lpae_t *p, lpae_t pte) -{ - asm volatile ( - /* Ensure any writes have completed with the old mappings. */ - "dsb;" - /* Safely write the entry (STRD is atomic on CPUs that support LPAE) */ - "strd %0, %H0, [%1];" - "dsb;" - : : "r" (pte.bits), "r" (p) : "memory"); -} - /* Inline ASM to invalidate dcache on register R (may be an inline asm operand) */ #define __invalidate_dcache_one(R) STORE_CP32(R, DCIMVAC) diff --git a/xen/arch/arm/include/asm/arm64/page.h b/xen/arch/arm/include/asm/arm64/page.h index 0cba2663733b..4f58c0382adc 100644 --- a/xen/arch/arm/include/asm/arm64/page.h +++ b/xen/arch/arm/include/asm/arm64/page.h @@ -5,17 +5,6 @@ #include -/* Write a pagetable entry */ -static inline void write_pte(lpae_t *p, lpae_t pte) -{ - asm volatile ( - /* Ensure any writes have completed with the old mappings. */ - "dsb sy;" - "str %0, [%1];" /* Write the entry */ - "dsb sy;" - : : "r" (pte.bits), "r" (p) : "memory"); -} - /* Inline ASM to invalidate dcache on register R (may be an inline asm operand) */ #define __invalidate_dcache_one(R) "dc ivac, %" #R ";" diff --git a/xen/arch/arm/include/asm/page.h b/xen/arch/arm/include/asm/page.h index e7cd62190c7f..ea96983ab976 100644 --- a/xen/arch/arm/include/asm/page.h +++ b/xen/arch/arm/include/asm/page.h @@ -126,6 +126,7 @@ #include #include #include +#include #include #if defined(CONFIG_ARM_32) @@ -237,6 +238,22 @@ static inline int clean_and_invalidate_dcache_va_range : : "r" (_p), "m" (*_p)); \ } while (0) +/* + * Write a pagetable entry. + * + * It is the responsibility of the caller to issue an ISB (if a new entry) + * or a TLB flush (if modified or removed) after write_pte(). + */ +static inline void write_pte(lpae_t *p, lpae_t pte) +{ + /* Ensure any writes have completed with the old mappings. */ + dsb(sy); + /* Safely write the entry. This should always be an atomic write. */ + write_atomic(p, pte); + dsb(sy); +} + + /* Flush the dcache for an entire page. */ void flush_page_to_ram(unsigned long mfn, bool sync_icache); From patchwork Mon Jun 19 17:01:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13284839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97156EB64DB for ; Mon, 19 Jun 2023 17:01:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551246.860720 (Exim 4.92) (envelope-from ) id 1qBIFq-0004Od-JX; Mon, 19 Jun 2023 17:01:26 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551246.860720; Mon, 19 Jun 2023 17:01:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFq-0004OP-Dk; Mon, 19 Jun 2023 17:01:26 +0000 Received: by outflank-mailman (input) for mailman id 551246; Mon, 19 Jun 2023 17:01:25 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFp-0004BY-MQ for xen-devel@lists.xenproject.org; Mon, 19 Jun 2023 17:01:25 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFp-0002f7-BR; Mon, 19 Jun 2023 17:01:25 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qBIFp-00079R-43; Mon, 19 Jun 2023 17:01:25 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=o/7iDTA3VqOW8+2Qi5rctGMLXOWeKouoykuCMLKWUGo=; b=M7jvehIVVy5FSRF3uLpCQZAzMO jQXxwm8KyBvQYsD/lands5Nz8cBJSki4dsg+nVmUrSnArcRS7I7K+YAu5ylo+ONaewS57xD/6v+/R zSISTdQCHGljRm5pfUXH9LYgteEjrMCoXo+nuxB5Q6L8fJZk2mHj6rf0xmdqwUGyouVE=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 5/7] xen/arm: pmap: Add missing ISB in arch_pmap_map() Date: Mon, 19 Jun 2023 18:01:13 +0100 Message-Id: <20230619170115.81398-6-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619170115.81398-1-julien@xen.org> References: <20230619170115.81398-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Per the Arm Arm, (Armv7 DDI406C.d A3.8.3 and Armv8 DDI 0487J.a B2.3.12): "The DMB and DSB memory barriers affect reads and writes to the memory system generated by load/store instructions and data or unified cache maintenance operations being executed by the processor. Instruction fetches or accesses caused by a hardware translation table access are not explicit accesses." Note that second sentence is not part of the newer Armv8 spec. But the interpretation is not much different. As the entry created by arch_pmap_map() will be used soon after pmap_map() returns, we want to ensure the DSB in write_pte() has completed. So add an ISB. Fixes: 4f17357b52f6 ("xen/arm: add Persistent Map (PMAP) infrastructure") Signed-off-by: Julien Grall Reviewed-by: Henry Wang Tested-by: Henry Wang Reviewed-by: Bertrand Marquis --- xen/arch/arm/include/asm/pmap.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/xen/arch/arm/include/asm/pmap.h b/xen/arch/arm/include/asm/pmap.h index e094d13dd282..bca3381796f3 100644 --- a/xen/arch/arm/include/asm/pmap.h +++ b/xen/arch/arm/include/asm/pmap.h @@ -15,6 +15,11 @@ static inline void arch_pmap_map(unsigned int slot, mfn_t mfn) pte = mfn_to_xen_entry(mfn, PAGE_HYPERVISOR_RW); pte.pt.table = 1; write_pte(entry, pte); + /* + * The new entry will be used very soon after arch_pmap_map() returns. + * So ensure the DSB in write_pte() has completed before continuing. + */ + isb(); } static inline void arch_pmap_unmap(unsigned int slot) From patchwork Mon Jun 19 17:01:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13284837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0FB37EB64D9 for ; Mon, 19 Jun 2023 17:01:39 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551247.860730 (Exim 4.92) (envelope-from ) id 1qBIFs-0004mZ-Rn; Mon, 19 Jun 2023 17:01:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551247.860730; Mon, 19 Jun 2023 17:01:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFs-0004mO-OS; Mon, 19 Jun 2023 17:01:28 +0000 Received: by outflank-mailman (input) for mailman id 551247; Mon, 19 Jun 2023 17:01:27 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFq-0004Y6-U7 for xen-devel@lists.xenproject.org; Mon, 19 Jun 2023 17:01:26 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFq-0002fP-K2; Mon, 19 Jun 2023 17:01:26 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qBIFq-00079R-Ci; Mon, 19 Jun 2023 17:01:26 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=Z5DRZNZmlBW9wLWM72auv5rCsE+gqkJPzk13KavQHZY=; b=hQHBgzPEL0IUqiiOdL9ZuROF+w e7n3xPToVnbSWxPv6sFGuKZ+s2VRKe6FV4sUneSINgB41LKNdnLdvMCDEHUOklzonZfgp6qYRsD4W yaVwyHS/OLAxjTd0Rf8OEUzA+GKkLFfZ55t3wbdENLRKVh2Fu6pPsCfElVwHCWyghOdo=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 6/7] xen/arm: mm: Add missing ISB in xen_pt_update() Date: Mon, 19 Jun 2023 18:01:14 +0100 Message-Id: <20230619170115.81398-7-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619170115.81398-1-julien@xen.org> References: <20230619170115.81398-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Per the Arm Arm, (Armv7 DDI406C.d A3.8.3 and Armv8 DDI 0487J.a B2.3.12): "The DMB and DSB memory barriers affect reads and writes to the memory system generated by load/store instructions and data or unified cache maintenance operations being executed by the processor. Instruction fetches or accesses caused by a hardware translation table access are not explicit accesses." Note that second sentence is not part of the newer Armv8 spec. But the interpretation is not much different. The updated entry will not be used until xen_pt_update() completes. So rather than adding the ISB after write_pte() in create_xen_table() and xen_pt-update_entry(), add it in xen_pt_update(). Also document the reasoning of the deferral after each write_pte() calls. Fixes: 07d11f63d03e ("xen/arm: mm: Avoid flushing the TLBs when mapping are inserted") Signed-off-by: Julien Grall Reviewed-by: Henry Wang Tested-by: Henry Wang Reviewed-by: Bertrand Marquis --- xen/arch/arm/mm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index e460249736c3..84e652799dd2 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -779,6 +779,11 @@ static int create_xen_table(lpae_t *entry) pte = mfn_to_xen_entry(mfn, MT_NORMAL); pte.pt.table = 1; write_pte(entry, pte); + /* + * No ISB here. It is deferred to xen_pt_update() as the new table + * will not be used for hardware translation table access as part of + * the mapping update. + */ return 0; } @@ -1017,6 +1022,10 @@ static int xen_pt_update_entry(mfn_t root, unsigned long virt, } write_pte(entry, pte); + /* + * No ISB or TLB flush here. They are deferred to xen_pt_update() + * as the entry will not be used as part of the mapping update. + */ rc = 0; @@ -1196,6 +1205,9 @@ static int xen_pt_update(unsigned long virt, /* * The TLBs flush can be safely skipped when a mapping is inserted * as we don't allow mapping replacement (see xen_pt_check_entry()). + * Although we still need an ISB to ensure any DSB in + * write_pte() will complete because the mapping may be used soon + * after. * * For all the other cases, the TLBs will be flushed unconditionally * even if the mapping has failed. This is because we may have @@ -1204,6 +1216,8 @@ static int xen_pt_update(unsigned long virt, */ if ( !((flags & _PAGE_PRESENT) && !mfn_eq(mfn, INVALID_MFN)) ) flush_xen_tlb_range_va(virt, PAGE_SIZE * nr_mfns); + else + isb(); spin_unlock(&xen_pt_lock); From patchwork Mon Jun 19 17:01:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13284841 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F187EB64D9 for ; Mon, 19 Jun 2023 17:01:47 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551248.860736 (Exim 4.92) (envelope-from ) id 1qBIFt-0004uF-Fw; Mon, 19 Jun 2023 17:01:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551248.860736; Mon, 19 Jun 2023 17:01:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFt-0004rI-9K; Mon, 19 Jun 2023 17:01:29 +0000 Received: by outflank-mailman (input) for mailman id 551248; Mon, 19 Jun 2023 17:01:28 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFs-0004l9-3o for xen-devel@lists.xenproject.org; Mon, 19 Jun 2023 17:01:28 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBIFr-0002fd-Sj; Mon, 19 Jun 2023 17:01:27 +0000 Received: from 54-240-197-232.amazon.com ([54.240.197.232] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1qBIFr-00079R-LM; Mon, 19 Jun 2023 17:01:27 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=kb0w434WqcCO6B2fvVViD2fzwzZIeQ5lguZBKStXu+g=; b=VA76lUbCPBM1ZD3fyiyCAAzR6x skIaKc9psvsiUMVqfbXfeup2ya+mrvIvlBSgtWTgq45muJruisir4eP51MLSeq5neKLkuNdAsxWAg rKj2HQErZCoPdkRJq0BHzI5xwuqxS2rSMzVZ2b2uUzFzlIhUe3RurhounxKXjpUI27hU=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: Luca.Fancellu@arm.com, michal.orzel@amd.com, Henry.Wang@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH 7/7] xen/arm32: head: Widen the use of the temporary mapping Date: Mon, 19 Jun 2023 18:01:15 +0100 Message-Id: <20230619170115.81398-8-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230619170115.81398-1-julien@xen.org> References: <20230619170115.81398-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall At the moment, the temporary mapping is only used when the virtual runtime region of Xen is clashing with the physical region. In follow-up patches, we will rework how secondary CPU bring-up works and it will be convenient to use the fixmap area for accessing the root page-table (it is per-cpu). Rework the code to use temporary mapping when the Xen physical address is not overlapping with the temporary mapping. This also has the advantage to simplify the logic to identity map Xen. Signed-off-by: Julien Grall Reviewed-by: Henry Wang Reviewed-by: Michal Orzel ---- This patch was originally part of [1] but it was reverted due to Xen not booting on the Arndale. The first patch of this series is fixing it (confirmed by booting on the Arndale). So I am including this patch. Also all the tags but the tested-by have been kept because the code has not changed. Happy to drop any if there are any concerns. [1] https://lore.kernel.org/xen-devel/20230416143211.72227-1-julien@xen.org/ Changelog from the previous series: Changes in v6: - Add Henry's reviewed-by and tested-by tag - Add Michal's reviewed-by - Add newline in remove_identity_mapping for clarity Changes in v5: - Fix typo in a comment - No need to link boot_{second, third}_id again if we need to create a temporary area. Changes in v3: - Resolve conflicts after switching from "ldr rX,