From patchwork Tue Jun 20 10:47:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 979FBEB64D7 for ; Tue, 20 Jun 2023 10:47:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231501AbjFTKro (ORCPT ); Tue, 20 Jun 2023 06:47:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232276AbjFTKrn (ORCPT ); Tue, 20 Jun 2023 06:47:43 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32E681A5 for ; Tue, 20 Jun 2023 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Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 01/11] mmc: core: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:12 +0200 Message-Id: <20230620104722.16465-1-marex@denx.de> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- include/linux/mmc/core.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index 6efec0b9820c1..23db84630ae8a 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -26,16 +26,16 @@ enum mmc_blk_status { struct mmc_command { u32 opcode; u32 arg; -#define MMC_CMD23_ARG_REL_WR (1 << 31) +#define MMC_CMD23_ARG_REL_WR BIT(31) #define MMC_CMD23_ARG_PACKED ((0 << 31) | (1 << 30)) -#define MMC_CMD23_ARG_TAG_REQ (1 << 29) +#define MMC_CMD23_ARG_TAG_REQ BIT(29) u32 resp[4]; unsigned int flags; /* expected response type */ -#define MMC_RSP_PRESENT (1 << 0) -#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ +#define MMC_RSP_PRESENT BIT(0) +#define MMC_RSP_136 BIT(1) /* 136 bit response */ +#define MMC_RSP_CRC BIT(2) /* expect valid crc */ +#define MMC_RSP_BUSY BIT(3) /* card may send busy */ +#define MMC_RSP_OPCODE BIT(4) /* response contains opcode */ #define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ #define MMC_CMD_AC (0 << 5) @@ -43,10 +43,10 @@ struct mmc_command { #define MMC_CMD_BC (2 << 5) #define MMC_CMD_BCR (3 << 5) -#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ -#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ -#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ -#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ +#define MMC_RSP_SPI_S1 BIT(7) /* one status byte */ +#define MMC_RSP_SPI_S2 BIT(8) /* second byte */ +#define MMC_RSP_SPI_B4 BIT(9) /* four data bytes */ +#define MMC_RSP_SPI_BUSY BIT(10) /* card may send busy */ /* * These are the native response types, and correspond to valid bit From patchwork Tue Jun 20 10:47:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BF56EB64D8 for ; Tue, 20 Jun 2023 10:47:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232230AbjFTKrq (ORCPT ); Tue, 20 Jun 2023 06:47:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232269AbjFTKrp (ORCPT ); Tue, 20 Jun 2023 06:47:45 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C82901A8 for ; Tue, 20 Jun 2023 03:47:42 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id B136D846D9; Tue, 20 Jun 2023 12:47:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258061; bh=up06Owk+NDTUAaAvH70nAKZwmnz3/pTSTRxylfq3s98=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N7BxCKYy18gPBZbNoEzmm0R9WELVbtjRFVmvnAI7fw3BTiml8ap+0L9KYTp8VXIbj xwwNpl/tm/aUkilPM2YKLLHnOcJsBzyQyOcuyt/brlfmDh3UuwnYQhRCEJFqFFQxUH DsFzL/nfONSk6mNiKPwJWzJ4nI5GMXXPixNGzCYWURY1UP/3TgL6nS/yyg0IMeIR00 BYhRl+OgnRDBDsV8qzAbgxn6he/f8ZxvDm1Yxu2HQGRaUgsJifp3aMnMZNJa/iAvWM Sz4ZYQTAqhdFO0AudbEDFL95fpWPdSFYfk2Piqr+5U5iFN77YbE1KV2JMNSi3SSJuI cF2dERxC9bp4g== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 02/11] mmc: card: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:13 +0200 Message-Id: <20230620104722.16465-2-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- drivers/mmc/core/card.h | 12 +++--- include/linux/mmc/card.h | 86 ++++++++++++++++++++-------------------- 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/mmc/core/card.h b/drivers/mmc/core/card.h index 4edf9057fa79d..1040335f64241 100644 --- a/drivers/mmc/core/card.h +++ b/drivers/mmc/core/card.h @@ -17,12 +17,12 @@ #define mmc_dev_to_card(d) container_of(d, struct mmc_card, dev) /* Card states */ -#define MMC_STATE_PRESENT (1<<0) /* present in sysfs */ -#define MMC_STATE_READONLY (1<<1) /* card is read-only */ -#define MMC_STATE_BLOCKADDR (1<<2) /* card uses block-addressing */ -#define MMC_CARD_SDXC (1<<3) /* card is SDXC */ -#define MMC_CARD_REMOVED (1<<4) /* card has been removed */ -#define MMC_STATE_SUSPENDED (1<<5) /* card is suspended */ +#define MMC_STATE_PRESENT BIT(0) /* present in sysfs */ +#define MMC_STATE_READONLY BIT(1) /* card is read-only */ +#define MMC_STATE_BLOCKADDR BIT(2) /* card uses block-addressing */ +#define MMC_CARD_SDXC BIT(3) /* card is SDXC */ +#define MMC_CARD_REMOVED BIT(4) /* card has been removed */ +#define MMC_STATE_SUSPENDED BIT(5) /* card is suspended */ #define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT) #define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index daa2f40d9ce65..5e8f7ed595098 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -135,13 +135,13 @@ struct sd_scr { unsigned char sda_spec4; unsigned char sda_specx; unsigned char bus_widths; -#define SD_SCR_BUS_WIDTH_1 (1<<0) -#define SD_SCR_BUS_WIDTH_4 (1<<2) +#define SD_SCR_BUS_WIDTH_1 BIT(0) +#define SD_SCR_BUS_WIDTH_4 BIT(2) unsigned char cmds; -#define SD_SCR_CMD20_SUPPORT (1<<0) -#define SD_SCR_CMD23_SUPPORT (1<<1) -#define SD_SCR_CMD48_SUPPORT (1<<2) -#define SD_SCR_CMD58_SUPPORT (1<<3) +#define SD_SCR_CMD20_SUPPORT BIT(0) +#define SD_SCR_CMD23_SUPPORT BIT(1) +#define SD_SCR_CMD48_SUPPORT BIT(2) +#define SD_SCR_CMD58_SUPPORT BIT(3) }; struct sd_ssr { @@ -168,12 +168,12 @@ struct sd_switch_caps { #define UHS_SDR104_BUS_SPEED 3 #define UHS_DDR50_BUS_SPEED 4 -#define SD_MODE_HIGH_SPEED (1 << HIGH_SPEED_BUS_SPEED) -#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED) -#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED) -#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED) -#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED) -#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED) +#define SD_MODE_HIGH_SPEED BIT(HIGH_SPEED_BUS_SPEED) +#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED) +#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED) +#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED) +#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED) +#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED) unsigned int sd3_drv_type; #define SD_DRIVER_TYPE_B 0x01 #define SD_DRIVER_TYPE_A 0x02 @@ -186,10 +186,10 @@ struct sd_switch_caps { #define SD_SET_CURRENT_LIMIT_800 3 #define SD_SET_CURRENT_NO_CHANGE (-1) -#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200) -#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400) -#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600) -#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800) +#define SD_MAX_CURRENT_200 BIT(SD_SET_CURRENT_LIMIT_200) +#define SD_MAX_CURRENT_400 BIT(SD_SET_CURRENT_LIMIT_400) +#define SD_MAX_CURRENT_600 BIT(SD_SET_CURRENT_LIMIT_600) +#define SD_MAX_CURRENT_800 BIT(SD_SET_CURRENT_LIMIT_800) }; struct sd_ext_reg { @@ -200,15 +200,15 @@ struct sd_ext_reg { u8 feature_enabled; u8 feature_support; /* Power Management Function. */ -#define SD_EXT_POWER_OFF_NOTIFY (1<<0) -#define SD_EXT_POWER_SUSTENANCE (1<<1) -#define SD_EXT_POWER_DOWN_MODE (1<<2) +#define SD_EXT_POWER_OFF_NOTIFY BIT(0) +#define SD_EXT_POWER_SUSTENANCE BIT(1) +#define SD_EXT_POWER_DOWN_MODE BIT(2) /* Performance Enhancement Function. */ -#define SD_EXT_PERF_FX_EVENT (1<<0) -#define SD_EXT_PERF_CARD_MAINT (1<<1) -#define SD_EXT_PERF_HOST_MAINT (1<<2) -#define SD_EXT_PERF_CACHE (1<<3) -#define SD_EXT_PERF_CMD_QUEUE (1<<4) +#define SD_EXT_PERF_FX_EVENT BIT(0) +#define SD_EXT_PERF_CARD_MAINT BIT(1) +#define SD_EXT_PERF_HOST_MAINT BIT(2) +#define SD_EXT_PERF_CACHE BIT(3) +#define SD_EXT_PERF_CMD_QUEUE BIT(4) }; struct sdio_cccr { @@ -255,10 +255,10 @@ struct mmc_part { char name[MAX_MMC_PART_NAME_LEN]; bool force_ro; /* to make boot parts RO by default */ unsigned int area_type; -#define MMC_BLK_DATA_AREA_MAIN (1<<0) -#define MMC_BLK_DATA_AREA_BOOT (1<<1) -#define MMC_BLK_DATA_AREA_GP (1<<2) -#define MMC_BLK_DATA_AREA_RPMB (1<<3) +#define MMC_BLK_DATA_AREA_MAIN BIT(0) +#define MMC_BLK_DATA_AREA_BOOT BIT(1) +#define MMC_BLK_DATA_AREA_GP BIT(2) +#define MMC_BLK_DATA_AREA_RPMB BIT(3) }; /* @@ -277,24 +277,24 @@ struct mmc_card { unsigned int state; /* (our) card state */ unsigned int quirks; /* card quirks */ unsigned int quirk_max_rate; /* max rate set by quirks */ -#define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */ -#define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */ +#define MMC_QUIRK_LENIENT_FN0 BIT(0) /* allow SDIO FN0 writes outside of the VS CCCR range */ +#define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE BIT(1) /* use func->cur_blksize */ /* for byte mode */ -#define MMC_QUIRK_NONSTD_SDIO (1<<2) /* non-standard SDIO card attached */ +#define MMC_QUIRK_NONSTD_SDIO BIT(2) /* non-standard SDIO card attached */ /* (missing CIA registers) */ -#define MMC_QUIRK_NONSTD_FUNC_IF (1<<4) /* SDIO card has nonstd function interfaces */ -#define MMC_QUIRK_DISABLE_CD (1<<5) /* disconnect CD/DAT[3] resistor */ -#define MMC_QUIRK_INAND_CMD38 (1<<6) /* iNAND devices have broken CMD38 */ -#define MMC_QUIRK_BLK_NO_CMD23 (1<<7) /* Avoid CMD23 for regular multiblock */ -#define MMC_QUIRK_BROKEN_BYTE_MODE_512 (1<<8) /* Avoid sending 512 bytes in */ +#define MMC_QUIRK_NONSTD_FUNC_IF BIT(4) /* SDIO card has nonstd function interfaces */ +#define MMC_QUIRK_DISABLE_CD BIT(5) /* disconnect CD/DAT[3] resistor */ +#define MMC_QUIRK_INAND_CMD38 BIT(6) /* iNAND devices have broken CMD38 */ +#define MMC_QUIRK_BLK_NO_CMD23 BIT(7) /* Avoid CMD23 for regular multiblock */ +#define MMC_QUIRK_BROKEN_BYTE_MODE_512 BIT(8) /* Avoid sending 512 bytes in */ /* byte mode */ -#define MMC_QUIRK_LONG_READ_TIME (1<<9) /* Data read time > CSD says */ -#define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN (1<<10) /* Skip secure for erase/trim */ -#define MMC_QUIRK_BROKEN_IRQ_POLLING (1<<11) /* Polling SDIO_CCCR_INTx could create a fake interrupt */ -#define MMC_QUIRK_TRIM_BROKEN (1<<12) /* Skip trim */ -#define MMC_QUIRK_BROKEN_HPI (1<<13) /* Disable broken HPI support */ -#define MMC_QUIRK_BROKEN_SD_DISCARD (1<<14) /* Disable broken SD discard support */ -#define MMC_QUIRK_BROKEN_SD_CACHE (1<<15) /* Disable broken SD cache support */ +#define MMC_QUIRK_LONG_READ_TIME BIT(9) /* Data read time > CSD says */ +#define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN BIT(10) /* Skip secure for erase/trim */ +#define MMC_QUIRK_BROKEN_IRQ_POLLING BIT(11) /* Polling SDIO_CCCR_INTx could create a fake interrupt */ +#define MMC_QUIRK_TRIM_BROKEN BIT(12) /* Skip trim */ +#define MMC_QUIRK_BROKEN_HPI BIT(13) /* Disable broken HPI support */ +#define MMC_QUIRK_BROKEN_SD_DISCARD BIT(14) /* Disable broken SD discard support */ +#define MMC_QUIRK_BROKEN_SD_CACHE BIT(15) /* Disable broken SD cache support */ bool reenable_cmdq; /* Re-enable Command Queue */ From patchwork Tue Jun 20 10:47:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99246EB64D7 for ; Tue, 20 Jun 2023 10:47:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232296AbjFTKrr (ORCPT ); Tue, 20 Jun 2023 06:47:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232278AbjFTKrp (ORCPT ); Tue, 20 Jun 2023 06:47:45 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0571A8F for ; Tue, 20 Jun 2023 03:47:43 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 395178474B; Tue, 20 Jun 2023 12:47:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258061; bh=p9+WamblI8WBdLqm4ibnnaJzlMEhpVgdQhNNQwSTpLU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CoN4bEDkYUfvI15yrhTLTwwsKlUr87DDYde+CD3MnkNSmPt2e9wMa1yLneCCCU5Jw zcambEXF1dXUU7CZd8PVPuDJn6Nq9HDhKwtSZ/k1SCCzWXadsjlFXHfTW7eCa5sbBP YgGcqj2In4rklKVOt/epyROwGMXjTZIZmJ7o8d7MJZmkIKewOKgZLEWCaQL2+bQcIs xeGUD/CEEBGMJkr9Kb98nkZZZkX7Tr0IhmBCS+rbar7fJ1Kd8HaOLW+c9HTmG37tNH RIii9xVjp9CYJHldaGpK8pET/Fai18r3Ryy+Q3SvV6SMG/kr89w/jDHUntNa8q3Ixi q9d/e98lFUSTA== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 03/11] mmc: host: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:14 +0200 Message-Id: <20230620104722.16465-3-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- include/linux/mmc/host.h | 108 +++++++++++++++++++-------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 461d1543893bf..71084a5ed6a04 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -349,78 +349,78 @@ struct mmc_host { u32 caps; /* Host capabilities */ -#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */ -#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */ -#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */ -#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */ -#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */ -#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */ -#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */ -#define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */ -#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ -#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ -#define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */ -#define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */ -#define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */ +#define MMC_CAP_4_BIT_DATA BIT(0) /* Can the host do 4 bit transfers */ +#define MMC_CAP_MMC_HIGHSPEED BIT(1) /* Can do MMC high-speed timing */ +#define MMC_CAP_SD_HIGHSPEED BIT(2) /* Can do SD high-speed timing */ +#define MMC_CAP_SDIO_IRQ BIT(3) /* Can signal pending SDIO IRQs */ +#define MMC_CAP_SPI BIT(4) /* Talks only SPI protocols */ +#define MMC_CAP_NEEDS_POLL BIT(5) /* Needs polling for card-detection */ +#define MMC_CAP_8_BIT_DATA BIT(6) /* Can the host do 8 bit transfers */ +#define MMC_CAP_AGGRESSIVE_PM BIT(7) /* Suspend (e)MMC/SD at idle */ +#define MMC_CAP_NONREMOVABLE BIT(8) /* Nonremovable e.g. eMMC */ +#define MMC_CAP_WAIT_WHILE_BUSY BIT(9) /* Waits while card is busy */ +#define MMC_CAP_3_3V_DDR BIT(11) /* Host supports eMMC DDR 3.3V */ +#define MMC_CAP_1_8V_DDR BIT(12) /* Host supports eMMC DDR 1.8V */ +#define MMC_CAP_1_2V_DDR BIT(13) /* Host supports eMMC DDR 1.2V */ #define MMC_CAP_DDR (MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | \ MMC_CAP_1_2V_DDR) -#define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */ -#define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */ -#define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */ -#define MMC_CAP_UHS_SDR25 (1 << 17) /* Host supports UHS SDR25 mode */ -#define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */ -#define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */ -#define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */ +#define MMC_CAP_POWER_OFF_CARD BIT(14) /* Can power off after boot */ +#define MMC_CAP_BUS_WIDTH_TEST BIT(15) /* CMD14/CMD19 bus width ok */ +#define MMC_CAP_UHS_SDR12 BIT(16) /* Host supports UHS SDR12 mode */ +#define MMC_CAP_UHS_SDR25 BIT(17) /* Host supports UHS SDR25 mode */ +#define MMC_CAP_UHS_SDR50 BIT(18) /* Host supports UHS SDR50 mode */ +#define MMC_CAP_UHS_SDR104 BIT(19) /* Host supports UHS SDR104 mode */ +#define MMC_CAP_UHS_DDR50 BIT(20) /* Host supports UHS DDR50 mode */ #define MMC_CAP_UHS (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | \ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | \ MMC_CAP_UHS_DDR50) -#define MMC_CAP_SYNC_RUNTIME_PM (1 << 21) /* Synced runtime PM suspends. */ -#define MMC_CAP_NEED_RSP_BUSY (1 << 22) /* Commands with R1B can't use R1. */ -#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ -#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ -#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ -#define MMC_CAP_DONE_COMPLETE (1 << 27) /* RW reqs can be completed within mmc_request_done() */ -#define MMC_CAP_CD_WAKE (1 << 28) /* Enable card detect wake */ -#define MMC_CAP_CMD_DURING_TFR (1 << 29) /* Commands during data transfer */ -#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */ -#define MMC_CAP_HW_RESET (1 << 31) /* Reset the eMMC card via RST_n */ +#define MMC_CAP_SYNC_RUNTIME_PM BIT(21) /* Synced runtime PM suspends. */ +#define MMC_CAP_NEED_RSP_BUSY BIT(22) /* Commands with R1B can't use R1. */ +#define MMC_CAP_DRIVER_TYPE_A BIT(23) /* Host supports Driver Type A */ +#define MMC_CAP_DRIVER_TYPE_C BIT(24) /* Host supports Driver Type C */ +#define MMC_CAP_DRIVER_TYPE_D BIT(25) /* Host supports Driver Type D */ +#define MMC_CAP_DONE_COMPLETE BIT(27) /* RW reqs can be completed within mmc_request_done() */ +#define MMC_CAP_CD_WAKE BIT(28) /* Enable card detect wake */ +#define MMC_CAP_CMD_DURING_TFR BIT(29) /* Commands during data transfer */ +#define MMC_CAP_CMD23 BIT(30) /* CMD23 supported. */ +#define MMC_CAP_HW_RESET BIT(31) /* Reset the eMMC card via RST_n */ u32 caps2; /* More host capabilities */ -#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ -#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */ -#define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1 << 3) /* Can do full power cycle in suspend */ -#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ -#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ +#define MMC_CAP2_BOOTPART_NOACC BIT(0) /* Boot partition no access */ +#define MMC_CAP2_FULL_PWR_CYCLE BIT(2) /* Can do full power cycle */ +#define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND BIT(3) /* Can do full power cycle in suspend */ +#define MMC_CAP2_HS200_1_8V_SDR BIT(5) /* can support */ +#define MMC_CAP2_HS200_1_2V_SDR BIT(6) /* can support */ #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ MMC_CAP2_HS200_1_2V_SDR) -#define MMC_CAP2_SD_EXP (1 << 7) /* SD express via PCIe */ -#define MMC_CAP2_SD_EXP_1_2V (1 << 8) /* SD express 1.2V */ -#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ -#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ -#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ -#define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */ -#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */ +#define MMC_CAP2_SD_EXP BIT(7) /* SD express via PCIe */ +#define MMC_CAP2_SD_EXP_1_2V BIT(8) /* SD express 1.2V */ +#define MMC_CAP2_CD_ACTIVE_HIGH BIT(10) /* Card-detect signal active high */ +#define MMC_CAP2_RO_ACTIVE_HIGH BIT(11) /* Write-protect signal active high */ +#define MMC_CAP2_NO_PRESCAN_POWERUP BIT(14) /* Don't power up before scan */ +#define MMC_CAP2_HS400_1_8V BIT(15) /* Can support HS400 1.8V */ +#define MMC_CAP2_HS400_1_2V BIT(16) /* Can support HS400 1.2V */ #define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \ MMC_CAP2_HS400_1_2V) #define MMC_CAP2_HSX00_1_8V (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V) #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) -#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) -#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */ -#define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */ -#define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */ -#define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */ -#define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */ -#define MMC_CAP2_CQE (1 << 23) /* Has eMMC command queue engine */ -#define MMC_CAP2_CQE_DCMD (1 << 24) /* CQE can issue a direct command */ -#define MMC_CAP2_AVOID_3_3V (1 << 25) /* Host must negotiate down from 3.3V */ -#define MMC_CAP2_MERGE_CAPABLE (1 << 26) /* Host can merge a segment over the segment size */ +#define MMC_CAP2_SDIO_IRQ_NOTHREAD BIT(17) +#define MMC_CAP2_NO_WRITE_PROTECT BIT(18) /* No physical write protect pin, assume that card is always read-write */ +#define MMC_CAP2_NO_SDIO BIT(19) /* Do not send SDIO commands during initialization */ +#define MMC_CAP2_HS400_ES BIT(20) /* Host supports enhanced strobe */ +#define MMC_CAP2_NO_SD BIT(21) /* Do not send SD commands during initialization */ +#define MMC_CAP2_NO_MMC BIT(22) /* Do not send (e)MMC commands during initialization */ +#define MMC_CAP2_CQE BIT(23) /* Has eMMC command queue engine */ +#define MMC_CAP2_CQE_DCMD BIT(24) /* CQE can issue a direct command */ +#define MMC_CAP2_AVOID_3_3V BIT(25) /* Host must negotiate down from 3.3V */ +#define MMC_CAP2_MERGE_CAPABLE BIT(26) /* Host can merge a segment over the segment size */ #ifdef CONFIG_MMC_CRYPTO -#define MMC_CAP2_CRYPTO (1 << 27) /* Host supports inline encryption */ +#define MMC_CAP2_CRYPTO BIT(27) /* Host supports inline encryption */ #else #define MMC_CAP2_CRYPTO 0 #endif -#define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */ +#define MMC_CAP2_ALT_GPT_TEGRA BIT(28) /* Host with eMMC that has GPT entry at a non-standard location */ int fixed_drv_type; /* fixed driver type for non-removable media */ From patchwork Tue Jun 20 10:47:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 782B8EB64D7 for ; Tue, 20 Jun 2023 10:47:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232269AbjFTKrw (ORCPT ); Tue, 20 Jun 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b=uAfunrtdHVeyi7YwYjPnzeQeOrEtcq8iFCNuCutSZRQLTVaA3qtpFv67KOwT8l4LO Yi+Dt23wBBqAIObm+/z/ROHV1Oj/ca6VV+JnS9hQe6opFIKuRKX0hm868Elv9BRrJm GnRAa7GawrIytBD1L/jn8St6kE+V5KePluKEiYKgqeScirU5oT8olgOJLcGWRjNDVQ 37ARZkhsWjfyTJ+oseAXTswm+/NQvZokOAqiHiGPpKxn0rQ3n8A1uRIolwp2JRzYNn LCV6VBOm3tMMS1RoOuoVLuHoFz8nCqUSg6iGJEzpZYic2nBr/rFFyj2kOwBIbbu4Kp o5lhMbO5mQMsw== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 04/11] mmc: mmc: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:15 +0200 Message-Id: <20230620104722.16465-4-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- include/linux/mmc/mmc.h | 128 ++++++++++++++++++++-------------------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h index 6f7993803ee78..bbd3678e87aa7 100644 --- a/include/linux/mmc/mmc.h +++ b/include/linux/mmc/mmc.h @@ -131,31 +131,31 @@ static inline bool mmc_op_tuning(u32 opcode) c : clear by read */ -#define R1_OUT_OF_RANGE (1 << 31) /* er, c */ -#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ -#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ -#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ -#define R1_ERASE_PARAM (1 << 27) /* ex, c */ -#define R1_WP_VIOLATION (1 << 26) /* erx, c */ -#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ -#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ -#define R1_COM_CRC_ERROR (1 << 23) /* er, b */ -#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ -#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ -#define R1_CC_ERROR (1 << 20) /* erx, c */ -#define R1_ERROR (1 << 19) /* erx, c */ -#define R1_UNDERRUN (1 << 18) /* ex, c */ -#define R1_OVERRUN (1 << 17) /* ex, c */ -#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ -#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ -#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ -#define R1_ERASE_RESET (1 << 13) /* sr, c */ +#define R1_OUT_OF_RANGE BIT(31) /* er, c */ +#define R1_ADDRESS_ERROR BIT(30) /* erx, c */ +#define R1_BLOCK_LEN_ERROR BIT(29) /* er, c */ +#define R1_ERASE_SEQ_ERROR BIT(28) /* er, c */ +#define R1_ERASE_PARAM BIT(27) /* ex, c */ +#define R1_WP_VIOLATION BIT(26) /* erx, c */ +#define R1_CARD_IS_LOCKED BIT(25) /* sx, a */ +#define R1_LOCK_UNLOCK_FAILED BIT(24) /* erx, c */ +#define R1_COM_CRC_ERROR BIT(23) /* er, b */ +#define R1_ILLEGAL_COMMAND BIT(22) /* er, b */ +#define R1_CARD_ECC_FAILED BIT(21) /* ex, c */ +#define R1_CC_ERROR BIT(20) /* erx, c */ +#define R1_ERROR BIT(19) /* erx, c */ +#define R1_UNDERRUN BIT(18) /* ex, c */ +#define R1_OVERRUN BIT(17) /* ex, c */ +#define R1_CID_CSD_OVERWRITE BIT(16) /* erx, c, CID/CSD overwrite */ +#define R1_WP_ERASE_SKIP BIT(15) /* sx, c */ +#define R1_CARD_ECC_DISABLED BIT(14) /* sx, a */ +#define R1_ERASE_RESET BIT(13) /* sr, c */ #define R1_STATUS(x) (x & 0xFFF9A000) #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ -#define R1_READY_FOR_DATA (1 << 8) /* sx, a */ -#define R1_SWITCH_ERROR (1 << 7) /* sx, c */ -#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */ -#define R1_APP_CMD (1 << 5) /* sr, c */ +#define R1_READY_FOR_DATA BIT(8) /* sx, a */ +#define R1_SWITCH_ERROR BIT(7) /* sx, c */ +#define R1_EXCEPTION_EVENT BIT(6) /* sr, a */ +#define R1_APP_CMD BIT(5) /* sr, c */ #define R1_STATE_IDLE 0 #define R1_STATE_READY 1 @@ -181,23 +181,23 @@ static inline bool mmc_ready_for_data(u32 status) * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS * R1 is the low order byte; R2 is the next highest byte, when present. */ -#define R1_SPI_IDLE (1 << 0) -#define R1_SPI_ERASE_RESET (1 << 1) -#define R1_SPI_ILLEGAL_COMMAND (1 << 2) -#define R1_SPI_COM_CRC (1 << 3) -#define R1_SPI_ERASE_SEQ (1 << 4) -#define R1_SPI_ADDRESS (1 << 5) -#define R1_SPI_PARAMETER (1 << 6) +#define R1_SPI_IDLE BIT(0) +#define R1_SPI_ERASE_RESET BIT(1) +#define R1_SPI_ILLEGAL_COMMAND BIT(2) +#define R1_SPI_COM_CRC BIT(3) +#define R1_SPI_ERASE_SEQ BIT(4) +#define R1_SPI_ADDRESS BIT(5) +#define R1_SPI_PARAMETER BIT(6) /* R1 bit 7 is always zero */ -#define R2_SPI_CARD_LOCKED (1 << 8) -#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ +#define R2_SPI_CARD_LOCKED BIT(8) +#define R2_SPI_WP_ERASE_SKIP BIT(9) /* or lock/unlock fail */ #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP -#define R2_SPI_ERROR (1 << 10) -#define R2_SPI_CC_ERROR (1 << 11) -#define R2_SPI_CARD_ECC_ERROR (1 << 12) -#define R2_SPI_WP_VIOLATION (1 << 13) -#define R2_SPI_ERASE_PARAM (1 << 14) -#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ +#define R2_SPI_ERROR BIT(10) +#define R2_SPI_CC_ERROR BIT(11) +#define R2_SPI_CARD_ECC_ERROR BIT(12) +#define R2_SPI_WP_VIOLATION BIT(13) +#define R2_SPI_ERASE_PARAM BIT(14) +#define R2_SPI_OUT_OF_RANGE BIT(15) /* or CSD overwrite */ #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE /* @@ -208,28 +208,28 @@ static inline bool mmc_ready_for_data(u32 status) /* * Card Command Classes (CCC) */ -#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ +#define CCC_BASIC BIT(0) /* (0) Basic protocol functions */ /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ /* (and for SPI, CMD58,59) */ -#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ +#define CCC_STREAM_READ BIT(1) /* (1) Stream read commands */ /* (CMD11) */ -#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ +#define CCC_BLOCK_READ BIT(2) /* (2) Block read commands */ /* (CMD16,17,18) */ -#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ +#define CCC_STREAM_WRITE BIT(3) /* (3) Stream write commands */ /* (CMD20) */ -#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ +#define CCC_BLOCK_WRITE BIT(4) /* (4) Block write commands */ /* (CMD16,24,25,26,27) */ -#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ +#define CCC_ERASE BIT(5) /* (5) Ability to erase blocks */ /* (CMD32,33,34,35,36,37,38,39) */ -#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ +#define CCC_WRITE_PROT BIT(6) /* (6) Able to write protect blocks */ /* (CMD28,29,30) */ -#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ +#define CCC_LOCK_CARD BIT(7) /* (7) Able to lock down card */ /* (CMD16,CMD42) */ -#define CCC_APP_SPEC (1<<8) /* (8) Application specific */ +#define CCC_APP_SPEC BIT(8) /* (8) Application specific */ /* (CMD55,56,57,ACMD*) */ -#define CCC_IO_MODE (1<<9) /* (9) I/O mode */ +#define CCC_IO_MODE BIT(9) /* (9) I/O mode */ /* (CMD5,39,40,52,53) */ -#define CCC_SWITCH (1<<10) /* (10) High speed switch */ +#define CCC_SWITCH BIT(10) /* (10) High speed switch */ /* (CMD6,34,35,36,37,50) */ /* (11) Reserved */ /* (CMD?) */ @@ -330,8 +330,8 @@ static inline bool mmc_ready_for_data(u32 status) * EXT_CSD field definitions */ -#define EXT_CSD_WR_REL_PARAM_EN (1<<2) -#define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1<<4) +#define EXT_CSD_WR_REL_PARAM_EN BIT(2) +#define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR BIT(4) #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) @@ -346,30 +346,30 @@ static inline bool mmc_ready_for_data(u32 status) #define EXT_CSD_PART_SETTING_COMPLETED (0x1) #define EXT_CSD_PART_SUPPORT_PART_EN (0x1) -#define EXT_CSD_CMD_SET_NORMAL (1<<0) -#define EXT_CSD_CMD_SET_SECURE (1<<1) -#define EXT_CSD_CMD_SET_CPSECURE (1<<2) +#define EXT_CSD_CMD_SET_NORMAL BIT(0) +#define EXT_CSD_CMD_SET_SECURE BIT(1) +#define EXT_CSD_CMD_SET_CPSECURE BIT(2) -#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */ -#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_HS_26 BIT(0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_HS_52 BIT(1) /* Card can run at 52MHz */ #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \ EXT_CSD_CARD_TYPE_HS_52) -#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V BIT(2) /* Card can run at 52MHz */ /* DDR mode @1.8V or 3V I/O */ -#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_DDR_1_2V BIT(3) /* Card can run at 52MHz */ /* DDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | EXT_CSD_CARD_TYPE_DDR_1_2V) -#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */ -#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ /* SDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ EXT_CSD_CARD_TYPE_HS200_1_2V) -#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */ -#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ +#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) /* Card can run at 200MHz DDR, 1.8V */ +#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) /* Card can run at 200MHz DDR, 1.2V */ #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ EXT_CSD_CARD_TYPE_HS400_1_2V) -#define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */ +#define EXT_CSD_CARD_TYPE_HS400ES BIT(8) /* Card can run at HS400ES */ #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ @@ -453,6 +453,6 @@ static inline bool mmc_ready_for_data(u32 status) #define MMC_SECURE_ARGS 0x80000000 #define MMC_TRIM_OR_DISCARD_ARGS 0x00008003 -#define mmc_driver_type_mask(n) (1 << (n)) +#define mmc_driver_type_mask(n) BIT(n) #endif /* LINUX_MMC_MMC_H */ From patchwork Tue Jun 20 10:47:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DED5EB64D8 for ; Tue, 20 Jun 2023 10:47:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232278AbjFTKrs (ORCPT ); Tue, 20 Jun 2023 06:47:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231191AbjFTKrq (ORCPT ); Tue, 20 Jun 2023 06:47:46 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15786E3 for ; Tue, 20 Jun 2023 03:47:45 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 7E1028621C; Tue, 20 Jun 2023 12:47:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258063; bh=O1B5W8YRKbL28jB5zXlP6jQZRRvE9HyDOB/sGe8V4CY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QD+KZyJxLedJMxodMp1e+DHHNs+H/qEJn+cyQDhAwWWw40UW6slyt9z3APMMl+Wt3 z28y6yruaXtG0jP5Uzgrru3GZeDtVehci33AK4DFQwbFHlBlNLhImZfCRAyjg4NJ8m UT8L0MfCK6zyH8HHcr0HXtTkFln6mM7LgIopEzBPdBnaW0kRJPLbq5y9z17j19iU4U fji+LJ09Fojk/J0ODdHtHjGroq9mYmkAJYVHYyBwJHZrqffFdIf+La9ohvHKVytLN6 j+07yVQUFNQYDKAfwmABAOZO7vDZ1xcTiDJ1pqbaeiuUA9+N5SVcXptlCDG3X+Hid+ jFx0gGu8aQzuA== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 05/11] mmc: sd: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:16 +0200 Message-Id: <20230620104722.16465-5-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- include/linux/mmc/sd.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/mmc/sd.h b/include/linux/mmc/sd.h index 6727576a87555..6cf44c337e832 100644 --- a/include/linux/mmc/sd.h +++ b/include/linux/mmc/sd.h @@ -34,10 +34,10 @@ #define SD_WRITE_EXTR_SINGLE 49 /* adtc [31:0] R1 */ /* OCR bit definitions */ -#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */ +#define SD_OCR_S18R BIT(24) /* 1.8V switching request */ #define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */ -#define SD_OCR_XPC (1 << 28) /* SDXC power control */ -#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */ +#define SD_OCR_XPC BIT(28) /* SDXC power control */ +#define SD_OCR_CCS BIT(30) /* Card Capacity Status */ /* * SD_SWITCH argument format: From patchwork Tue Jun 20 10:47:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4120EB64DB for ; Tue, 20 Jun 2023 10:47:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231191AbjFTKrv (ORCPT ); Tue, 20 Jun 2023 06:47:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232292AbjFTKrq (ORCPT ); Tue, 20 Jun 2023 06:47:46 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F3081A7 for ; Tue, 20 Jun 2023 03:47:45 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 1CED486341; Tue, 20 Jun 2023 12:47:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258063; bh=11XhSg/rtQyxOo5HjQ0ol7zrrG68C5e/Ya70YCnybPs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WBi8XfVssuwc3iFUgrgHXaZkyVjKpGkPb7bGqOLUb2tvlwFhjJomp6WD5vTOas25y ceCp90NfVL8uzsoPlDfOFnBUv/VDoH6TgBaXTvENbIPDbOAfSsu8rDZjSw5GQIXya1 CyxWSAlXmcYUVG40+TniiB2NRSlzUaDEGdL+M/ImSgWIlNJCP5r04a/KyTa3mcEoKO opZGj9KoYFK5R7gyyYV1JIv+g4+EvogpjanmaevWxc2ptea2x8HbJ5oAVKDWDj4CKS POrkkSJ1FE/1KlT1JmbFwBGqej6A9iL6PI+6rGsGeaCvoR885WpibHqhoeaCf/Wt5u iqGi/a8FGMz+A== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 06/11] mmc: sdio: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:17 +0200 Message-Id: <20230620104722.16465-6-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- include/linux/mmc/sdio.h | 24 ++++++++++++------------ include/linux/mmc/sdio_func.h | 2 +- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/include/linux/mmc/sdio.h b/include/linux/mmc/sdio.h index 1ef400f28642e..e43806e9dd138 100644 --- a/include/linux/mmc/sdio.h +++ b/include/linux/mmc/sdio.h @@ -34,8 +34,8 @@ * [8:0] Byte/block count */ -#define R4_18V_PRESENT (1<<24) -#define R4_MEMORY_PRESENT (1 << 27) +#define R4_18V_PRESENT BIT(24) +#define R4_MEMORY_PRESENT BIT(27) /* SDIO status in R5 @@ -52,11 +52,11 @@ c : clear by read */ -#define R5_COM_CRC_ERROR (1 << 15) /* er, b */ -#define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */ -#define R5_ERROR (1 << 11) /* erx, c */ -#define R5_FUNCTION_NUMBER (1 << 9) /* er, c */ -#define R5_OUT_OF_RANGE (1 << 8) /* er, c */ +#define R5_COM_CRC_ERROR BIT(15) /* er, b */ +#define R5_ILLEGAL_COMMAND BIT(14) /* er, b */ +#define R5_ERROR BIT(11) /* erx, c */ +#define R5_FUNCTION_NUMBER BIT(9) /* er, c */ +#define R5_OUT_OF_RANGE BIT(8) /* er, c */ #define R5_STATUS(x) (x & 0xCB00) #define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */ @@ -150,9 +150,9 @@ #define SDIO_CCCR_DRIVE_STRENGTH 0x15 #define SDIO_SDTx_MASK 0x07 -#define SDIO_DRIVE_SDTA (1<<0) -#define SDIO_DRIVE_SDTC (1<<1) -#define SDIO_DRIVE_SDTD (1<<2) +#define SDIO_DRIVE_SDTA BIT(0) +#define SDIO_DRIVE_SDTC BIT(1) +#define SDIO_DRIVE_SDTD BIT(2) #define SDIO_DRIVE_DTSx_MASK 0x03 #define SDIO_DRIVE_DTSx_SHIFT 4 #define SDIO_DTSx_SET_TYPE_B (0 << SDIO_DRIVE_DTSx_SHIFT) @@ -161,8 +161,8 @@ #define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT) #define SDIO_CCCR_INTERRUPT_EXT 0x16 -#define SDIO_INTERRUPT_EXT_SAI (1 << 0) -#define SDIO_INTERRUPT_EXT_EAI (1 << 1) +#define SDIO_INTERRUPT_EXT_SAI BIT(0) +#define SDIO_INTERRUPT_EXT_EAI BIT(1) /* * Function Basic Registers (FBR) diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h index 478855b8e406f..ce8ffddd5bd3b 100644 --- a/include/linux/mmc/sdio_func.h +++ b/include/linux/mmc/sdio_func.h @@ -47,7 +47,7 @@ struct sdio_func { unsigned enable_timeout; /* max enable timeout in msec */ unsigned int state; /* function state */ -#define SDIO_STATE_PRESENT (1<<0) /* present in sysfs */ +#define SDIO_STATE_PRESENT BIT(0) /* present in sysfs */ u8 *tmpbuf; /* DMA:able scratch buffer */ From patchwork Tue Jun 20 10:47:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81883EB64DD for ; Tue, 20 Jun 2023 10:47:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232276AbjFTKrw (ORCPT ); Tue, 20 Jun 2023 06:47:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232289AbjFTKrr (ORCPT ); Tue, 20 Jun 2023 06:47:47 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA1A1E72 for ; Tue, 20 Jun 2023 03:47:45 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id B56D886346; Tue, 20 Jun 2023 12:47:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258064; bh=CScvQWUtkhOT9THcU2nJyb9WlpQlI0dStzbXsk/unfc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HuHpPvj/2eUEQ9eY2iIMfOFtNz7XVgiw4YQ++HXE4lKdeE3Nm/q/C/Czc/RURWthi S31Q+waDw532p3dHCW7iDxSwnjHJjwWHg4AH/B4y0kF1zgQM7Evw98qqf4MqehTBNI R6g5v97YtG+xwfQK3PNlTDJM+yfnc1ayeoWtdMeBHgiFyJHtFbN1AjPwHjL1/mNVKF UV75sP98GSXHVTAtNoAhCKZ0Kt/AhdTP//ZFgdFvetJ+G5/PMONoJYCmjC7rgoydvj 4E+2Lj3Lw0iVsHubfeyZweUnu2bsnFFiMqAGxgmMxjDdBDqhCPYZPIJbSkliwZvks4 aL6J+8H4DghlQ== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 07/11] mmc: mmci: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:18 +0200 Message-Id: <20230620104722.16465-7-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- drivers/mmc/host/mmci.h | 170 ++++++++++++++++++++-------------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index e1a9b96a3396f..d34e6020548c3 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -8,18 +8,18 @@ #define MCI_PWR_OFF 0x00 #define MCI_PWR_UP 0x02 #define MCI_PWR_ON 0x03 -#define MCI_OD (1 << 6) -#define MCI_ROD (1 << 7) +#define MCI_OD BIT(6) +#define MCI_ROD BIT(7) /* * The ST Micro version does not have ROD and reuse the voltage registers for * direction settings. */ -#define MCI_ST_DATA2DIREN (1 << 2) -#define MCI_ST_CMDDIREN (1 << 3) -#define MCI_ST_DATA0DIREN (1 << 4) -#define MCI_ST_DATA31DIREN (1 << 5) -#define MCI_ST_FBCLKEN (1 << 7) -#define MCI_ST_DATA74DIREN (1 << 8) +#define MCI_ST_DATA2DIREN BIT(2) +#define MCI_ST_CMDDIREN BIT(3) +#define MCI_ST_DATA0DIREN BIT(4) +#define MCI_ST_DATA31DIREN BIT(5) +#define MCI_ST_FBCLKEN BIT(7) +#define MCI_ST_DATA74DIREN BIT(8) /* * The STM32 sdmmc does not have PWR_UP/OD/ROD * and uses the power register for @@ -30,21 +30,21 @@ #define MCI_STM32_DIRPOL BIT(4) #define MMCICLOCK 0x004 -#define MCI_CLK_ENABLE (1 << 8) -#define MCI_CLK_PWRSAVE (1 << 9) -#define MCI_CLK_BYPASS (1 << 10) -#define MCI_4BIT_BUS (1 << 11) +#define MCI_CLK_ENABLE BIT(8) +#define MCI_CLK_PWRSAVE BIT(9) +#define MCI_CLK_BYPASS BIT(10) +#define MCI_4BIT_BUS BIT(11) /* * 8bit wide buses, hardware flow contronl, negative edges and clock inversion * supported in ST Micro U300 and Ux500 versions */ -#define MCI_ST_8BIT_BUS (1 << 12) -#define MCI_ST_U300_HWFCEN (1 << 13) -#define MCI_ST_UX500_NEG_EDGE (1 << 13) -#define MCI_ST_UX500_HWFCEN (1 << 14) -#define MCI_ST_UX500_CLK_INV (1 << 15) +#define MCI_ST_8BIT_BUS BIT(12) +#define MCI_ST_U300_HWFCEN BIT(13) +#define MCI_ST_UX500_NEG_EDGE BIT(13) +#define MCI_ST_UX500_HWFCEN BIT(14) +#define MCI_ST_UX500_CLK_INV BIT(15) /* Modified PL180 on Versatile Express platform */ -#define MCI_ARM_HWFCEN (1 << 12) +#define MCI_ARM_HWFCEN BIT(12) /* Modified on Qualcomm Integrations */ #define MCI_QCOM_CLK_WIDEBUS_8 (BIT(10) | BIT(11)) @@ -65,7 +65,7 @@ #define MCI_STM32_CLK_BUSSPEED BIT(19) #define MCI_STM32_CLK_SEL_MSK GENMASK(21, 20) #define MCI_STM32_CLK_SELCK (0 << 20) -#define MCI_STM32_CLK_SELCKIN (1 << 20) +#define MCI_STM32_CLK_SELCKIN BIT(20) #define MCI_STM32_CLK_SELFBCK (2 << 20) #define MMCIARGUMENT 0x008 @@ -95,7 +95,7 @@ #define MCI_CPSM_STM32_CMDSTOP BIT(7) #define MCI_CPSM_STM32_WAITRESP_MASK GENMASK(9, 8) #define MCI_CPSM_STM32_NORSP (0 << 8) -#define MCI_CPSM_STM32_SRSP_CRC (1 << 8) +#define MCI_CPSM_STM32_SRSP_CRC BIT(8) #define MCI_CPSM_STM32_SRSP (2 << 8) #define MCI_CPSM_STM32_LRSP_CRC (3 << 8) #define MCI_CPSM_STM32_ENABLE BIT(12) @@ -130,90 +130,90 @@ #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) /* Control register extensions in STM32 versions */ #define MCI_DPSM_STM32_MODE_BLOCK (0 << 2) -#define MCI_DPSM_STM32_MODE_SDIO (1 << 2) +#define MCI_DPSM_STM32_MODE_SDIO BIT(2) #define MCI_DPSM_STM32_MODE_STREAM (2 << 2) #define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2) #define MMCIDATACNT 0x030 #define MMCISTATUS 0x034 -#define MCI_CMDCRCFAIL (1 << 0) -#define MCI_DATACRCFAIL (1 << 1) -#define MCI_CMDTIMEOUT (1 << 2) -#define MCI_DATATIMEOUT (1 << 3) -#define MCI_TXUNDERRUN (1 << 4) -#define MCI_RXOVERRUN (1 << 5) -#define MCI_CMDRESPEND (1 << 6) -#define MCI_CMDSENT (1 << 7) -#define MCI_DATAEND (1 << 8) -#define MCI_STARTBITERR (1 << 9) -#define MCI_DATABLOCKEND (1 << 10) -#define MCI_CMDACTIVE (1 << 11) -#define MCI_TXACTIVE (1 << 12) -#define MCI_RXACTIVE (1 << 13) -#define MCI_TXFIFOHALFEMPTY (1 << 14) -#define MCI_RXFIFOHALFFULL (1 << 15) -#define MCI_TXFIFOFULL (1 << 16) -#define MCI_RXFIFOFULL (1 << 17) -#define MCI_TXFIFOEMPTY (1 << 18) -#define MCI_RXFIFOEMPTY (1 << 19) -#define MCI_TXDATAAVLBL (1 << 20) -#define MCI_RXDATAAVLBL (1 << 21) +#define MCI_CMDCRCFAIL BIT(0) +#define MCI_DATACRCFAIL BIT(1) +#define MCI_CMDTIMEOUT BIT(2) +#define MCI_DATATIMEOUT BIT(3) +#define MCI_TXUNDERRUN BIT(4) +#define MCI_RXOVERRUN BIT(5) +#define MCI_CMDRESPEND BIT(6) +#define MCI_CMDSENT BIT(7) +#define MCI_DATAEND BIT(8) +#define MCI_STARTBITERR BIT(9) +#define MCI_DATABLOCKEND BIT(10) +#define MCI_CMDACTIVE BIT(11) +#define MCI_TXACTIVE BIT(12) +#define MCI_RXACTIVE BIT(13) +#define MCI_TXFIFOHALFEMPTY BIT(14) +#define MCI_RXFIFOHALFFULL BIT(15) +#define MCI_TXFIFOFULL BIT(16) +#define MCI_RXFIFOFULL BIT(17) +#define MCI_TXFIFOEMPTY BIT(18) +#define MCI_RXFIFOEMPTY BIT(19) +#define MCI_TXDATAAVLBL BIT(20) +#define MCI_RXDATAAVLBL BIT(21) /* Extended status bits for the ST Micro variants */ -#define MCI_ST_SDIOIT (1 << 22) -#define MCI_ST_CEATAEND (1 << 23) -#define MCI_ST_CARDBUSY (1 << 24) +#define MCI_ST_SDIOIT BIT(22) +#define MCI_ST_CEATAEND BIT(23) +#define MCI_ST_CARDBUSY BIT(24) /* Extended status bits for the STM32 variants */ #define MCI_STM32_BUSYD0 BIT(20) #define MCI_STM32_BUSYD0END BIT(21) #define MCI_STM32_VSWEND BIT(25) #define MMCICLEAR 0x038 -#define MCI_CMDCRCFAILCLR (1 << 0) -#define MCI_DATACRCFAILCLR (1 << 1) -#define MCI_CMDTIMEOUTCLR (1 << 2) -#define MCI_DATATIMEOUTCLR (1 << 3) -#define MCI_TXUNDERRUNCLR (1 << 4) -#define MCI_RXOVERRUNCLR (1 << 5) -#define MCI_CMDRESPENDCLR (1 << 6) -#define MCI_CMDSENTCLR (1 << 7) -#define MCI_DATAENDCLR (1 << 8) -#define MCI_STARTBITERRCLR (1 << 9) -#define MCI_DATABLOCKENDCLR (1 << 10) +#define MCI_CMDCRCFAILCLR BIT(0) +#define MCI_DATACRCFAILCLR BIT(1) +#define MCI_CMDTIMEOUTCLR BIT(2) +#define MCI_DATATIMEOUTCLR BIT(3) +#define MCI_TXUNDERRUNCLR BIT(4) +#define MCI_RXOVERRUNCLR BIT(5) +#define MCI_CMDRESPENDCLR BIT(6) +#define MCI_CMDSENTCLR BIT(7) +#define MCI_DATAENDCLR BIT(8) +#define MCI_STARTBITERRCLR BIT(9) +#define MCI_DATABLOCKENDCLR BIT(10) /* Extended status bits for the ST Micro variants */ -#define MCI_ST_SDIOITC (1 << 22) -#define MCI_ST_CEATAENDC (1 << 23) -#define MCI_ST_BUSYENDC (1 << 24) +#define MCI_ST_SDIOITC BIT(22) +#define MCI_ST_CEATAENDC BIT(23) +#define MCI_ST_BUSYENDC BIT(24) /* Extended clear bits for the STM32 variants */ #define MCI_STM32_VSWENDC BIT(25) #define MCI_STM32_CKSTOPC BIT(26) #define MMCIMASK0 0x03c -#define MCI_CMDCRCFAILMASK (1 << 0) -#define MCI_DATACRCFAILMASK (1 << 1) -#define MCI_CMDTIMEOUTMASK (1 << 2) -#define MCI_DATATIMEOUTMASK (1 << 3) -#define MCI_TXUNDERRUNMASK (1 << 4) -#define MCI_RXOVERRUNMASK (1 << 5) -#define MCI_CMDRESPENDMASK (1 << 6) -#define MCI_CMDSENTMASK (1 << 7) -#define MCI_DATAENDMASK (1 << 8) -#define MCI_STARTBITERRMASK (1 << 9) -#define MCI_DATABLOCKENDMASK (1 << 10) -#define MCI_CMDACTIVEMASK (1 << 11) -#define MCI_TXACTIVEMASK (1 << 12) -#define MCI_RXACTIVEMASK (1 << 13) -#define MCI_TXFIFOHALFEMPTYMASK (1 << 14) -#define MCI_RXFIFOHALFFULLMASK (1 << 15) -#define MCI_TXFIFOFULLMASK (1 << 16) -#define MCI_RXFIFOFULLMASK (1 << 17) -#define MCI_TXFIFOEMPTYMASK (1 << 18) -#define MCI_RXFIFOEMPTYMASK (1 << 19) -#define MCI_TXDATAAVLBLMASK (1 << 20) -#define MCI_RXDATAAVLBLMASK (1 << 21) +#define MCI_CMDCRCFAILMASK BIT(0) +#define MCI_DATACRCFAILMASK BIT(1) +#define MCI_CMDTIMEOUTMASK BIT(2) +#define MCI_DATATIMEOUTMASK BIT(3) +#define MCI_TXUNDERRUNMASK BIT(4) +#define MCI_RXOVERRUNMASK BIT(5) +#define MCI_CMDRESPENDMASK BIT(6) +#define MCI_CMDSENTMASK BIT(7) +#define MCI_DATAENDMASK BIT(8) +#define MCI_STARTBITERRMASK BIT(9) +#define MCI_DATABLOCKENDMASK BIT(10) +#define MCI_CMDACTIVEMASK BIT(11) +#define MCI_TXACTIVEMASK BIT(12) +#define MCI_RXACTIVEMASK BIT(13) +#define MCI_TXFIFOHALFEMPTYMASK BIT(14) +#define MCI_RXFIFOHALFFULLMASK BIT(15) +#define MCI_TXFIFOFULLMASK BIT(16) +#define MCI_RXFIFOFULLMASK BIT(17) +#define MCI_TXFIFOEMPTYMASK BIT(18) +#define MCI_RXFIFOEMPTYMASK BIT(19) +#define MCI_TXDATAAVLBLMASK BIT(20) +#define MCI_RXDATAAVLBLMASK BIT(21) /* Extended status bits for the ST Micro variants */ -#define MCI_ST_SDIOITMASK (1 << 22) -#define MCI_ST_CEATAENDMASK (1 << 23) -#define MCI_ST_BUSYENDMASK (1 << 24) +#define MCI_ST_SDIOITMASK BIT(22) +#define MCI_ST_CEATAENDMASK BIT(23) +#define MCI_ST_BUSYENDMASK BIT(24) /* Extended status bits for the STM32 variants */ #define MCI_STM32_BUSYD0ENDMASK BIT(21) From patchwork Tue Jun 20 10:47:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D90E2EB64DC for ; Tue, 20 Jun 2023 10:47:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232289AbjFTKrx (ORCPT ); Tue, 20 Jun 2023 06:47:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232295AbjFTKrr (ORCPT ); Tue, 20 Jun 2023 06:47:47 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AB091A5 for ; Tue, 20 Jun 2023 03:47:46 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 781CC8634C; Tue, 20 Jun 2023 12:47:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258064; bh=bHiG/wByeL7J08YAL18goM+iHMaAtIDWsEG+k+ffIT0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Sgle1zu5M75/40KhCfyKggoAsghKQ75Jlyr9u5TQ7uB0jazCOfPjCPAFgxsjYCakF s4/7eOO0QLFcDMRTT5oDmoS4iJmzkY2B+QKWPpVViI2VJJx8QGLxBHGWufYooRusif AWf05oqgkBWB+jFqc1LQise+bBzUdc9oRzfaKcKI7xCYcxTNU15taG+WSA58R9Zgz3 /I4TQbA3xeNyp2KHdtQR0O3Aoymn+fJA3VFTjY/RNoE63eblixR2FZW8Uq2ockePpH nCRe2nefR8gchfugKaP+nNZrJQHuoy5J225hYRW1DOmipdvSl5ckwsLjzvT5Uv7J5O iNmeCkA39pH2Q== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 08/11] mmc: pxav3: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:19 +0200 Message-Id: <20230620104722.16465-8-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- drivers/mmc/host/sdhci-pxav3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index e39dcc998772d..12c342a231dfc 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -35,7 +35,7 @@ #define SDCLK_DELAY_MASK 0x1f #define SD_CFG_FIFO_PARAM 0x100 -#define SDCFG_GEN_PAD_CLK_ON (1<<6) +#define SDCFG_GEN_PAD_CLK_ON BIT(6) #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 @@ -43,8 +43,8 @@ #define SD_CE_ATA_1 0x10C #define SD_CE_ATA_2 0x10E -#define SDCE_MISC_INT (1<<2) -#define SDCE_MISC_INT_EN (1<<1) +#define SDCE_MISC_INT BIT(2) +#define SDCE_MISC_INT_EN BIT(1) struct sdhci_pxa { struct clk *clk_core; From patchwork Tue Jun 20 10:47:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57BD4C0015E for ; Tue, 20 Jun 2023 10:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231246AbjFTKr4 (ORCPT ); Tue, 20 Jun 2023 06:47:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232283AbjFTKrs (ORCPT ); Tue, 20 Jun 2023 06:47:48 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1C808F for ; Tue, 20 Jun 2023 03:47:46 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 13ACB86351; Tue, 20 Jun 2023 12:47:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258065; bh=I28rLw3TRO4a0p5HTA64AoGki+TRUpTaASYkwxYYktM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RdN65J1PiQj/ZxMg6DaG2S62fX963lujan34Nk0cQdXdrCwm7isJrsDm8iZwYW2ir HvpGNI5NRyg/vpvUzrZ271sUZKjk5XqCrggNLCN/PCVYL330QbAWdt6ZCMtM6w1mCp OGUREUOMLVJ6PTS1P5rF2yc05F0cZrmnCcA4U5GLdN88YprRcogL06xpvINn9K9o6Q DX6LKq+b2H4IafRsfrIxG+BH7xUtvVUDfNDjfVojckdnYoNYQ4Sbue5LhX25pvZ413 SSudb3BVhEP3SCEez800INsF48IRRAnr13R5ZHJTyDrdzeWpsuJYRWN+bGm3L00RSe ksT1t8+P1+zfQ== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 09/11] mmc: sdhci: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:20 +0200 Message-Id: <20230620104722.16465-9-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- drivers/mmc/host/sdhci.h | 126 +++++++++++++++++++-------------------- 1 file changed, 63 insertions(+), 63 deletions(-) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f219bdea8f280..05bdd5ef958a1 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -379,112 +379,112 @@ struct sdhci_host { unsigned int quirks; /* Deviations from spec. */ /* Controller doesn't honor resets unless we touch the clock register */ -#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) +#define SDHCI_QUIRK_CLOCK_BEFORE_RESET BIT(0) /* Controller has bad caps bits, but really supports DMA */ -#define SDHCI_QUIRK_FORCE_DMA (1<<1) +#define SDHCI_QUIRK_FORCE_DMA BIT(1) /* Controller doesn't like to be reset when there is no card inserted. */ -#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) +#define SDHCI_QUIRK_NO_CARD_NO_RESET BIT(2) /* Controller doesn't like clearing the power reg before a change */ -#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) +#define SDHCI_QUIRK_SINGLE_POWER_WRITE BIT(3) /* Controller has an unusable DMA engine */ -#define SDHCI_QUIRK_BROKEN_DMA (1<<5) +#define SDHCI_QUIRK_BROKEN_DMA BIT(5) /* Controller has an unusable ADMA engine */ -#define SDHCI_QUIRK_BROKEN_ADMA (1<<6) +#define SDHCI_QUIRK_BROKEN_ADMA BIT(6) /* Controller can only DMA from 32-bit aligned addresses */ -#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) +#define SDHCI_QUIRK_32BIT_DMA_ADDR BIT(7) /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ -#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) +#define SDHCI_QUIRK_32BIT_DMA_SIZE BIT(8) /* Controller can only ADMA chunks that are a multiple of 32 bits */ -#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) +#define SDHCI_QUIRK_32BIT_ADMA_SIZE BIT(9) /* Controller needs to be reset after each request to stay stable */ -#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) +#define SDHCI_QUIRK_RESET_AFTER_REQUEST BIT(10) /* Controller needs voltage and power writes to happen separately */ -#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) +#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER BIT(11) /* Controller provides an incorrect timeout value for transfers */ -#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) +#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL BIT(12) /* Controller has an issue with buffer bits for small transfers */ -#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) +#define SDHCI_QUIRK_BROKEN_SMALL_PIO BIT(13) /* Controller does not provide transfer-complete interrupt when not busy */ -#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) +#define SDHCI_QUIRK_NO_BUSY_IRQ BIT(14) /* Controller has unreliable card detection */ -#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) +#define SDHCI_QUIRK_BROKEN_CARD_DETECTION BIT(15) /* Controller reports inverted write-protect state */ -#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) +#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT BIT(16) /* Controller has unusable command queue engine */ -#define SDHCI_QUIRK_BROKEN_CQE (1<<17) +#define SDHCI_QUIRK_BROKEN_CQE BIT(17) /* Controller does not like fast PIO transfers */ -#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) +#define SDHCI_QUIRK_PIO_NEEDS_DELAY BIT(18) /* Controller does not have a LED */ -#define SDHCI_QUIRK_NO_LED (1<<19) +#define SDHCI_QUIRK_NO_LED BIT(19) /* Controller has to be forced to use block size of 2048 bytes */ -#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) +#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 BIT(20) /* Controller cannot do multi-block transfers */ -#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) +#define SDHCI_QUIRK_NO_MULTIBLOCK BIT(21) /* Controller can only handle 1-bit data transfers */ -#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) +#define SDHCI_QUIRK_FORCE_1_BIT_DATA BIT(22) /* Controller needs 10ms delay between applying power and clock */ -#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) +#define SDHCI_QUIRK_DELAY_AFTER_POWER BIT(23) /* Controller uses SDCLK instead of TMCLK for data timeouts */ -#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) +#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK BIT(24) /* Controller reports wrong base clock capability */ -#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) +#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN BIT(25) /* Controller cannot support End Attribute in NOP ADMA descriptor */ -#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) +#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC BIT(26) /* Controller uses Auto CMD12 command to stop the transfer */ -#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) +#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 BIT(28) /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ -#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) +#define SDHCI_QUIRK_NO_HISPD_BIT BIT(29) /* Controller treats ADMA descriptors with length 0000h incorrectly */ -#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) +#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC BIT(30) /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ -#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) +#define SDHCI_QUIRK_UNSTABLE_RO_DETECT BIT(31) unsigned int quirks2; /* More deviations from spec. */ -#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) -#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) +#define SDHCI_QUIRK2_HOST_OFF_CARD_ON BIT(0) +#define SDHCI_QUIRK2_HOST_NO_CMD23 BIT(1) /* The system physically doesn't support 1.8v, even if the host does */ -#define SDHCI_QUIRK2_NO_1_8_V (1<<2) -#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) -#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) +#define SDHCI_QUIRK2_NO_1_8_V BIT(2) +#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN BIT(3) +#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON BIT(4) /* Controller has a non-standard host control register */ -#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) +#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL BIT(5) /* Controller does not support HS200 */ -#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) +#define SDHCI_QUIRK2_BROKEN_HS200 BIT(6) /* Controller does not support DDR50 */ -#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) +#define SDHCI_QUIRK2_BROKEN_DDR50 BIT(7) /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ -#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) +#define SDHCI_QUIRK2_STOP_WITH_TC BIT(8) /* Controller does not support 64-bit DMA */ -#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) +#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA BIT(9) /* need clear transfer mode register before send cmd */ -#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) +#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD BIT(10) /* Capability register bit-63 indicates HS400 support */ -#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) +#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 BIT(11) /* forced tuned clock */ -#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) +#define SDHCI_QUIRK2_TUNING_WORK_AROUND BIT(12) /* disable the block count for single block transactions */ -#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) +#define SDHCI_QUIRK2_SUPPORT_SINGLE BIT(13) /* Controller broken with using ACMD23 */ -#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) +#define SDHCI_QUIRK2_ACMD23_BROKEN BIT(14) /* Broken Clock divider zero in controller */ -#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) +#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN BIT(15) /* Controller has CRC in 136 bit Command Response */ -#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) +#define SDHCI_QUIRK2_RSP_136_HAS_CRC BIT(16) /* * Disable HW timeout if the requested timeout is more than the maximum * obtainable timeout. */ -#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) +#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT BIT(17) /* * 32-bit block count may not support eMMC where upper bits of CMD23 are used * for other purposes. Consequently we support 16-bit block count by default. * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit * block count. */ -#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT BIT(18) /* Issue CMD and DATA reset together */ -#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) +#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER BIT(19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ @@ -508,19 +508,19 @@ struct sdhci_host { spinlock_t lock; /* Mutex */ int flags; /* Host attributes */ -#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ -#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ -#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ -#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ -#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ -#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ -#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ -#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ -#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ -#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ -#define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ -#define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ -#define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ +#define SDHCI_USE_SDMA BIT(0) /* Host is SDMA capable */ +#define SDHCI_USE_ADMA BIT(1) /* Host is ADMA capable */ +#define SDHCI_REQ_USE_DMA BIT(2) /* Use DMA for this req. */ +#define SDHCI_DEVICE_DEAD BIT(3) /* Device unresponsive */ +#define SDHCI_SDR50_NEEDS_TUNING BIT(4) /* SDR50 needs tuning */ +#define SDHCI_AUTO_CMD12 BIT(6) /* Auto CMD12 support */ +#define SDHCI_AUTO_CMD23 BIT(7) /* Auto CMD23 support */ +#define SDHCI_PV_ENABLED BIT(8) /* Preset value enabled */ +#define SDHCI_USE_64_BIT_DMA BIT(12) /* Use 64-bit DMA */ +#define SDHCI_HS400_TUNING BIT(13) /* Tuning for HS400 */ +#define SDHCI_SIGNALING_330 BIT(14) /* Host is capable of 3.3V signaling */ +#define SDHCI_SIGNALING_180 BIT(15) /* Host is capable of 1.8V signaling */ +#define SDHCI_SIGNALING_120 BIT(16) /* Host is capable of 1.2V signaling */ unsigned int version; /* SDHCI spec. version */ From patchwork Tue Jun 20 10:47:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13285609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BACF8EB64D8 for ; Tue, 20 Jun 2023 10:47:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232292AbjFTKry (ORCPT ); Tue, 20 Jun 2023 06:47:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232297AbjFTKrs (ORCPT ); Tue, 20 Jun 2023 06:47:48 -0400 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DA94197 for ; Tue, 20 Jun 2023 03:47:47 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id A4CDE86354; Tue, 20 Jun 2023 12:47:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258066; bh=psHkjDcuH/noI1mwgUE/rgdIDb1uLlAZknH9j+hekS8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NgIEWLzldTAhanCHOawX2ApLBOqbzUVFPKVqVTFxbSbeK+5M5/RcC2mdEKBFDdlu/ YqItZturcuh26UKNcxf9cpwBwJATAWoRqWGcNaGWPpAcqC4qvtlrD1KBqnpNOSA1Gf AO2f//Mp0c9vhszA+2GzdYSr812ij5ppWgzwsd2epuf0LGgBecNuA/ulu6el/aehro AsSrPsc6Hg8fhnu8bFNuWDRJ1gxoW53Fso3VwLmI3RqrwZjpHbY76tJaE5EVH5Yrvt 1ddV/OQiTRvyOVP8umPKpO1eBEGUjsSud4vbQWXx6Zk2D93O/dglee67Q21di7GP3m oJbg/iSGtb9SA== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 10/11] mmc: vub300: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:21 +0200 Message-Id: <20230620104722.16465-10-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- drivers/mmc/host/vub300.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/vub300.c b/drivers/mmc/host/vub300.c index 9ec593d52f0fa..4216d57262dc3 100644 --- a/drivers/mmc/host/vub300.c +++ b/drivers/mmc/host/vub300.c @@ -323,7 +323,7 @@ struct vub300_mmc_host { struct sdio_register sdio_register[16]; struct offload_interrupt_function_register { #define MAXREGBITS 4 -#define MAXREGS (1< X-Patchwork-Id: 13285610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30C39EB64DB for ; Tue, 20 Jun 2023 10:47:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232295AbjFTKrz (ORCPT ); Tue, 20 Jun 2023 06:47:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232301AbjFTKrs (ORCPT ); Tue, 20 Jun 2023 06:47:48 -0400 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5335E3 for ; Tue, 20 Jun 2023 03:47:47 -0700 (PDT) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 374C686359; Tue, 20 Jun 2023 12:47:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1687258066; bh=ZnnWoa3Bd9N8jj4RihC5dDZX+ySbFdQgnGriPTF8ymA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sKIiZVkWQw/KXFR+ACl7FhnK+rlo94BDa32a0dEoGA8+WNxNTcL2bcDtsq8CLf0sP bwald+W9Fkl9vLJ+sDFAcnr2MUKZzlVfLIsE6K88N1Y+lGzQyFibPvA9TKYEpT4gIa 5t5+2tJ2jWvjKy/sCyY3vlJBFV+5T6Xt5mR0VT9WDOHBYoSA/JmKxxqRnRQUDp13fX YpatwLFkM+zMyvT1tmtS4vXznrikWNIas0OS3ZUw7asU6O91Nqz98D/J82pbmJcp2I gF6OwzvIe+W/ChtOGwadwLahE+SskWbZyzPZjEV2PCfeAP5FZlZYBr2lWFv1SxWhTu 9RBJr3Nhz2/oQ== From: Marek Vasut To: linux-mmc@vger.kernel.org Cc: Marek Vasut , Adrian Hunter , Avri Altman , Bo Liu , Deren Wu , Philipp Zabel , Pierre Ossman , Russell King , Ulf Hansson , Yang Yingliang Subject: [PATCH 11/11] mmc: wbsd: Use BIT() macro Date: Tue, 20 Jun 2023 12:47:22 +0200 Message-Id: <20230620104722.16465-11-marex@denx.de> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230620104722.16465-1-marex@denx.de> References: <20230620104722.16465-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use the BIT(n) macro instead of (1< --- Cc: Adrian Hunter Cc: Avri Altman Cc: Bo Liu Cc: Deren Wu Cc: Philipp Zabel Cc: Pierre Ossman Cc: Russell King Cc: Ulf Hansson Cc: Yang Yingliang Cc: linux-mmc@vger.kernel.org --- drivers/mmc/host/wbsd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/wbsd.h b/drivers/mmc/host/wbsd.h index be30b4d8ce4c7..e78258d00b868 100644 --- a/drivers/mmc/host/wbsd.h +++ b/drivers/mmc/host/wbsd.h @@ -141,8 +141,8 @@ struct wbsd_host int flags; /* Driver states */ -#define WBSD_FCARD_PRESENT (1<<0) /* Card is present */ -#define WBSD_FIGNORE_DETECT (1<<1) /* Ignore card detection */ +#define WBSD_FCARD_PRESENT BIT(0) /* Card is present */ +#define WBSD_FIGNORE_DETECT BIT(1) /* Ignore card detection */ struct mmc_request* mrq; /* Current request */