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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [PATCH v1] xen/arm: arm32: Add support to identify the Cortex-R52 processor Date: Tue, 20 Jun 2023 16:17:36 +0100 Message-ID: <20230620151736.3720850-1-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001507:EE_|CY8PR12MB8412:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b298864-e065-4a50-2218-08db71a182c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zMlt3Sfva4MlT8IB4LFZJnhHdANjbEqcsSIPELX8CvZfdhJYBexN9/kvFW6ksBOKxFq2xHGoLonji5fxq4xhoe7h+SOxHMCm4OQN1z/t0fBst0QaCrxxdB4KG6W/NSlXa8tOjC1QQM0lWUzsqHNb3OIy5CVcmKdOdUoZQT4ItgJdwb6rqcl7uWhdvVlr+/s/KrxDFyQZofRe7XYNKTCC1DTCPL+pTkjqIooKekh7gAGJSR51roliWuQXWPacZjj/79a4uTGEWPjMuxAxnVVAZ5G8J6jbc77fqHd/SrlRkcj0aUF9hrCDqaGnlxvKQRxJnWYpzOFETO3QBmPO2VHRL/lu8V/AgVBvMnwCm3c7bUCLMkSqp+NvIp5yLEhg4TdElzsvI+WNplMxNhu6ckW9cMc6/wl1PoqYY77P4MXR1q/NPj0UXaKC707NhMXm71f71AyB03Bhgy74uFNyXbsL1aEnjeqn9XWt4P5caHMWhzOgMNAzTwCzxGxX2bRewusRKhNrQCUP4Kx5mGh0pOZ7Sf3IH8rc8g7z3JYPhcSzs6xCkETnpUliAQZ0j0YQLYzJylL9e4iGWKNotQ+KVyqBNmKs6ne4JTsFu+8v3YZQlWv529kAxc6vz86Z0GeF3tfBVOCRH9M7vXUwbNQ0KrucnoVDCqrsWfI6JteD0ag0RR1nBi9sfqgKIWdnfAl6OC6BV4T0XKHPN+3vcSwhRG3F1sWS+B8zC9MFULC2m3uMokw1i3OQ1axad5Ajd+cWUSF19TS3cI4+SHnlj66Mr+3OMw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(39860400002)(396003)(376002)(451199021)(46966006)(36840700001)(40470700004)(1076003)(478600001)(5660300002)(6916009)(70586007)(70206006)(4326008)(2906002)(54906003)(41300700001)(316002)(6666004)(8676002)(8936002)(186003)(26005)(426003)(2616005)(336012)(36860700001)(47076005)(82740400003)(81166007)(356005)(82310400005)(36756003)(103116003)(40460700003)(86362001)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2023 15:17:50.0062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b298864-e065-4a50-2218-08db71a182c5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001507.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8412 Add a special configuration (CONFIG_AARCH32_V8R) to setup the Cortex-R52 specifics. Cortex-R52 is an Arm-V8R AArch32 processor. Refer ARM DDI 0487I.a ID081822, G8-9647, G8.2.112 MIDR, bits[31:24] = 0x41 , Arm Ltd bits[23:20] = Implementation defined bits[19:16] = 0xf , Arch features are individually identified bits[15:4] = Implementation defined bits[3:0] = Implementation defined Thus, the processor id is 0x410f0000 and the processor id mask is 0xff0f0000 Also, there is no special initialization required for R52. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/Kconfig | 7 +++++++ xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/proc-v8.S | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+) create mode 100644 xen/arch/arm/arm32/proc-v8.S diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 61e581b8c2..c45753a2dd 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -3,6 +3,13 @@ config ARM_32 depends on "$(ARCH)" = "arm32" select ARCH_MAP_DOMAIN_PAGE +config AARCH32_V8R + bool "AArch32 Arm V8R Support (UNSUPPORTED)" if UNSUPPORTED + def_bool n + depends on ARM_32 + help + This option enables Armv8-R profile for AArch32. + config ARM_64 def_bool y depends on !ARM_32 diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 520fb42054..2ab808a7a8 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -8,6 +8,7 @@ obj-y += head.o obj-y += insn.o obj-$(CONFIG_LIVEPATCH) += livepatch.o obj-y += proc-v7.o proc-caxx.o +obj-$(CONFIG_AARCH32_V8R) += proc-v8.o obj-y += smpboot.o obj-y += traps.o obj-y += vfp.o diff --git a/xen/arch/arm/arm32/proc-v8.S b/xen/arch/arm/arm32/proc-v8.S new file mode 100644 index 0000000000..c5a566b165 --- /dev/null +++ b/xen/arch/arm/arm32/proc-v8.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * xen/arch/arm/arm32/proc-v8.S + * + * AArch32 V8R specific initialization + * + * Copyright (C) 2023, Advanced Micro Devices, Inc. All Rights Reserved. + */ + +#include +#include + +cr52_init: + mov pc, lr + + .section ".proc.info", #alloc + .type __v8_cr52_proc_info, #object +__v8_cr52_proc_info: + .long 0x410F0000 /* Cortex-R52 */ + .long 0xFF0F0000 /* Mask */ + .long cr52_init + .size __v8_cr52_proc_info, . - __v8_cr52_proc_info + + .section ".proc.info", #alloc + .type __v8_cr52_proc_info, #object + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */