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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:11 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4c120d33-0f8e-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281432; x=1689873432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ukzGpEENG0RlgItA22pHLWRfkG/TIG2MuZvDy/EWEFU=; b=Ui3x4e2d1x7msUonmnEtV2oZD/YnB5TKiukjofsjZMyaIwsa94EELiqp60Boh7w1Pd liSVUEjzvbLj7tNmPLSnwXvkE984RpJyNnkXgYJZxhasBdPPGttj7ZGEV4y39soxZp9c N4ZfA42vod69hfNmN9IJ1UuqF00rTRL9LirV/KUu30KsvxUra2WpOikuQNaTy6FXa0jV nKpdECVzHl/hIa3mN1mFGSpHgP0PQFsMh30tOsQBMSO9WejSZNk1cKAFk3FzuDiNVIOd AaJ0V/WtfyIMRW0c+vwlTxx3oFUinCAo0Uwq+c2hlryeCvv7la++wJp5beXgaNJc1scy Jopw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281432; x=1689873432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ukzGpEENG0RlgItA22pHLWRfkG/TIG2MuZvDy/EWEFU=; b=KQiCI/HFAq1BTHOH2Jb157hnKkgSjfLMRpVl8Hludy2nCWRLkBxYdG8wQX4Enmc4kZ sJaWgionB+iqfo8hBR1OcYh9V95j0ushUrJz2sKD3sf3yTmV0/UW4M+nnHHSuXfFVZ7l jl6mqFtAHrdN+XmB3ysQ6LJbbiEtPxCqlSrXHsE0uRPhDSEyLygTkdDElRwD9hv3rUuT R11ajEFJsgdd5clerzerlIDfzIzyKtpBM4A6DeFhBRsLMjlPFqvgvKkoXOszNapkgRYb V4++5REnIorYVj38+HcvFEBJALNbmKh29VgfJb1caIoS4Enenditz0KqLKIBlK8q3RR3 jEDA== X-Gm-Message-State: AC+VfDwwPsMGEhj7GwmB2uNYvazuOucxwyqLyNmV8TWj75tsjzEukYS/ 7Q9//S7Klqg7rYkJIiQnoC+WMKlePjRr+g== X-Google-Smtp-Source: ACHHUZ7sEKIwUdOwq8v0ZiXEvcWcwlhyvF7IGBk2nsbUQnRGQM9cgKjioeDKihYNY1gaGXgxfzYrGQ== X-Received: by 2002:a25:b195:0:b0:b8e:cb88:1b69 with SMTP id h21-20020a25b195000000b00b8ecb881b69mr10005548ybj.34.1687281431908; Tue, 20 Jun 2023 10:17:11 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Jan Beulich , Wei Liu , Anthony PERARD Subject: [PATCH v2 01/12] libacpi: new DSDT ACPI table for Q35 Date: Tue, 20 Jun 2023 13:15:41 -0400 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 This patch adds the DSDT table for Q35 (new tools/libacpi/dsdt_q35.asl file). There are not many differences with dsdt.asl (for i440) at the moment, namely: - BDF location of LPC Controller - Minor changes related to FDC detection - Addition of _OSC method to inform OSPM about PCIe features supported As we are still using 4 PCI router links and their corresponding device/register addresses are same (offset 0x60), no need to change PCI routing descriptions. Also, ACPI hotplug is still used to control passed through device hot (un)plug (as it was for i440). Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/libacpi/dsdt_q35.asl | 578 +++++++++++++++++++++++++++++++++++++ 1 file changed, 578 insertions(+) create mode 100644 tools/libacpi/dsdt_q35.asl diff --git a/tools/libacpi/dsdt_q35.asl b/tools/libacpi/dsdt_q35.asl new file mode 100644 index 0000000000..1ec32a8010 --- /dev/null +++ b/tools/libacpi/dsdt_q35.asl @@ -0,0 +1,578 @@ +/****************************************************************************** + * DSDT for Xen with Qemu device model (for Q35 machine) + * + * Copyright (c) 2004, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 only. with the special + * exception on linking described in file LICENSE. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + */ + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "Xen", "HVM", 0) +{ + Name (\PMBS, 0x0C00) + Name (\PMLN, 0x08) + Name (\IOB1, 0x00) + Name (\IOL1, 0x00) + Name (\APCB, 0xFEC00000) + Name (\APCL, 0x00010000) + Name (\PUID, 0x00) + + + Scope (\_SB) + { + + /* Fix HCT test for 0x400 pci memory: + * - need to report low 640 MB mem as motherboard resource + */ + Device(MEM0) + { + Name(_HID, EISAID("PNP0C02")) + Name(_CRS, ResourceTemplate() { + QWordMemory( + ResourceConsumer, PosDecode, MinFixed, + MaxFixed, Cacheable, ReadWrite, + 0x00000000, + 0x00000000, + 0x0009ffff, + 0x00000000, + 0x000a0000) + }) + } + + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08")) + Name(_CID, EisaId("PNP0A03")) + Name (_UID, 0x00) + Name (_ADR, 0x00) + Name (_BBN, 0x00) + + /* _OSC, modified from ASL sample in ACPI spec */ + Name(SUPP, 0) /* PCI _OSC Support Field value */ + Name(CTRL, 0) /* PCI _OSC Control Field value */ + Method(_OSC, 4) { + /* Create DWORD-addressable fields from the Capabilities Buffer */ + CreateDWordField(Arg3, 0, CDW1) + + /* Switch by UUID. + * Only PCI Host Bridge Device capabilities UUID used for now + */ + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + /* Create DWORD-addressable fields from the Capabilities Buffer */ + CreateDWordField(Arg3, 4, CDW2) + CreateDWordField(Arg3, 8, CDW3) + + /* Save Capabilities DWORD2 & 3 */ + Store(CDW2, SUPP) + Store(CDW3, CTRL) + + /* Validate Revision DWORD */ + If (LNotEqual(Arg1, One)) { + /* Unknown revision */ + /* Support and Control DWORDs will be returned anyway */ + Or(CDW1, 0x08, CDW1) + } + + /* Control field bits are: + * bit 0 PCI Express Native Hot Plug control + * bit 1 SHPC Native Hot Plug control + * bit 2 PCI Express Native Power Management Events control + * bit 3 PCI Express Advanced Error Reporting control + * bit 4 PCI Express Capability Structure control + */ + + /* Always allow native PME, AER (no dependencies) + * Never allow SHPC (no SHPC controller in this system) + * Do not allow PCIe Capability Structure control for now + * Also, ACPI hotplug is used for now instead of PCIe + * Native Hot Plug + */ + And(CTRL, 0x0C, CTRL) + + If (LNotEqual(CDW3, CTRL)) { + /* Some of Capabilities bits were masked */ + Or(CDW1, 0x10, CDW1) + } + /* Update DWORD3 in the buffer */ + Store(CTRL, CDW3) + } Else { + Or(CDW1, 4, CDW1) /* Unrecognized UUID */ + } + Return (Arg3) + } + /* end of _OSC */ + + + /* Make cirrues VGA S3 suspend/resume work in Windows XP/2003 */ + Device (VGA) + { + Name (_ADR, 0x00020000) + + Method (_S1D, 0, NotSerialized) + { + Return (0x00) + } + Method (_S2D, 0, NotSerialized) + { + Return (0x00) + } + Method (_S3D, 0, NotSerialized) + { + Return (0x00) + } + } + + Method (_CRS, 0, NotSerialized) + { + Store (ResourceTemplate () + { + /* bus number is from 0 - 255*/ + WordBusNumber( + ResourceProducer, MinFixed, MaxFixed, SubDecode, + 0x0000, + 0x0000, + 0x00FF, + 0x0000, + 0x0100) + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) + WordIO( + ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, + 0x0000, + 0x0CF7, + 0x0000, + 0x0CF8) + WordIO( + ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, + 0x0D00, + 0xFFFF, + 0x0000, + 0xF300) + + /* reserve memory for pci devices */ + DWordMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, + WriteCombining, ReadWrite, + 0x00000000, + 0x000A0000, + 0x000BFFFF, + 0x00000000, + 0x00020000) + + DWordMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, + 0xF0000000, + 0xF4FFFFFF, + 0x00000000, + 0x05000000, + ,, _Y01) + + QWordMemory ( + ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x0000000000000000, + 0x0000000FFFFFFFF0, + 0x0000000FFFFFFFFF, + 0x0000000000000000, + 0x0000000000000010, + ,, _Y02) + + }, Local1) + + CreateDWordField(Local1, \_SB.PCI0._CRS._Y01._MIN, MMIN) + CreateDWordField(Local1, \_SB.PCI0._CRS._Y01._MAX, MMAX) + CreateDWordField(Local1, \_SB.PCI0._CRS._Y01._LEN, MLEN) + + Store(\_SB.PMIN, MMIN) + Store(\_SB.PLEN, MLEN) + Add(MMIN, MLEN, MMAX) + Subtract(MMAX, One, MMAX) + + /* + * WinXP / Win2K3 blue-screen for operations on 64-bit values. + * Therefore we need to split the 64-bit calculations needed + * here, but different iasl versions evaluate name references + * to integers differently: + * Year (approximate) 2006 2008 2012 + * \_SB.PCI0._CRS._Y02 zero valid valid + * \_SB.PCI0._CRS._Y02._MIN valid valid huge + */ + If(LEqual(Zero, \_SB.PCI0._CRS._Y02)) { + Subtract(\_SB.PCI0._CRS._Y02._MIN, 14, Local0) + } Else { + Store(\_SB.PCI0._CRS._Y02, Local0) + } + CreateDWordField(Local1, Add(Local0, 14), MINL) + CreateDWordField(Local1, Add(Local0, 18), MINH) + CreateDWordField(Local1, Add(Local0, 22), MAXL) + CreateDWordField(Local1, Add(Local0, 26), MAXH) + CreateDWordField(Local1, Add(Local0, 38), LENL) + CreateDWordField(Local1, Add(Local0, 42), LENH) + + Store(\_SB.LMIN, MINL) + Store(\_SB.HMIN, MINH) + Store(\_SB.LLEN, LENL) + Store(\_SB.HLEN, LENH) + Add(MINL, LENL, MAXL) + Add(MINH, LENH, MAXH) + If(LLess(MAXL, MINL)) { + Add(MAXH, One, MAXH) + } + If(LOr(MINH, LENL)) { + If(LEqual(MAXL, 0)) { + Subtract(MAXH, One, MAXH) + } + Subtract(MAXL, One, MAXL) + } + + Return (Local1) + } + + Device(HPET) { + Name(_HID, EISAID("PNP0103")) + Name(_UID, 0) + Method (_STA, 0, NotSerialized) { + If(LEqual(\_SB.HPET, 0)) { + Return(0x00) + } Else { + Return(0x0F) + } + } + Name(_CRS, ResourceTemplate() { + DWordMemory( + ResourceConsumer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, + 0xFED00000, + 0xFED003FF, + 0x00000000, + 0x00000400 /* 1K memory: FED00000 - FED003FF */ + ) + }) + } + + + /**************************************************************** + * LPC ISA bridge + ****************************************************************/ + + Device (ISA) + { + Name (_ADR, 0x001f0000) /* device 31, fn 0 */ + + /* PCI Interrupt Routing Register 1 - PIRQA..PIRQD */ + OperationRegion(PIRQ, PCI_Config, 0x60, 0x4) + Scope(\) { + Field (\_SB.PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8 + } + } + /* + PCI Interrupt Routing Register 2 (PIRQE..PIRQH) cannot be + used because of existing Xen IRQ limitations (4 PCI links + only) + */ + + /* LPC_I/O: I/O Decode Ranges Register */ + OperationRegion(LPCD, PCI_Config, 0x80, 0x2) + Field(LPCD, AnyAcc, NoLock, Preserve) { + COMA, 3, + , 1, + COMB, 3, + + Offset(0x01), + LPTD, 2, + , 2, + FDCD, 2 + } + + /* LPC_EN: LPC I/F Enables Register */ + OperationRegion(LPCE, PCI_Config, 0x82, 0x2) + Field(LPCE, AnyAcc, NoLock, Preserve) { + CAEN, 1, + CBEN, 1, + LPEN, 1, + FDEN, 1 + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + Name (CRS, ResourceTemplate () + { + /* TODO: list hidden resources */ + IO (Decode16, 0x0010, 0x0010, 0x00, 0x10) + IO (Decode16, 0x0022, 0x0022, 0x00, 0x0C) + IO (Decode16, 0x0030, 0x0030, 0x00, 0x10) + IO (Decode16, 0x0044, 0x0044, 0x00, 0x1C) + IO (Decode16, 0x0062, 0x0062, 0x00, 0x02) + IO (Decode16, 0x0065, 0x0065, 0x00, 0x0B) + IO (Decode16, 0x0072, 0x0072, 0x00, 0x0E) + IO (Decode16, 0x0080, 0x0080, 0x00, 0x01) + IO (Decode16, 0x0084, 0x0084, 0x00, 0x03) + IO (Decode16, 0x0088, 0x0088, 0x00, 0x01) + IO (Decode16, 0x008C, 0x008C, 0x00, 0x03) + IO (Decode16, 0x0090, 0x0090, 0x00, 0x10) + IO (Decode16, 0x00A2, 0x00A2, 0x00, 0x1C) + IO (Decode16, 0x00E0, 0x00E0, 0x00, 0x10) + IO (Decode16, 0x08A0, 0x08A0, 0x00, 0x04) + IO (Decode16, 0x0CC0, 0x0CC0, 0x00, 0x10) + IO (Decode16, 0x04D0, 0x04D0, 0x00, 0x02) + }) + Method (_CRS, 0, NotSerialized) + { + Return (CRS) + } + } + + Device (PIC) + { + Name (_HID, EisaId ("PNP0000")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) + IRQNoFlags () {2} + }) + } + + Device (DMA0) + { + Name (_HID, EisaId ("PNP0200")) + Name (_CRS, ResourceTemplate () + { + DMA (Compatibility, BusMaster, Transfer8) {4} + IO (Decode16, 0x0000, 0x0000, 0x00, 0x10) + IO (Decode16, 0x0081, 0x0081, 0x00, 0x03) + IO (Decode16, 0x0087, 0x0087, 0x00, 0x01) + IO (Decode16, 0x0089, 0x0089, 0x00, 0x03) + IO (Decode16, 0x008F, 0x008F, 0x00, 0x01) + IO (Decode16, 0x00C0, 0x00C0, 0x00, 0x20) + IO (Decode16, 0x0480, 0x0480, 0x00, 0x10) + }) + } + + Device (TMR) + { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0040, 0x0040, 0x00, 0x04) + IRQNoFlags () {0} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0070, 0x0070, 0x00, 0x02) + IRQNoFlags () {8} + }) + } + + Device (SPKR) + { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0061, 0x0061, 0x00, 0x01) + }) + } + + Device (PS2M) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_CID, 0x130FD041) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IRQNoFlags () {12} + }) + } + + Device (PS2K) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, 0x0B03D041) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0060, 0x0060, 0x00, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x00, 0x01) + IRQNoFlags () {1} + }) + } + + Device(FDC0) + { + Name(_HID, EisaId("PNP0700")) + Method(_STA, 0, NotSerialized) + { + Store(FDEN, Local0) + If (LEqual(Local0, 0)) { + Return (0x00) + } Else { + Return (0x0F) + } + } + + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO(Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags() { 6 } + DMA(Compatibility, NotBusMaster, Transfer8) { 2 } + }) + } + + Device (UAR1) + { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, 0x01) + Method (_STA, 0, NotSerialized) + { + If(LEqual(\_SB.UAR1, 0)) { + Return(0x00) + } Else { + Return(0x0F) + } + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x03F8, 0x03F8, 8, 8) + IRQNoFlags () {4} + }) + } + + Device (UAR2) + { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + If(LEqual(\_SB.UAR2, 0)) { + Return(0x00) + } Else { + Return(0x0F) + } + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x02F8, 0x02F8, 8, 8) + IRQNoFlags () {3} + }) + } + + Device (LTP1) + { + Name (_HID, EisaId ("PNP0400")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + If(LEqual(\_SB.LTP1, 0)) { + Return(0x00) + } Else { + Return(0x0F) + } + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x0378, 0x0378, 0x08, 0x08) + IRQNoFlags () {7} + }) + } + + Device(VGID) { + Name(_HID, EisaId ("XEN0000")) + Name(_UID, 0x00) + Name(_CID, "VM_Gen_Counter") + Name(_DDN, "VM_Gen_Counter") + Method(_STA, 0, NotSerialized) + { + If(LEqual(\_SB.VGIA, 0x00000000)) { + Return(0x00) + } Else { + Return(0x0F) + } + } + Name(PKG, Package () + { + 0x00000000, + 0x00000000 + }) + Method(ADDR, 0, NotSerialized) + { + Store(\_SB.VGIA, Index(PKG, 0)) + Return(PKG) + } + } + + /* EHCI Controller 0:1d.0 */ + + Device (EHC1) + { + Name(_ADR, 0x001d0000) + + /* Power Resources for Wake */ + Name(_PRW, Package() { 13, 4 }) + + /* Highest D state in S3 state */ + Name(_S3D, 2) + + /* Highest D state in S4 state */ + Name(_S4D, 2) + + Device (HUB7) + { + Name(_ADR, 0x00000000) + + Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */ + Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */ + Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */ + Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */ + } + } + } + } + } + /* _S3 and _S4 are in separate SSDTs */ + Name (\_S5, Package (0x04) { + 0x00, /* PM1a_CNT.SLP_TYP */ + 0x00, /* PM1b_CNT.SLP_TYP */ + 0x00, /* reserved */ + 0x00 /* reserved */ + }) + Name(PICD, 0) + Method(_PIC, 1) { + Store(Arg0, PICD) + } +} From patchwork Tue Jun 20 17:15:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:15 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4e6826f3-0f8e-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281436; x=1689873436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rmjMX94/CnuZ+DKqQNwFS/gJapQsRaGCdFJ+ixf1jU8=; b=nEXO+tw/MG+WTEDv60cExTVrsHhY517hsBKXVfVqM6MvGnYFb8LU9YYZvjI2W9g1cK TLQxCR2B815QgXYKBrDkId7DekHBQ5ps/asJznNk1vJVBZad57bdHSKAPPCcglUnW5qG gRgE0Ws+r17fOJYv+lVpX2XmhbFcR4AcESeqrxlGSfFo9X9KcgWtyrqT+Ohz4IvnuKJT U3dkQBmezB4TO9iTTIXo1T46OuePEIzs0fqW5h/YSrqJvIs/9bI85684LYDYPbGS0zMo /xtPSNEoA4AutkSwGIwWEgP18lfb5NP6eOLUbWx1yUzK4uv+PPb7C35gGdihBuQ08A/9 RCcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281436; x=1689873436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rmjMX94/CnuZ+DKqQNwFS/gJapQsRaGCdFJ+ixf1jU8=; b=fH712lG4fqYi0x8dP024TgjQfCOHnOQRBRbpDS1sPjs+WP3EsNbwVhrm5K198zIxtN n0AUXcAoR013S9vmgXAEO6irImbulVGcqI0WkqOSOgywVq0Ku4T1rD8vVFcKKrjIj4DX VlPhTj+vU8EvIQb2mYSvfsoGogiMSGtE0mAAXNQgJaI8b14WUMAxlnFuXlqDK0z+WM5i E/K2OG5dUEhiHrqwj9Tevsckv1VDovMPNjD6TrGrnrYRaQAHzfX6HuMNzQWCwMu/5TUf /uPG8A58hkdFNKj15xixQSiIe3P8NMcKPG5YIMFrb/4niiZZMBF89WWieNJkSDUzB98Z LKYA== X-Gm-Message-State: AC+VfDxipHzj31BAeSXRNSBOJSevWlqV/v88rqtVZtJuIk1l50SBKI6D gax8PHR8FlrcVepS+8N6oQUtfEaNvI2LHw== X-Google-Smtp-Source: ACHHUZ5IYdtGjOJynA9TpDdq64wxYLUQAEz6ka8t3dG2aTivhnlshW2hypqfbNz5NkT/xVvlAf4LZQ== X-Received: by 2002:a25:b188:0:b0:be4:684e:1971 with SMTP id h8-20020a25b188000000b00be4684e1971mr11353800ybj.63.1687281436189; Tue, 20 Jun 2023 10:17:16 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Anthony PERARD Subject: [PATCH v2 02/12] Makefile: build and use new DSDT table for Q35 Date: Tue, 20 Jun 2023 13:15:42 -0400 Message-Id: <1579bbf01f01ff92496260866f87b263a95cd8fe.1687215890.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Provide building for newly added dsdt_q35.asl file, in a way similar to dsdt.asl. Note that '15cpu' ACPI tables are only applicable to qemu-traditional (which have no support for Q35), so we need to use 'anycpu' version only. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/firmware/hvmloader/Makefile | 2 +- tools/libacpi/Makefile | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/tools/firmware/hvmloader/Makefile b/tools/firmware/hvmloader/Makefile index e5de1ade17..e3c8eb3ca1 100644 --- a/tools/firmware/hvmloader/Makefile +++ b/tools/firmware/hvmloader/Makefile @@ -70,7 +70,7 @@ rombios.o: roms.inc smbios.o: CFLAGS += -D__SMBIOS_DATE__="\"$(SMBIOS_REL_DATE)\"" ACPI_PATH = ../../libacpi -DSDT_FILES = dsdt_anycpu.c dsdt_15cpu.c dsdt_anycpu_qemu_xen.c +DSDT_FILES = dsdt_anycpu.c dsdt_15cpu.c dsdt_anycpu_qemu_xen.c dsdt_q35_anycpu_qemu_xen.c ACPI_OBJS = $(patsubst %.c,%.o,$(DSDT_FILES)) build.o static_tables.o $(ACPI_OBJS): CFLAGS += -iquote . -DLIBACPI_STDUTILS=\"$(CURDIR)/util.h\" CFLAGS += -I$(ACPI_PATH) diff --git a/tools/libacpi/Makefile b/tools/libacpi/Makefile index b21a64c6b4..d1ad2c6d85 100644 --- a/tools/libacpi/Makefile +++ b/tools/libacpi/Makefile @@ -11,7 +11,7 @@ endif MK_DSDT = $(ACPI_BUILD_DIR)/mk_dsdt -C_SRC-$(CONFIG_X86) = dsdt_anycpu.c dsdt_15cpu.c dsdt_anycpu_qemu_xen.c dsdt_pvh.c +C_SRC-$(CONFIG_X86) = dsdt_anycpu.c dsdt_15cpu.c dsdt_anycpu_qemu_xen.c dsdt_q35_anycpu_qemu_xen.c dsdt_pvh.c C_SRC-$(CONFIG_ARM_64) = dsdt_anycpu_arm.c DSDT_FILES ?= $(C_SRC-y) C_SRC = $(addprefix $(ACPI_BUILD_DIR)/, $(DSDT_FILES)) @@ -54,6 +54,14 @@ $(ACPI_BUILD_DIR)/dsdt_%cpu.asl: dsdt.asl dsdt_acpi_info.asl $(MK_DSDT) $(MK_DSDT) --debug=$(debug) --maxcpu $* >> $@.$(TMP_SUFFIX) mv -f $@.$(TMP_SUFFIX) $@ +$(ACPI_BUILD_DIR)/dsdt_q35_anycpu_qemu_xen.asl: dsdt_q35.asl dsdt_acpi_info.asl $(MK_DSDT) + # Remove last bracket + awk 'NR > 1 {print s} {s=$$0}' $< > $@.$(TMP_SUFFIX) + cat dsdt_acpi_info.asl >> $@.$(TMP_SUFFIX) + $(MK_DSDT) --debug=$(debug) --dm-version qemu-xen >> $@.$(TMP_SUFFIX) + mv -f $@.$(TMP_SUFFIX) $@ + + $(ACPI_BUILD_DIR)/dsdt_pvh.asl: dsdt_acpi_info.asl $(MK_DSDT) printf "DefinitionBlock (\"DSDT.aml\", \"DSDT\", 5, \"Xen\", \"HVM\", 0)\n{" > $@ cat dsdt_acpi_info.asl >> $@ From patchwork Tue Jun 20 17:15:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DECBEB64D8 for ; Tue, 20 Jun 2023 17:17:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551987.861807 (Exim 4.92) (envelope-from ) id 1qBeyn-0005x7-Bh; Tue, 20 Jun 2023 17:17:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551987.861807; Tue, 20 Jun 2023 17:17:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeyn-0005ww-8J; Tue, 20 Jun 2023 17:17:21 +0000 Received: by outflank-mailman (input) for mailman id 551987; Tue, 20 Jun 2023 17:17:20 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeym-0005iB-E0 for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 17:17:20 +0000 Received: from mail-yb1-xb29.google.com (mail-yb1-xb29.google.com [2607:f8b0:4864:20::b29]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 4f6b5504-0f8e-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 19:17:19 +0200 (CEST) Received: by mail-yb1-xb29.google.com with SMTP id 3f1490d57ef6-bd20beffda6so5024182276.1 for ; Tue, 20 Jun 2023 10:17:19 -0700 (PDT) Received: from joel-Precision-7920-Tower.. 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Supported return values: - MACHINE_TYPE_I440 - MACHINE_TYPE_Q35 - MACHINE_TYPE_UNKNOWN, results in the error message being printed followed by calling BUG() in hvmloader. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/firmware/hvmloader/pci_regs.h | 4 +++ tools/firmware/hvmloader/util.c | 47 +++++++++++++++++++++++++++++ tools/firmware/hvmloader/util.h | 8 +++++ 3 files changed, 59 insertions(+) diff --git a/tools/firmware/hvmloader/pci_regs.h b/tools/firmware/hvmloader/pci_regs.h index 7bf2d873ab..4d4dc0cd01 100644 --- a/tools/firmware/hvmloader/pci_regs.h +++ b/tools/firmware/hvmloader/pci_regs.h @@ -107,6 +107,10 @@ #define PCI_INTEL_OPREGION 0xfc /* 4 bits */ +#define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_82441 0x1237 +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 + #endif /* __HVMLOADER_PCI_REGS_H__ */ /* diff --git a/tools/firmware/hvmloader/util.c b/tools/firmware/hvmloader/util.c index e82047d993..a8685ee23a 100644 --- a/tools/firmware/hvmloader/util.c +++ b/tools/firmware/hvmloader/util.c @@ -22,6 +22,7 @@ #include "hypercall.h" #include "ctype.h" #include "vnuma.h" +#include "pci_regs.h" #include #include #include @@ -735,6 +736,52 @@ void __bug(const char *file, int line) crash(); } + +static int machine_type = MACHINE_TYPE_UNDEFINED; + +int get_pc_machine_type(void) +{ + uint16_t vendor_id; + uint16_t device_id; + + if (machine_type != MACHINE_TYPE_UNDEFINED) + return machine_type; + + machine_type = MACHINE_TYPE_UNKNOWN; + + vendor_id = pci_readw(0, PCI_VENDOR_ID); + device_id = pci_readw(0, PCI_DEVICE_ID); + + /* only Intel platforms are emulated currently */ + if (vendor_id == PCI_VENDOR_ID_INTEL) + { + switch (device_id) + { + case PCI_DEVICE_ID_INTEL_82441: + machine_type = MACHINE_TYPE_I440; + printf("Detected i440 chipset\n"); + break; + + case PCI_DEVICE_ID_INTEL_Q35_MCH: + machine_type = MACHINE_TYPE_Q35; + printf("Detected Q35 chipset\n"); + break; + + default: + break; + } + } + + if (machine_type == MACHINE_TYPE_UNKNOWN) + { + printf("Unknown emulated chipset encountered, VID=%04Xh, DID=%04Xh\n", + vendor_id, device_id); + BUG(); + } + + return machine_type; +} + static void validate_hvm_info(struct hvm_info_table *t) { uint8_t *ptr = (uint8_t *)t; diff --git a/tools/firmware/hvmloader/util.h b/tools/firmware/hvmloader/util.h index 87be213dec..f6a6cc3421 100644 --- a/tools/firmware/hvmloader/util.h +++ b/tools/firmware/hvmloader/util.h @@ -90,6 +90,14 @@ void pci_write(uint32_t devfn, uint32_t reg, uint32_t len, uint32_t val); #define pci_writew(devfn, reg, val) pci_write(devfn, reg, 2, (uint16_t)(val)) #define pci_writel(devfn, reg, val) pci_write(devfn, reg, 4, (uint32_t)(val)) +/* Emulated machine types */ +#define MACHINE_TYPE_UNDEFINED 0 +#define MACHINE_TYPE_I440 1 +#define MACHINE_TYPE_Q35 2 +#define MACHINE_TYPE_UNKNOWN (-1) + +int get_pc_machine_type(void); + /* Get a pointer to the shared-info page */ struct shared_info *get_shared_info(void) __attribute__ ((const)); From patchwork Tue Jun 20 17:15:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 936D6EB64DC for ; Tue, 20 Jun 2023 17:17:43 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551988.861817 (Exim 4.92) (envelope-from ) id 1qBeyp-0006Ew-No; Tue, 20 Jun 2023 17:17:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551988.861817; Tue, 20 Jun 2023 17:17:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeyp-0006Em-Jn; Tue, 20 Jun 2023 17:17:23 +0000 Received: by outflank-mailman (input) for mailman id 551988; Tue, 20 Jun 2023 17:17:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeyn-0005iB-Ky for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 17:17:21 +0000 Received: from mail-yb1-xb2a.google.com (mail-yb1-xb2a.google.com [2607:f8b0:4864:20::b2a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 5074ba68-0f8e-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 19:17:21 +0200 (CEST) Received: by mail-yb1-xb2a.google.com with SMTP id 3f1490d57ef6-bd61dd9a346so5007021276.2 for ; Tue, 20 Jun 2023 10:17:21 -0700 (PDT) Received: from joel-Precision-7920-Tower.. ([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:19 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5074ba68-0f8e-11ee-b234-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281439; x=1689873439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hrsL9N7k7kk6HzmUebq9GcrGzTo0jj1csEdzXuASa80=; b=r458G9N//EmRZupWk7DFyj1OcVfX+K2vo0GSHriPM9JysWQHtkfXbvRj2A57h3lOjf fyFoq+3f0BVPNnuB1GeEmj/6CcCBiMO/W8RJ/TBs3DSbf4xFu1qKxMJjmkdM3NaRZl4j 4HXeHSEI/PQxaehhqkYli3zoDMt2BuSwvx5PMO53c/ovICZvLlin/rnODXN8m3GV12ab JXNy2GdcDcW895FJ4HzQE/51Ykts4VqZbOr00AoJm2cq5Yrl3WRFZonHLAcU69svswLb baaI2MY0TvafazzJkZNgZbxLlWQT8Rj90jRCnnpZmT8VHR9g0X7I8IpMFPmfiNuu6XPI HPEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281439; x=1689873439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hrsL9N7k7kk6HzmUebq9GcrGzTo0jj1csEdzXuASa80=; b=Gpa/lRkANV2QKrWNEYqYMEr1ohfsTKUg9Ax2B7NZxqE9Eb8lwHrheY1zVSNsM6lI1+ HYBPSPWa61CFbY5VG1XVXxY3uBJMss92+um6on1jUT+5MwPwakly/Hq7HxufOkOcUcgv zMHE/1xPOuKW28q5DWC+yR4k3uXccTW3P9ItjUuq0Bwk7CvNNAVGu3eFjhj5lxoI/vDZ q/oviWRYa+eG7KxIebbO7v40fXt2oPukokVdRokqqOLQFizczETD/EKLEePLqNC/hDTz iHiY5HDk0cuY2ThUmu0CxwKHTbYh2DJEP4v36O5SpyoatxQ+jAZO7X4y0x5XlkHggSa1 iALQ== X-Gm-Message-State: AC+VfDyALFAw0aOumqhsufb5KjyxmX2VQ9LJd0axds2Dj1RiiW448KH1 d9NBer+ZAiAvY3Hv2KdEz7yZaUWwQla23g== X-Google-Smtp-Source: ACHHUZ4hfo79N+MtJ+Ae9j/hgIrf2qXfKtJUxQu6OxiIhiXFuIgZUxkSS/4hU8G5OWESk5KBKcsNbA== X-Received: by 2002:a25:ae48:0:b0:bcf:ef73:1431 with SMTP id g8-20020a25ae48000000b00bcfef731431mr9113565ybe.26.1687281439615; Tue, 20 Jun 2023 10:17:19 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Anthony PERARD Subject: [PATCH v2 04/12] hvmloader: add ACPI enabling for Q35 Date: Tue, 20 Jun 2023 13:15:44 -0400 Message-Id: <0aad12501165eaba2a3b987b37779ff7ced6ce82.1687215890.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 In order to turn on ACPI for OS, we need to write a chipset-specific value to SMI_CMD register (sort of imitation of the APM->ACPI switch on real systems). Modify acpi_enable_sci() function to support both i440 and Q35 emulation. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/firmware/hvmloader/hvmloader.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/tools/firmware/hvmloader/hvmloader.c b/tools/firmware/hvmloader/hvmloader.c index c58841e5b5..ef0e66b214 100644 --- a/tools/firmware/hvmloader/hvmloader.c +++ b/tools/firmware/hvmloader/hvmloader.c @@ -259,8 +259,17 @@ static const struct bios_config *detect_bios(void) static void acpi_enable_sci(void) { uint8_t pm1a_cnt_val; + uint8_t acpi_enable_val; + +#define SMI_CMD_IOPORT 0xb2 +#define PIIX4_ACPI_ENABLE 0xf1 +#define ICH9_ACPI_ENABLE 0x02 + + if (get_pc_machine_type() == MACHINE_TYPE_Q35) + acpi_enable_val = ICH9_ACPI_ENABLE; + else + acpi_enable_val = PIIX4_ACPI_ENABLE; -#define PIIX4_SMI_CMD_IOPORT 0xb2 #define PIIX4_ACPI_ENABLE 0xf1 /* @@ -269,7 +278,7 @@ static void acpi_enable_sci(void) */ pm1a_cnt_val = inb(ACPI_PM1A_CNT_BLK_ADDRESS_V1); if ( !(pm1a_cnt_val & ACPI_PM1C_SCI_EN) ) - outb(PIIX4_SMI_CMD_IOPORT, PIIX4_ACPI_ENABLE); + outb(SMI_CMD_IOPORT, acpi_enable_val); pm1a_cnt_val = inb(ACPI_PM1A_CNT_BLK_ADDRESS_V1); BUG_ON(!(pm1a_cnt_val & ACPI_PM1C_SCI_EN)); From patchwork Tue Jun 20 17:15:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2290DEB64D7 for ; Tue, 20 Jun 2023 17:17:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551989.861823 (Exim 4.92) (envelope-from ) id 1qBeyq-0006JL-3P; Tue, 20 Jun 2023 17:17:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551989.861823; Tue, 20 Jun 2023 17:17:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeyp-0006I8-Tn; Tue, 20 Jun 2023 17:17:23 +0000 Received: by outflank-mailman (input) for mailman id 551989; Tue, 20 Jun 2023 17:17:23 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeyp-0005iB-A7 for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 17:17:23 +0000 Received: from mail-yb1-xb34.google.com (mail-yb1-xb34.google.com [2607:f8b0:4864:20::b34]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 516987df-0f8e-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 19:17:22 +0200 (CEST) Received: by mail-yb1-xb34.google.com with SMTP id 3f1490d57ef6-bd6d9d7da35so5098134276.0 for ; Tue, 20 Jun 2023 10:17:22 -0700 (PDT) Received: from joel-Precision-7920-Tower.. ([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:20 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 516987df-0f8e-11ee-b234-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281441; x=1689873441; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YD449Sev2tYSUJnmMC+HzxBJLT1Su39PvBIo4ApXUGY=; b=adRdWFSbOakGYazV9dcYXomiWWj7+4rJ6o1sZx3SvR8hyPBj+FsOCRxipT6ZXCv51h 57kB2SqdQvNHyE+E9TzTG/a7nsz3ll0LHU67ZHKSvSgkOqsR7rAgf1AN4M7UF828ddHL QlOw1k32tsp/vY9FOVcuWgx5b+RHgeZ7r3WNSnU+0c3SIWg9W87cXrXjoM9BRLUH1lvk ot2GiNtfkbvvPAhDYD64MY57bSWNQMGMFiHZ92iLKRWA0O+QIbdZfKenCbdghHnqLMAB U+QjDjVGr7jSAXjutlQTdFe6WfZIxtLiMmb9pWtJs3PxU7sk5AwrTKe1jBZcnrDIz81x FQUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281441; x=1689873441; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YD449Sev2tYSUJnmMC+HzxBJLT1Su39PvBIo4ApXUGY=; b=KMs3fTXZlw0/OxoYkCVyC4ze72osOUgLvm18aNR8GWIjrctQtk8rmJRaPjsHU8o7F1 fji1AoZ4eeS7IWMoEbotHc2JpqbYKp7dfxtGlTNP76DzVe7OFxQYVUHRLszeuGSPRXDL 39wuQUSL6ezYy0coWJUH0cSNv/iEHAFcDmMwrasXAzQTc/PSpbQDAwHkufipbWVImqbT vxzPldyPAOFKgs8g787bbW3N/03CxAbDUVHqztD0o32pG2QTRESVf9oiQzX8IWl/10O2 rDFukEycWLVDnF36tyODuTbTLLLrlGedAooc0Lo7N6DjNvgC7fF6H4H+d+sS/eusARIe lApg== X-Gm-Message-State: AC+VfDzM06HrDI6gMcCU3iA/EPKjqr/ojmI7+tl/wVefy2v0UKF3NVt0 cfY8dU7DdC0MAk5/ytPT39H3JSHQR5i3Kg== X-Google-Smtp-Source: ACHHUZ5RtF84snsglSfujdJdWSxsr7g0T2grHUJCkp1rzv3jieejRbWNytcQ3zIPz/2IHBQfkHq10A== X-Received: by 2002:a25:b09:0:b0:bfe:8a76:18da with SMTP id 9-20020a250b09000000b00bfe8a7618damr15543ybl.49.1687281441220; Tue, 20 Jun 2023 10:17:21 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Anthony PERARD Subject: [PATCH v2 05/12] hvmloader: add Q35 DSDT table loading Date: Tue, 20 Jun 2023 13:15:45 -0400 Message-Id: <6eae751cfad220a62f23bc551b78416c66213f38.1687215890.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Allows to select Q35 DSDT table in hvmloader_acpi_build_tables(). Function get_pc_machine_type() is used to select a proper table (i440/q35). As we are bound to the qemu-xen device model for Q35, no need to initialize config->dsdt_15cpu/config->dsdt_15cpu_len fields. Added the seabios/ovmf loading here as well. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/firmware/hvmloader/ovmf.c | 5 +++++ tools/firmware/hvmloader/seabios.c | 5 +++++ tools/firmware/hvmloader/util.c | 13 +++++++++++-- tools/firmware/hvmloader/util.h | 2 ++ 4 files changed, 23 insertions(+), 2 deletions(-) diff --git a/tools/firmware/hvmloader/ovmf.c b/tools/firmware/hvmloader/ovmf.c index 23610a0717..2945c8a516 100644 --- a/tools/firmware/hvmloader/ovmf.c +++ b/tools/firmware/hvmloader/ovmf.c @@ -125,6 +125,11 @@ static void ovmf_acpi_build_tables(void) .dsdt_15cpu_len = 0 }; + if (get_pc_machine_type() == MACHINE_TYPE_Q35) { + config.dsdt_anycpu = dsdt_q35_anycpu_qemu_xen; + config.dsdt_anycpu_len = dsdt_q35_anycpu_qemu_xen_len; + } + hvmloader_acpi_build_tables(&config, ACPI_PHYSICAL_ADDRESS); } diff --git a/tools/firmware/hvmloader/seabios.c b/tools/firmware/hvmloader/seabios.c index 444d118ddb..72aabea130 100644 --- a/tools/firmware/hvmloader/seabios.c +++ b/tools/firmware/hvmloader/seabios.c @@ -96,6 +96,11 @@ static void seabios_acpi_build_tables(void) .dsdt_15cpu_len = 0, }; + if (get_pc_machine_type() == MACHINE_TYPE_Q35) { + config.dsdt_anycpu = dsdt_q35_anycpu_qemu_xen; + config.dsdt_anycpu_len = dsdt_q35_anycpu_qemu_xen_len; + } + hvmloader_acpi_build_tables(&config, rsdp); add_table(rsdp); } diff --git a/tools/firmware/hvmloader/util.c b/tools/firmware/hvmloader/util.c index a8685ee23a..ea416ebe10 100644 --- a/tools/firmware/hvmloader/util.c +++ b/tools/firmware/hvmloader/util.c @@ -984,8 +984,17 @@ void hvmloader_acpi_build_tables(struct acpi_config *config, } else if ( !strncmp(s, "qemu_xen", 9) ) { - config->dsdt_anycpu = dsdt_anycpu_qemu_xen; - config->dsdt_anycpu_len = dsdt_anycpu_qemu_xen_len; + if (get_pc_machine_type() == MACHINE_TYPE_Q35) + { + config->dsdt_anycpu = dsdt_q35_anycpu_qemu_xen; + config->dsdt_anycpu_len = dsdt_q35_anycpu_qemu_xen_len; + } + else + { + config->dsdt_anycpu = dsdt_anycpu_qemu_xen; + config->dsdt_anycpu_len = dsdt_anycpu_qemu_xen_len; + } + config->dsdt_15cpu = NULL; config->dsdt_15cpu_len = 0; } diff --git a/tools/firmware/hvmloader/util.h b/tools/firmware/hvmloader/util.h index f6a6cc3421..c6747c336d 100644 --- a/tools/firmware/hvmloader/util.h +++ b/tools/firmware/hvmloader/util.h @@ -278,7 +278,9 @@ bool check_overlap(uint64_t start, uint64_t size, uint64_t reserved_start, uint64_t reserved_size); extern const unsigned char dsdt_anycpu_qemu_xen[], dsdt_anycpu[], dsdt_15cpu[]; +extern const unsigned char dsdt_q35_anycpu_qemu_xen[]; extern const int dsdt_anycpu_qemu_xen_len, dsdt_anycpu_len, dsdt_15cpu_len; +extern const int dsdt_q35_anycpu_qemu_xen_len; unsigned long acpi_pages_allocated(void); From patchwork Tue Jun 20 17:15:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8055EB64DB for ; Tue, 20 Jun 2023 17:17:47 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551991.861837 (Exim 4.92) (envelope-from ) id 1qBeyt-0006p2-8K; Tue, 20 Jun 2023 17:17:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551991.861837; Tue, 20 Jun 2023 17:17:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeyt-0006on-5I; Tue, 20 Jun 2023 17:17:27 +0000 Received: by outflank-mailman (input) for mailman id 551991; Tue, 20 Jun 2023 17:17:26 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeys-0005QM-6i for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 17:17:26 +0000 Received: from mail-yw1-x1134.google.com (mail-yw1-x1134.google.com [2607:f8b0:4864:20::1134]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 5264411f-0f8e-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 19:17:24 +0200 (CEST) Received: by mail-yw1-x1134.google.com with SMTP id 00721157ae682-56fff21c2ebso53685627b3.3 for ; Tue, 20 Jun 2023 10:17:24 -0700 (PDT) Received: from joel-Precision-7920-Tower.. ([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:22 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5264411f-0f8e-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281443; x=1689873443; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K2J1bNKwymcLCcica7VZKf11hCWokpfQzX8mE5sXyNo=; b=LZXZlej+K+2mi+QtRPDeuSiUGjLupvYCx2+7xRf6ywldCJs6yisa+0DNOPO1ZHPFOO IHtbs1VQYBms9Gp7kgBBCqadOl2zuuF5YlymFFcY0OOULvJCiLn8i7ATSf0fzUVJBeRa XrAJyjYmh4Ftxicni6gJMPY9D+4QTwDnbwgUB+Q9cj4Zta9ZY/yJDix+ZEbR++N8DYiw jJ9SjbwmVH7dLHcLv/b/OvnTetsSWDSnFufAwNri67evQigTGYiqw9zmF1gGDCdbrCiK qb2bWgmR/q+DTIr7aTiPvwRnaKbqRgnR8tBBiQpCnoegydkoDCYQyoYTU5A8J381KjgG DSqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281443; x=1689873443; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K2J1bNKwymcLCcica7VZKf11hCWokpfQzX8mE5sXyNo=; b=USFYdw6moSxB36JapTZRTUQz7jMP4Nv6Lcs8JOt2FVq+ufR0qNz04HQYpFXiTSv5Ki o/1/KNFVve2jwAGfPjiR7j0uESp8PYicsRMhdgw1ALH8+z9x2acX+lglkLeFGSAPwBAP W7YpvLGHOX0yT633gBpH2qr8mfghghhh4/MuFpjqHCTQQ43ddMuK/aJJDVe3rfuW3HhY LauP2Lle+eENopukMi5SbVyro36+xZJrT/YNZsFosRbWt7P1BQ2EqXapbaoY6vtO+LTT qhJbMjrmwkW5jAGya9t1rT3GbBGLmN2+RateTdolDlmQT1FKIQ3OQ07ePV3ycXAlYdOW KRdQ== X-Gm-Message-State: AC+VfDzKGFfVnaYD7aVDKRa3OTTzRIJiew9z5CVA/aQuyI2AWzM4E84p HQKjT1WVqfllR/FV+aiJGWhYa5f2EIEtxQ== X-Google-Smtp-Source: ACHHUZ4XHmDRoy3fVyRInCf5TN0utBd/CpKeJ1xE1JOORcBMmo0GGOD5iOo+u5GQosrgQoRbYL56yg== X-Received: by 2002:a05:6902:cd:b0:bd5:9d1e:7182 with SMTP id i13-20020a05690200cd00b00bd59d1e7182mr9697443ybs.8.1687281442753; Tue, 20 Jun 2023 10:17:22 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Anthony PERARD Subject: [PATCH v2 06/12] hvmloader: add basic Q35 support Date: Tue, 20 Jun 2023 13:15:46 -0400 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 This patch does following: 1. Move PCI-device specific initialization out of pci_setup function to the newly created class_specific_pci_device_setup function to simplify code. 2. PCI-device specific initialization extended with LPC controller initialization 3. Initialize PIRQA...{PIRQD, PIRQH} routing accordingly to the emulated south bridge (either located on PCI_ISA_DEVFN or PCI_ICH9_LPC_DEVFN). Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/firmware/hvmloader/config.h | 1 + tools/firmware/hvmloader/pci.c | 162 +++++++++++++++++++----------- 2 files changed, 104 insertions(+), 59 deletions(-) diff --git a/tools/firmware/hvmloader/config.h b/tools/firmware/hvmloader/config.h index c82adf6dc5..de3bbed609 100644 --- a/tools/firmware/hvmloader/config.h +++ b/tools/firmware/hvmloader/config.h @@ -54,6 +54,7 @@ extern uint8_t ioapic_version; #define PCI_ISA_DEVFN 0x08 /* dev 1, fn 0 */ #define PCI_ISA_IRQ_MASK 0x0c20U /* ISA IRQs 5,10,11 are PCI connected */ +#define PCI_ICH9_LPC_DEVFN 0xf8 /* dev 31, fn 0 */ #define ACPI_TIS_HDR_ADDRESS 0xFED40F00UL diff --git a/tools/firmware/hvmloader/pci.c b/tools/firmware/hvmloader/pci.c index 257a6feb61..8249f70806 100644 --- a/tools/firmware/hvmloader/pci.c +++ b/tools/firmware/hvmloader/pci.c @@ -34,6 +34,7 @@ const uint32_t pci_mem_end = RESERVED_MEMBASE; uint64_t pci_hi_mem_start = 0, pci_hi_mem_end = 0; enum virtual_vga virtual_vga = VGA_none; +uint32_t vga_devfn = 256; unsigned long igd_opregion_pgbase = 0; /* Check if the specified range conflicts with any reserved device memory. */ @@ -75,14 +76,93 @@ static int find_next_rmrr(uint32_t base) return next_rmrr; } +#define SCI_EN_IOPORT (ACPI_PM1A_EVT_BLK_ADDRESS_V1 + 0x30) +#define GBL_SMI_EN (1 << 0) +#define APMC_EN (1 << 5) + +static void class_specific_pci_device_setup(uint16_t vendor_id, + uint16_t device_id, + uint8_t bus, uint8_t devfn) +{ + uint16_t class; + + class = pci_readw(devfn, PCI_CLASS_DEVICE); + + switch ( class ) + { + case 0x0300: + /* If emulated VGA is found, preserve it as primary VGA. */ + if ( (vendor_id == 0x1234) && (device_id == 0x1111) ) + { + vga_devfn = devfn; + virtual_vga = VGA_std; + } + else if ( (vendor_id == 0x1013) && (device_id == 0xb8) ) + { + vga_devfn = devfn; + virtual_vga = VGA_cirrus; + } + else if ( virtual_vga == VGA_none ) + { + vga_devfn = devfn; + virtual_vga = VGA_pt; + if ( vendor_id == 0x8086 ) + { + igd_opregion_pgbase = mem_hole_alloc(IGD_OPREGION_PAGES); + /* + * Write the the OpRegion offset to give the opregion + * address to the device model. The device model will trap + * and map the OpRegion at the give address. + */ + pci_writel(vga_devfn, PCI_INTEL_OPREGION, + igd_opregion_pgbase << PAGE_SHIFT); + } + } + break; + + case 0x0680: + /* PIIX4 ACPI PM. Special device with special PCI config space. */ + ASSERT((vendor_id == 0x8086) && (device_id == 0x7113)); + pci_writew(devfn, 0x20, 0x0000); /* No smb bus IO enable */ + pci_writew(devfn, 0xd2, 0x0000); /* No smb bus IO enable */ + pci_writew(devfn, 0x22, 0x0000); + pci_writew(devfn, 0x3c, 0x0009); /* Hardcoded IRQ9 */ + pci_writew(devfn, 0x3d, 0x0001); + pci_writel(devfn, 0x40, ACPI_PM1A_EVT_BLK_ADDRESS_V1 | 1); + pci_writeb(devfn, 0x80, 0x01); /* enable PM io space */ + break; + + case 0x0601: + /* LPC bridge */ + if (vendor_id == 0x8086 && device_id == 0x2918) + { + pci_writeb(devfn, 0x3c, 0x09); /* Hardcoded IRQ9 */ + pci_writeb(devfn, 0x3d, 0x01); + pci_writel(devfn, 0x40, ACPI_PM1A_EVT_BLK_ADDRESS_V1 | 1); + pci_writeb(devfn, 0x44, 0x80); /* enable PM io space */ + outl(SCI_EN_IOPORT, inl(SCI_EN_IOPORT) | GBL_SMI_EN | APMC_EN); + } + break; + + case 0x0101: + if ( vendor_id == 0x8086 ) + { + /* Intel ICHs since PIIX3: enable IDE legacy mode. */ + pci_writew(devfn, 0x40, 0x8000); /* enable IDE0 */ + pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */ + } + break; + } +} + void pci_setup(void) { uint8_t is_64bar, using_64bar, bar64_relocate = 0; uint32_t devfn, bar_reg, cmd, bar_data, bar_data_upper; uint64_t base, bar_sz, bar_sz_upper, mmio_total = 0; - uint32_t vga_devfn = 256; - uint16_t class, vendor_id, device_id; + uint16_t vendor_id, device_id; unsigned int bar, pin, link, isa_irq; + int is_running_on_q35 = 0; uint8_t pci_devfn_decode_type[256] = {}; /* Resources assignable to PCI devices via BARs. */ @@ -137,13 +217,28 @@ void pci_setup(void) if ( s ) mmio_hole_size = strtoll(s, NULL, 0); + /* check if we are on Q35 and set the flag if it is the case */ + is_running_on_q35 = get_pc_machine_type() == MACHINE_TYPE_Q35; + /* Program PCI-ISA bridge with appropriate link routes. */ isa_irq = 0; for ( link = 0; link < 4; link++ ) { do { isa_irq = (isa_irq + 1) & 15; } while ( !(PCI_ISA_IRQ_MASK & (1U << isa_irq)) ); - pci_writeb(PCI_ISA_DEVFN, 0x60 + link, isa_irq); + + if (is_running_on_q35) + { + pci_writeb(PCI_ICH9_LPC_DEVFN, 0x60 + link, isa_irq); + + /* PIRQE..PIRQH are unused */ + pci_writeb(PCI_ICH9_LPC_DEVFN, 0x68 + link, 0x80); + } + else + { + pci_writeb(PCI_ISA_DEVFN, 0x60 + link, isa_irq); + } + printf("PCI-ISA link %u routed to IRQ%u\n", link, isa_irq); } @@ -154,66 +249,13 @@ void pci_setup(void) /* Scan the PCI bus and map resources. */ for ( devfn = 0; devfn < 256; devfn++ ) { - class = pci_readw(devfn, PCI_CLASS_DEVICE); vendor_id = pci_readw(devfn, PCI_VENDOR_ID); device_id = pci_readw(devfn, PCI_DEVICE_ID); if ( (vendor_id == 0xffff) && (device_id == 0xffff) ) continue; - ASSERT((devfn != PCI_ISA_DEVFN) || - ((vendor_id == 0x8086) && (device_id == 0x7000))); - - switch ( class ) - { - case 0x0300: - /* If emulated VGA is found, preserve it as primary VGA. */ - if ( (vendor_id == 0x1234) && (device_id == 0x1111) ) - { - vga_devfn = devfn; - virtual_vga = VGA_std; - } - else if ( (vendor_id == 0x1013) && (device_id == 0xb8) ) - { - vga_devfn = devfn; - virtual_vga = VGA_cirrus; - } - else if ( virtual_vga == VGA_none ) - { - vga_devfn = devfn; - virtual_vga = VGA_pt; - if ( vendor_id == 0x8086 ) - { - igd_opregion_pgbase = mem_hole_alloc(IGD_OPREGION_PAGES); - /* - * Write the the OpRegion offset to give the opregion - * address to the device model. The device model will trap - * and map the OpRegion at the give address. - */ - pci_writel(vga_devfn, PCI_INTEL_OPREGION, - igd_opregion_pgbase << PAGE_SHIFT); - } - } - break; - case 0x0680: - /* PIIX4 ACPI PM. Special device with special PCI config space. */ - ASSERT((vendor_id == 0x8086) && (device_id == 0x7113)); - pci_writew(devfn, 0x20, 0x0000); /* No smb bus IO enable */ - pci_writew(devfn, 0xd2, 0x0000); /* No smb bus IO enable */ - pci_writew(devfn, 0x22, 0x0000); - pci_writew(devfn, 0x3c, 0x0009); /* Hardcoded IRQ9 */ - pci_writew(devfn, 0x3d, 0x0001); - pci_writel(devfn, 0x40, ACPI_PM1A_EVT_BLK_ADDRESS_V1 | 1); - pci_writeb(devfn, 0x80, 0x01); /* enable PM io space */ - break; - case 0x0101: - if ( vendor_id == 0x8086 ) - { - /* Intel ICHs since PIIX3: enable IDE legacy mode. */ - pci_writew(devfn, 0x40, 0x8000); /* enable IDE0 */ - pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */ - } - break; - } + class_specific_pci_device_setup(vendor_id, device_id, + 0 /* virt_bus support TBD */, devfn); /* * It is recommended that BAR programming be done whilst decode @@ -304,7 +346,9 @@ void pci_setup(void) { /* This is the barber's pole mapping used by Xen. */ link = ((pin - 1) + (devfn >> 3)) & 3; - isa_irq = pci_readb(PCI_ISA_DEVFN, 0x60 + link); + isa_irq = pci_readb(is_running_on_q35 ? + PCI_ICH9_LPC_DEVFN : PCI_ISA_DEVFN, + 0x60 + link); pci_writeb(devfn, PCI_INTERRUPT_LINE, isa_irq); printf("pci dev %02x:%x INT%c->IRQ%u\n", devfn>>3, devfn&7, 'A'+pin-1, isa_irq); From patchwork Tue Jun 20 17:15:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF189EB64DC for ; Tue, 20 Jun 2023 17:17:55 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551992.861846 (Exim 4.92) (envelope-from ) id 1qBeyu-00077S-MN; Tue, 20 Jun 2023 17:17:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551992.861846; Tue, 20 Jun 2023 17:17:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeyu-00077E-J1; Tue, 20 Jun 2023 17:17:28 +0000 Received: by outflank-mailman (input) for mailman id 551992; Tue, 20 Jun 2023 17:17:26 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeys-0005iB-Kx for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 17:17:26 +0000 Received: from mail-yb1-xb32.google.com (mail-yb1-xb32.google.com [2607:f8b0:4864:20::b32]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 534de959-0f8e-11ee-b234-6b7b168915f2; Tue, 20 Jun 2023 19:17:25 +0200 (CEST) Received: by mail-yb1-xb32.google.com with SMTP id 3f1490d57ef6-bf5f41a87ceso1815317276.1 for ; Tue, 20 Jun 2023 10:17:25 -0700 (PDT) Received: from joel-Precision-7920-Tower.. ([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:23 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 534de959-0f8e-11ee-b234-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281444; x=1689873444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RM7XI3GANtEN3rKi5JobU5SJg3vOxg/6WaWdszBvqtQ=; b=RBZgYaRAHUdyrJqdHgfRRDvmbr/Pt4oWavppwOuem+MSRJw9IVQCa3XeKX6Tatn8UM cxn28siWSpZQYIrrxL6NJ5vBG2J6GZMJETQO6RuHpZJ7/9WNrbiokjq5EM8976YrVbwX FJK5M0sclB3l1CEwnIiEGFAmlw45h+kkxGaOlDiNQeKYwTf9zGJ+4CAHy+cnRgIHe0YI c2FTRIvKIRz6UBp1V7XQ4nb9kOHNWy7+eZboNej53/IOpy7LeOoT0WXH0XLBkB0XGKtP 8fr7SJegSvgz/ST+nUWAEqSjzL4agdCLaPYCLVaGsPeMykBwdrzZHbIINZkUtN9s4cq1 VXEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281444; x=1689873444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RM7XI3GANtEN3rKi5JobU5SJg3vOxg/6WaWdszBvqtQ=; b=AkOb6EXyqNTdEQTqeuOeKNsv51ddhWKdhxqd/3Ny2GxaohB0p9CK++xbL6I2Ogffpc XIj+kjTg2Tg8Eobmuv0DEScuFIcsFuNM0obRjmreKR2zErQP3mVBB6H2dVI3m3eLi3rx mwxuWycUNIOEPNvcvTnRkTvwJlefWWMClDIaUFkd9/Ui7NGEM26j59S9FPvJKPhLP1we F6aAOXHHCb2pyhxmAiQ3D5Tt9nIYS4E3wIQimeARyw30if/69M/DY0Nzsz2/7QDzWX1I sMZmymcqi69PJm+eAsAAFQwnmitDcajEyHEanTNcOF0a8L3SvyI+Z/JlhxE2P6vu8TNU /IvA== X-Gm-Message-State: AC+VfDwdrZSAdxDzjRa9EDKo4IFdPHo73X4JD3zZSdF9KHL1Pb0HYY2+ 6oc55EjH6GTb56Utif/EfOqBc+VffcvdFw== X-Google-Smtp-Source: ACHHUZ6BePx58VbyOSs7xi34QCqm4HRe1+CoYMXNRqAbD0+Tvtsm02zuBAtOpUE/HsTRFpQCs2tC7A== X-Received: by 2002:a25:9191:0:b0:b9e:7ec8:5d45 with SMTP id w17-20020a259191000000b00b9e7ec85d45mr9006708ybl.55.1687281444253; Tue, 20 Jun 2023 10:17:24 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Anthony PERARD Subject: [PATCH v2 07/12] hvmloader: allocate MMCONFIG area in the MMIO hole + minor code refactoring Date: Tue, 20 Jun 2023 13:15:47 -0400 Message-Id: <389d2cd465f27a32f7370e976cecd2eefdf827db.1687215890.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Much like normal PCI BARs or other chipset-specific memory-mapped resources, MMCONFIG area needs space in MMIO hole, so we must allocate it manually. The actual MMCONFIG size depends on a number of PCI buses available which should be covered by ECAM. Possible options are 64MB, 128MB and 256MB. As we are limited to the bus 0 currently, thus using lowest possible setting (64MB), #defined via PCI_MAX_MCFG_BUSES in hvmloader/config.h. When multiple PCI buses support for Xen will be implemented, PCI_MAX_MCFG_BUSES may be changed to calculation of the number of buses according to results of the PCI devices enumeration. The way to allocate MMCONFIG range in MMIO hole is similar to how other PCI BARs are allocated. The patch extends 'bars' structure to make it universal for any arbitrary BAR type -- either IO, MMIO, ROM or a chipset-specific resource. One important new field is addr_mask, which tells which bits of the base address can (should) be written. Different address types (ROM, MMIO BAR, PCIEXBAR) will have different addr_mask values. For every assignable BAR range we store its size, PCI device BDF (devfn actually) to which it belongs, BAR type (mem/io/mem64) and corresponding register offset in device PCI conf space. This way we can insert MMCONFIG entry into bars array in the same manner like for any other BARs. In this case, the devfn field will point to MCH PCI device and bar_reg will contain PCIEXBAR register offset. It will be assigned a slot in MMIO hole later in a very same way like for plain PCI BARs, with respect to its size alignment. Also, to reduce code complexity, all long mem/mem64 BAR flags checks are replaced by simple bars[i] field probing, eg.: - if ( (bar_reg == PCI_ROM_ADDRESS) || - ((bar_data & PCI_BASE_ADDRESS_SPACE) == - PCI_BASE_ADDRESS_SPACE_MEMORY) ) + if ( bars[i].is_mem ) Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/firmware/hvmloader/config.h | 5 ++ tools/firmware/hvmloader/pci.c | 123 +++++++++++++++++++++------- tools/firmware/hvmloader/pci_regs.h | 2 + 3 files changed, 102 insertions(+), 28 deletions(-) diff --git a/tools/firmware/hvmloader/config.h b/tools/firmware/hvmloader/config.h index de3bbed609..53a3300d6e 100644 --- a/tools/firmware/hvmloader/config.h +++ b/tools/firmware/hvmloader/config.h @@ -55,6 +55,11 @@ extern uint8_t ioapic_version; #define PCI_ISA_DEVFN 0x08 /* dev 1, fn 0 */ #define PCI_ISA_IRQ_MASK 0x0c20U /* ISA IRQs 5,10,11 are PCI connected */ #define PCI_ICH9_LPC_DEVFN 0xf8 /* dev 31, fn 0 */ +#define PCI_MCH_DEVFN 0 /* bus 0, dev 0, func 0 */ + +/* possible values are: 64, 128, 256 */ +#define PCI_MAX_MCFG_BUSES 64 + #define ACPI_TIS_HDR_ADDRESS 0xFED40F00UL diff --git a/tools/firmware/hvmloader/pci.c b/tools/firmware/hvmloader/pci.c index 8249f70806..1137387c43 100644 --- a/tools/firmware/hvmloader/pci.c +++ b/tools/firmware/hvmloader/pci.c @@ -157,9 +157,10 @@ static void class_specific_pci_device_setup(uint16_t vendor_id, void pci_setup(void) { - uint8_t is_64bar, using_64bar, bar64_relocate = 0; + uint8_t is_64bar, using_64bar, bar64_relocate = 0, is_mem; uint32_t devfn, bar_reg, cmd, bar_data, bar_data_upper; uint64_t base, bar_sz, bar_sz_upper, mmio_total = 0; + uint64_t addr_mask; uint16_t vendor_id, device_id; unsigned int bar, pin, link, isa_irq; int is_running_on_q35 = 0; @@ -172,10 +173,14 @@ void pci_setup(void) /* Create a list of device BARs in descending order of size. */ struct bars { - uint32_t is_64bar; uint32_t devfn; uint32_t bar_reg; uint64_t bar_sz; + uint64_t addr_mask; /* which bits of the base address can be written */ + uint32_t bar_data; /* initial value - BAR flags here */ + uint8_t is_64bar; + uint8_t is_mem; + uint8_t padding[2]; } *bars = (struct bars *)scratch_start; unsigned int i, nr_bars = 0; uint64_t mmio_hole_size = 0; @@ -280,13 +285,20 @@ void pci_setup(void) bar_reg = PCI_ROM_ADDRESS; bar_data = pci_readl(devfn, bar_reg); + + is_mem = !!(((bar_data & PCI_BASE_ADDRESS_SPACE) == + PCI_BASE_ADDRESS_SPACE_MEMORY) || + (bar_reg == PCI_ROM_ADDRESS)); + if ( bar_reg != PCI_ROM_ADDRESS ) { - is_64bar = !!((bar_data & (PCI_BASE_ADDRESS_SPACE | - PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == - (PCI_BASE_ADDRESS_SPACE_MEMORY | + is_64bar = !!(is_mem && + ((bar_data & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64)); pci_writel(devfn, bar_reg, ~0); + + addr_mask = is_mem ? PCI_BASE_ADDRESS_MEM_MASK + : PCI_BASE_ADDRESS_IO_MASK; } else { @@ -294,15 +306,15 @@ void pci_setup(void) pci_writel(devfn, bar_reg, (bar_data | PCI_ROM_ADDRESS_MASK) & ~PCI_ROM_ADDRESS_ENABLE); + + addr_mask = PCI_ROM_ADDRESS_MASK; } bar_sz = pci_readl(devfn, bar_reg); pci_writel(devfn, bar_reg, bar_data); if ( bar_reg != PCI_ROM_ADDRESS ) - bar_sz &= (((bar_data & PCI_BASE_ADDRESS_SPACE) == - PCI_BASE_ADDRESS_SPACE_MEMORY) ? - PCI_BASE_ADDRESS_MEM_MASK : - (PCI_BASE_ADDRESS_IO_MASK & 0xffff)); + bar_sz &= is_mem ? PCI_BASE_ADDRESS_MEM_MASK : + (PCI_BASE_ADDRESS_IO_MASK & 0xffff); else bar_sz &= PCI_ROM_ADDRESS_MASK; if (is_64bar) { @@ -316,6 +328,9 @@ void pci_setup(void) if ( bar_sz == 0 ) continue; + /* leave only memtype/enable bits etc */ + bar_data &= ~addr_mask; + for ( i = 0; i < nr_bars; i++ ) if ( bars[i].bar_sz < bar_sz ) break; @@ -323,14 +338,15 @@ void pci_setup(void) if ( i != nr_bars ) memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars)); - bars[i].is_64bar = is_64bar; - bars[i].devfn = devfn; - bars[i].bar_reg = bar_reg; - bars[i].bar_sz = bar_sz; + bars[i].is_64bar = is_64bar; + bars[i].is_mem = is_mem; + bars[i].devfn = devfn; + bars[i].bar_reg = bar_reg; + bars[i].bar_sz = bar_sz; + bars[i].addr_mask = addr_mask; + bars[i].bar_data = bar_data; - if ( ((bar_data & PCI_BASE_ADDRESS_SPACE) == - PCI_BASE_ADDRESS_SPACE_MEMORY) || - (bar_reg == PCI_ROM_ADDRESS) ) + if ( is_mem ) mmio_total += bar_sz; nr_bars++; @@ -358,6 +374,63 @@ void pci_setup(void) pci_devfn_decode_type[devfn] = PCI_COMMAND_MASTER; } + /* + * Calculate MMCONFIG area size and squeeze it into the bars array + * for assigning a slot in the MMIO hole + */ + if (is_running_on_q35) + { + /* disable PCIEXBAR decoding for now */ + pci_writel(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR, 0); + pci_writel(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR + 4, 0); + +#define PCIEXBAR_64_BUSES (2 << 1) +#define PCIEXBAR_128_BUSES (1 << 1) +#define PCIEXBAR_256_BUSES (0 << 1) +#define PCIEXBAR_ENABLE (1 << 0) + + switch (PCI_MAX_MCFG_BUSES) + { + case 64: + bar_data = PCIEXBAR_64_BUSES | PCIEXBAR_ENABLE; + bar_sz = MB(64); + break; + + case 128: + bar_data = PCIEXBAR_128_BUSES | PCIEXBAR_ENABLE; + bar_sz = MB(128); + break; + + case 256: + bar_data = PCIEXBAR_256_BUSES | PCIEXBAR_ENABLE; + bar_sz = MB(256); + break; + + default: + /* unsupported number of buses specified */ + BUG(); + } + + addr_mask = ~(bar_sz - 1); + + for ( i = 0; i < nr_bars; i++ ) + if ( bars[i].bar_sz < bar_sz ) + break; + + if ( i != nr_bars ) + memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars)); + + bars[i].is_mem = 1; + bars[i].devfn = PCI_MCH_DEVFN; + bars[i].bar_reg = PCI_MCH_PCIEXBAR; + bars[i].bar_sz = bar_sz; + bars[i].addr_mask = addr_mask; + bars[i].bar_data = bar_data; + + mmio_total += bar_sz; + nr_bars++; + } + if ( mmio_hole_size ) { uint64_t max_ram_below_4g = GB(4) - mmio_hole_size; @@ -492,10 +565,9 @@ void pci_setup(void) */ using_64bar = bars[i].is_64bar && bar64_relocate && (mmio_total > (mem_resource.max - mem_resource.base)); - bar_data = pci_readl(devfn, bar_reg); + bar_data = bars[i].bar_data; - if ( (bar_data & PCI_BASE_ADDRESS_SPACE) == - PCI_BASE_ADDRESS_SPACE_MEMORY ) + if ( bars[i].is_mem ) { /* Mapping high memory if PCI device is 64 bits bar */ if ( using_64bar ) { @@ -505,18 +577,15 @@ void pci_setup(void) if ( !pci_hi_mem_start ) pci_hi_mem_start = high_mem_resource.base; resource = &high_mem_resource; - bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK; - } + } else { resource = &mem_resource; - bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK; } mmio_total -= bar_sz; } else { resource = &io_resource; - bar_data &= ~PCI_BASE_ADDRESS_IO_MASK; } base = (resource->base + bar_sz - 1) & ~(uint64_t)(bar_sz - 1); @@ -538,7 +607,7 @@ void pci_setup(void) } } - bar_data |= (uint32_t)base; + bar_data |= (uint32_t) (base & bars[i].addr_mask); bar_data_upper = (uint32_t)(base >> 32); base += bar_sz; @@ -559,10 +628,8 @@ void pci_setup(void) devfn>>3, devfn&7, bar_reg, PRIllx_arg(bar_sz), bar_data_upper, bar_data); - - if ( (bar_reg == PCI_ROM_ADDRESS) || - ((bar_data & PCI_BASE_ADDRESS_SPACE) == - PCI_BASE_ADDRESS_SPACE_MEMORY) ) + + if ( bars[i].is_mem ) pci_devfn_decode_type[devfn] |= PCI_COMMAND_MEMORY; else pci_devfn_decode_type[devfn] |= PCI_COMMAND_IO; diff --git a/tools/firmware/hvmloader/pci_regs.h b/tools/firmware/hvmloader/pci_regs.h index 4d4dc0cd01..b9261ee2af 100644 --- a/tools/firmware/hvmloader/pci_regs.h +++ b/tools/firmware/hvmloader/pci_regs.h @@ -111,6 +111,8 @@ #define PCI_DEVICE_ID_INTEL_82441 0x1237 #define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 +#define PCI_MCH_PCIEXBAR 0x60 + #endif /* __HVMLOADER_PCI_REGS_H__ */ /* From patchwork Tue Jun 20 17:15:48 2023 Content-Type: text/plain; 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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:25 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 542214f4-0f8e-11ee-b234-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281446; x=1689873446; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W6n7UkNFBYZK+AuffqP9HBzXa1ya+3d/QBUvXRQbFCI=; b=r5JhHlD7JEcSljp6bqBMH7Os3GLHWYE2c3zb4auizeHvepM/3G3Xlf2oKW2nlVEHYH 5e81JK507vpiQX0d/WdDxIwV0mceFriEJJCP0c+pQwfk3Ca0k1fbw5/oMTtIWn5mm6R5 UVcaXE+9VELaWqgVPFwXixRbepznblrbBprO1OZxluVWBzdbJN8UKFt1osvLmy4Qa6aG 4IU2jUes4S9CGjo2fz+GfpVkBkqQAdCHon0kRXn7XgpEBdIU+BLMUUfgT1jR/XmZpzt4 uDyyL1Y872Qxw9Kb7n3/T9u1TIfjbZpfeA88V5yxoQMQA2A6cE5BGa8Cn6YYd6/gRYEH WnhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281446; x=1689873446; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W6n7UkNFBYZK+AuffqP9HBzXa1ya+3d/QBUvXRQbFCI=; b=bagvDyyiCK0gmC2JSgoPvy3P0JSrwRGS6Q8xmepqw5m/J4h/edeCqfoWYd9N9sYZei zVkgC4FmQ73wbzaer0nx/k75GiqpKL75xZLcaZixQjbyPFGFHMIU043bnV6eKrJxU7DG yVHWVvUJmaiSJkzGURYj4/On4r6enDmxt3G8V6o4kVJ74Ny5CX2oGr9j506SwD29LEZE i87xPtZg5jY1k4A9j3xgLEt0jEVX7QoOFxYtv1vLr2Z38VCHdbKz7bvsRktBc0Gf20rY /Z7INp2iAFQJf9vIvuP1ngX5OEFs/WEXhsAarrcG0c2AqeVDjvOS5B7mJxSN7VvJ/HBr tK8Q== X-Gm-Message-State: AC+VfDyKS/cVb2KTb1fFWSO4wq1S4LSkJgVUKLQCQEjdBgPOEDfZLgA0 Ixv6Jk4h/R4C+2HBobewxOiW8MO+isGCrQ== X-Google-Smtp-Source: ACHHUZ68QC9oB49thILBTGeZaENYOVn48+DUMt+IbjZtfNSwljGZxv+Qb3iD0g2PT+etPmH1FI2Wow== X-Received: by 2002:a25:8046:0:b0:bc4:5a65:1a4f with SMTP id a6-20020a258046000000b00bc45a651a4fmr10790263ybn.5.1687281445775; Tue, 20 Jun 2023 10:17:25 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Wei Liu , Anthony PERARD , Juergen Gross Subject: [PATCH v2 08/12] libxl: Q35 support (new option device_model_machine) Date: Tue, 20 Jun 2023 13:15:48 -0400 Message-Id: <2aaf3c01bb1e43384fa5e5e0c4583d586f0a1bfe.1687215890.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Provide a new domain config option to select the emulated machine type, device_model_machine. It has following possible values: - "i440" - i440 emulation (default) - "q35" - emulate a Q35 machine. By default, the storage interface is AHCI. Note that omitting device_model_machine parameter means i440 system by default, so the default behavior doesn't change for existing domain config files. Setting device_model_machine to "q35" sends '-machine q35,accel=xen' argument to QEMU. Unlike i440, there no separate machine type to enable/disable Xen platform device, it is controlled via a machine property only. See 'libxl: Xen Platform device support for Q35' patch for a detailed description. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/libs/light/libxl_dm.c | 20 ++++++++++++++------ tools/libs/light/libxl_types.idl | 8 ++++++++ tools/xl/xl_parse.c | 14 ++++++++++++++ 3 files changed, 36 insertions(+), 6 deletions(-) diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c index fc264a3a13..17bc2113e1 100644 --- a/tools/libs/light/libxl_dm.c +++ b/tools/libs/light/libxl_dm.c @@ -1809,13 +1809,21 @@ static int libxl__build_device_model_args_new(libxl__gc *gc, flexarray_append(dm_args, b_info->extra_pv[i]); break; case LIBXL_DOMAIN_TYPE_HVM: - if (!libxl_defbool_val(b_info->u.hvm.xen_platform_pci)) { - /* Switching here to the machine "pc" which does not add - * the xen-platform device instead of the default "xenfv" machine. - */ - machinearg = libxl__strdup(gc, "pc,accel=xen,suppress-vmdesc=on"); + if (b_info->device_model_machine == LIBXL_DEVICE_MODEL_MACHINE_Q35) { + if (!libxl_defbool_val(b_info->u.hvm.xen_platform_pci)) { + machinearg = libxl__sprintf(gc, "q35,accel=xen"); + } else { + machinearg = libxl__sprintf(gc, "q35,accel=xen,xen-platform-dev=on"); + } } else { - machinearg = libxl__strdup(gc, "xenfv,suppress-vmdesc=on"); + if (!libxl_defbool_val(b_info->u.hvm.xen_platform_pci)) { + /* Switching here to the machine "pc" which does not add + * the xen-platform device instead of the default "xenfv" machine. + */ + machinearg = libxl__strdup(gc, "pc,accel=xen,suppress-vmdesc=on"); + } else { + machinearg = libxl__strdup(gc, "xenfv,suppress-vmdesc=on"); + } } if (b_info->u.hvm.mmio_hole_memkb) { uint64_t max_ram_below_4g = (1ULL << 32) - diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl index c10292e0d7..b1aadae877 100644 --- a/tools/libs/light/libxl_types.idl +++ b/tools/libs/light/libxl_types.idl @@ -108,6 +108,13 @@ libxl_device_model_version = Enumeration("device_model_version", [ (2, "QEMU_XEN"), # Upstream based qemu-xen device model ]) +libxl_device_model_machine = Enumeration("device_model_machine", [ + (0, "UNKNOWN"), + (1, "I440"), + (2, "Q35"), + ]) + + libxl_console_type = Enumeration("console_type", [ (0, "UNKNOWN"), (1, "SERIAL"), @@ -575,6 +582,7 @@ libxl_domain_build_info = Struct("domain_build_info",[ ("device_model_ssidref", uint32), ("device_model_ssid_label", string), ("device_model_user", string), + ("device_model_machine", libxl_device_model_machine), # extra parameters pass directly to qemu, NULL terminated ("extra", libxl_string_list), diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c index 1f6f47daf4..e6fb7a409a 100644 --- a/tools/xl/xl_parse.c +++ b/tools/xl/xl_parse.c @@ -2689,6 +2689,20 @@ skip_usbdev: if (!xlu_cfg_get_long (config, "stubdomain_memory", &l, 0)) b_info->stubdomain_memkb = l * 1024; + if (!xlu_cfg_get_string (config, "device_model_machine", &buf, 0)) { + if (!strcmp(buf, "i440")) { + b_info->device_model_machine = LIBXL_DEVICE_MODEL_MACHINE_I440; + } else if (!strcmp(buf, "q35")) { + b_info->device_model_machine = LIBXL_DEVICE_MODEL_MACHINE_Q35; + } else { + fprintf(stderr, + "Unknown device_model_machine \"%s\" specified\n", buf); + exit(1); + } + } else { + b_info->device_model_machine = LIBXL_DEVICE_MODEL_MACHINE_UNKNOWN; + } + #define parse_extra_args(type) \ e = xlu_cfg_get_list_as_string_list(config, "device_model_args"#type, \ &b_info->extra##type, 0); \ From patchwork Tue Jun 20 17:15:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60B16EB64DB for ; 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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:26 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5507f960-0f8e-11ee-b234-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281447; x=1689873447; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=euxQjj1nka42h3IgnfVDkR/WuQVbd1+OBbuouObQPZw=; b=ULINpF4cSUf3E0vswpH5QAioshxNpdrmsaQInoUb8RunfkwL889I8OvlIM6qjWZCk4 uxiDLykMuYl0naI1OGQNjyxFVfeQp0u9H1iPwZtbnWD2pX3538vZsErT3Dk3Tp9pH+7L FAjy9doJWjWE9uzJVcS9FI5byrLrI0tVlqwr8Li+iM8t4S7aHz925xtqyz7Jx9ECpwtw FexVqL6CDjTeADqsEE2H4t00aYSyDfWyahSmsy+rbU939psvTHIqO1x4AZ3jM5nXfIPE uCq2I+i8KDo503efp04bp6AiiRaVXs7cvdJwZ5FBO3aTg3y77vtQfke+tj6WIhSUwOyi 1ujw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281447; x=1689873447; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=euxQjj1nka42h3IgnfVDkR/WuQVbd1+OBbuouObQPZw=; b=lma+31c3vFuN7Hzuo5WA6bloFNnQRh8U41SjonSPx98vLoW2bgRlP1Kg7K3dbU2DSV h5cTIvVecn2eZsP/DS9AVVxcJ6XbamWZ6R7dDJP0dzAjfTR7R4cAGC0L5aLHo9cxS04T aqRkEU6LhdahCzn5clOqqFB1IjBPUHgziHn1gcg+92lBeUjdQJqA4bZ2e2n7U/BVPMz/ UYaHaOihQuYOQPpuH9Zbwk+4Fri4Jsz45dQnLtjocjjNIaeWnOLzcbdMsXztsqGJhAUK 3RLtWGT4ttskH5Fm0OIUS6U5j7df3ZPxxALYyITlqBII8yhSuGti6jEUjrJjJnufcRz7 aZUA== X-Gm-Message-State: AC+VfDwiTfdZ/x25PNRQQAKSEfrenjLgyM37uDcdaOy6u27RrVbBaYZr 6WRuoD5wo3pEMvvuT0puuG2gzQ0508xrqg== X-Google-Smtp-Source: ACHHUZ5EB8KP3P9ZxnevN/zJy70NatbVfjPaFOUdV6sEz7ptY4/9L8nrO3fKDKVEOiFJsfGBavnyxg== X-Received: by 2002:a25:3620:0:b0:bc9:716d:19bf with SMTP id d32-20020a253620000000b00bc9716d19bfmr7782477yba.14.1687281447274; Tue, 20 Jun 2023 10:17:27 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Jan Beulich , Wei Liu , Anthony PERARD Subject: [PATCH v2 09/12] libacpi: build ACPI MCFG table if requested Date: Tue, 20 Jun 2023 13:15:49 -0400 Message-Id: <906595ebdc789e88715289ce48d306ae72e69fe1.1687215890.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 This adds construct_mcfg() function to libacpi which allows to build MCFG table for a given mmconfig_addr/mmconfig_len pair if the ACPI_HAS_MCFG flag was specified in acpi_config struct. The maximum bus number is calculated from mmconfig_len using MCFG_SIZE_TO_NUM_BUSES macro (1MByte of MMIO space per bus). Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/libacpi/acpi2_0.h | 21 ++++++++++++++++++++ tools/libacpi/build.c | 43 +++++++++++++++++++++++++++++++++++++++++ tools/libacpi/libacpi.h | 4 ++++ 3 files changed, 68 insertions(+) diff --git a/tools/libacpi/acpi2_0.h b/tools/libacpi/acpi2_0.h index 6dfa939a8c..02b0cf1098 100644 --- a/tools/libacpi/acpi2_0.h +++ b/tools/libacpi/acpi2_0.h @@ -442,6 +442,24 @@ struct acpi_20_slit { uint64_t localities; uint8_t entry[0]; }; +/* + * PCI Express Memory Mapped Configuration Description Table + */ +struct mcfg_range_entry { + uint64_t base_address; + uint16_t pci_segment; + uint8_t start_pci_bus_num; + uint8_t end_pci_bus_num; + uint32_t reserved; +}; + +struct acpi_mcfg { + struct acpi_header header; + uint8_t reserved[8]; + struct mcfg_range_entry entries[1]; +}; + +#define MCFG_SIZE_TO_NUM_BUSES(size) ((size) >> 20) /* * Table Signatures. @@ -458,6 +476,8 @@ struct acpi_20_slit { #define ACPI_2_0_WAET_SIGNATURE ASCII32('W','A','E','T') #define ACPI_2_0_SRAT_SIGNATURE ASCII32('S','R','A','T') #define ACPI_2_0_SLIT_SIGNATURE ASCII32('S','L','I','T') +#define ACPI_MCFG_SIGNATURE ASCII32('M','C','F','G') + /* * Table revision numbers. @@ -473,6 +493,7 @@ struct acpi_20_slit { #define ACPI_1_0_FADT_REVISION 0x01 #define ACPI_2_0_SRAT_REVISION 0x01 #define ACPI_2_0_SLIT_REVISION 0x01 +#define ACPI_1_0_MCFG_REVISION 0x01 #pragma pack () diff --git a/tools/libacpi/build.c b/tools/libacpi/build.c index 2f29863db1..fc029d18bf 100644 --- a/tools/libacpi/build.c +++ b/tools/libacpi/build.c @@ -295,6 +295,37 @@ static struct acpi_20_slit *construct_slit(struct acpi_ctxt *ctxt, return slit; } +static struct acpi_mcfg *construct_mcfg(struct acpi_ctxt *ctxt, + const struct acpi_config *config) +{ + struct acpi_mcfg *mcfg; + + /* Warning: this code expects that we have only one PCI segment */ + mcfg = ctxt->mem_ops.alloc(ctxt, sizeof(*mcfg), 16); + if (!mcfg) + return NULL; + + memset(mcfg, 0, sizeof(*mcfg)); + mcfg->header.signature = ACPI_MCFG_SIGNATURE; + mcfg->header.revision = ACPI_1_0_MCFG_REVISION; + fixed_strcpy(mcfg->header.oem_id, ACPI_OEM_ID); + fixed_strcpy(mcfg->header.oem_table_id, ACPI_OEM_TABLE_ID); + mcfg->header.oem_revision = ACPI_OEM_REVISION; + mcfg->header.creator_id = ACPI_CREATOR_ID; + mcfg->header.creator_revision = ACPI_CREATOR_REVISION; + mcfg->header.length = sizeof(*mcfg); + + mcfg->entries[0].base_address = config->mmconfig_addr; + mcfg->entries[0].pci_segment = 0; + mcfg->entries[0].start_pci_bus_num = 0; + mcfg->entries[0].end_pci_bus_num = + MCFG_SIZE_TO_NUM_BUSES(config->mmconfig_len) - 1; + + set_checksum(mcfg, offsetof(struct acpi_header, checksum), sizeof(*mcfg)); + + return mcfg;; +} + static int construct_passthrough_tables(struct acpi_ctxt *ctxt, unsigned long *table_ptrs, int nr_tables, @@ -342,6 +373,7 @@ static int construct_secondary_tables(struct acpi_ctxt *ctxt, struct acpi_20_hpet *hpet; struct acpi_20_waet *waet; struct acpi_20_tcpa *tcpa; + struct acpi_mcfg *mcfg; struct acpi_20_tpm2 *tpm2; unsigned char *ssdt; void *lasa; @@ -402,6 +434,17 @@ static int construct_secondary_tables(struct acpi_ctxt *ctxt, memcpy(ssdt, ssdt_laptop_slate, sizeof(ssdt_laptop_slate)); table_ptrs[nr_tables++] = ctxt->mem_ops.v2p(ctxt, ssdt); } + + /* MCFG */ + if ( config->table_flags & ACPI_HAS_MCFG ) + { + mcfg = construct_mcfg(ctxt, config); + if (!mcfg) + return -1; + + table_ptrs[nr_tables++] = ctxt->mem_ops.v2p(ctxt, mcfg); + } + /* TPM and its SSDT. */ if ( config->table_flags & ACPI_HAS_TPM ) { diff --git a/tools/libacpi/libacpi.h b/tools/libacpi/libacpi.h index deda39e5db..b4d3116ca5 100644 --- a/tools/libacpi/libacpi.h +++ b/tools/libacpi/libacpi.h @@ -27,6 +27,7 @@ #define ACPI_HAS_8042 (1<<13) #define ACPI_HAS_CMOS_RTC (1<<14) #define ACPI_HAS_SSDT_LAPTOP_SLATE (1<<15) +#define ACPI_HAS_MCFG (1<<16) struct xen_vmemrange; struct acpi_numa { @@ -89,6 +90,9 @@ struct acpi_config { uint32_t ioapic_base_address; uint16_t pci_isa_irq_mask; uint8_t ioapic_id; + + uint64_t mmconfig_addr; + uint32_t mmconfig_len; }; int acpi_build_tables(struct acpi_ctxt *ctxt, struct acpi_config *config); From patchwork Tue Jun 20 17:15:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3E80EB64D7 for ; Tue, 20 Jun 2023 17:17:51 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551997.861877 (Exim 4.92) (envelope-from ) id 1qBeyz-00087q-5U; Tue, 20 Jun 2023 17:17:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551997.861877; 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([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:28 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 55e2d089-0f8e-11ee-b234-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281448; x=1689873448; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3fjtno19HlqIKZlbtqkAAG6ggnFUVfYA4lZq6D4RFmU=; b=iIdMeU4y0VdO4JnA0H+pJgryhUUU5Hs0JZa7LVogJRMtTMQ3KmFElVEGGxaUU7IOOL Si11cySxP2h8+a7v7oOnB0qStxH1lyRyRm5JQEhHovVwbdGRRMrOM/mJ7uV9bBf1I0nv VFKFCLu1wCnO2l1Z0KfX5sKKkUyLZrfWCgn9Bcy0/CrrU8JJuJRL+jbHQSQNTk6+lvPe 28jKgvTsAO2VtaMVdH7CvUOyIyEE7g4fmVDYufhk5C3Kzi/j9sra83o5gMMUORNnwkm/ MW7GaMu/SDakwBIkSiwPwe8gOdLijkkxo0jf8L9tlsa57XPzBiILu53p56LiJNijm88i qdgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281448; x=1689873448; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3fjtno19HlqIKZlbtqkAAG6ggnFUVfYA4lZq6D4RFmU=; b=ZFkdBLoeaqOgnCAE+W39Hs+pTl5G9V+JhJo00X5Ce2YmY+MA8jJFnnLUqTcy+sxd32 pXU++1UzRq7KiF//7iBqZc2uK7GoXvSKAysnTwUBvInMLrzZNuyomfqCz9JjOAgxR4OD jYjXPKHd5fCSkE7poD+d9HzxjbJmdpZS0VVjqPO7Sjk8C2Phs4c8ZPNxWv4uuCMfrrO2 q5Y9hbYTuATGe/WgNGr9lAAMuVXwymZ4rItoOsmYjYShjC55gBUrHq8QZpcaP/6cCS1A lCvDu1c8HjPmg2avRnl70xPVUUBqcc4hf1kOTDOLmadhPBQeW61klZsT3imMVInOkLO4 6h4g== X-Gm-Message-State: AC+VfDwyE22d1YtTn2ON9pOigDfsQguvN7J2Di88ffrKA/L/naKDxks/ 3bJlbmlyrZCkQqe2ZSfQTmtmobhz4D+KMA== X-Google-Smtp-Source: ACHHUZ7dPxqtN7XNpJ+cQlQ2aT5wsLr5A17J5Y7tAF+5tcvPlSCLK2UFAuZAbT0eu3bkNE00SJhJCQ== X-Received: by 2002:a67:d087:0:b0:438:d4bd:f1f2 with SMTP id s7-20020a67d087000000b00438d4bdf1f2mr4795848vsi.22.1687281448728; Tue, 20 Jun 2023 10:17:28 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu , Anthony PERARD Subject: [PATCH v2 10/12] hvmloader: use libacpi to build MCFG table Date: Tue, 20 Jun 2023 13:15:50 -0400 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 This patch extends hvmloader_acpi_build_tables() with code which detects if MMCONFIG is available -- i.e. initialized and enabled (+we're running on Q35), obtains its base address and size and asks libacpi to build MCFG table for it via setting the flag ACPI_HAS_MCFG in a manner similar to other optional ACPI tables building. Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- tools/firmware/hvmloader/util.c | 70 +++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/tools/firmware/hvmloader/util.c b/tools/firmware/hvmloader/util.c index ea416ebe10..7a75c07467 100644 --- a/tools/firmware/hvmloader/util.c +++ b/tools/firmware/hvmloader/util.c @@ -782,6 +782,69 @@ int get_pc_machine_type(void) return machine_type; } +#define PCIEXBAR_ADDR_MASK_64MB (~((1ULL << 26) - 1)) +#define PCIEXBAR_ADDR_MASK_128MB (~((1ULL << 27) - 1)) +#define PCIEXBAR_ADDR_MASK_256MB (~((1ULL << 28) - 1)) +#define PCIEXBAR_LENGTH_BITS(reg) (((reg) >> 1) & 3) +#define PCIEXBAREN 1 + +static uint64_t mmconfig_get_base(void) +{ + uint64_t base; + uint32_t reg = pci_readl(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR); + + base = reg | (uint64_t) pci_readl(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR+4) << 32; + + switch (PCIEXBAR_LENGTH_BITS(reg)) + { + case 0: + base &= PCIEXBAR_ADDR_MASK_256MB; + break; + case 1: + base &= PCIEXBAR_ADDR_MASK_128MB; + break; + case 2: + base &= PCIEXBAR_ADDR_MASK_64MB; + break; + case 3: + BUG(); /* a reserved value encountered */ + } + + return base; +} + +static uint32_t mmconfig_get_size(void) +{ + uint32_t reg = pci_readl(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR); + + switch (PCIEXBAR_LENGTH_BITS(reg)) + { + case 0: return MB(256); + case 1: return MB(128); + case 2: return MB(64); + case 3: + BUG(); /* a reserved value encountered */ + } + + return 0; +} + +static uint32_t mmconfig_is_enabled(void) +{ + return pci_readl(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR) & PCIEXBAREN; +} + +static int is_mmconfig_used(void) +{ + if (get_pc_machine_type() == MACHINE_TYPE_Q35) + { + if (mmconfig_is_enabled() && mmconfig_get_base()) + return 1; + } + + return 0; +} + static void validate_hvm_info(struct hvm_info_table *t) { uint8_t *ptr = (uint8_t *)t; @@ -1022,6 +1085,13 @@ void hvmloader_acpi_build_tables(struct acpi_config *config, config->pci_hi_len = pci_hi_mem_end - pci_hi_mem_start; } + if ( is_mmconfig_used() ) + { + config->table_flags |= ACPI_HAS_MCFG; + config->mmconfig_addr = mmconfig_get_base(); + config->mmconfig_len = mmconfig_get_size(); + } + s = xenstore_read("platform/generation-id", "0:0"); if ( s ) { From patchwork Tue Jun 20 17:15:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61673EB64D7 for ; Tue, 20 Jun 2023 17:18:02 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.551998.861886 (Exim 4.92) (envelope-from ) id 1qBez0-0008Rd-JC; Tue, 20 Jun 2023 17:17:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 551998.861886; Tue, 20 Jun 2023 17:17:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBez0-0008R5-BS; Tue, 20 Jun 2023 17:17:34 +0000 Received: by outflank-mailman (input) for mailman id 551998; Tue, 20 Jun 2023 17:17:33 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBeyz-0005QM-3r for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 17:17:33 +0000 Received: from mail-yb1-xb29.google.com (mail-yb1-xb29.google.com [2607:f8b0:4864:20::b29]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 56b00e4c-0f8e-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 19:17:31 +0200 (CEST) Received: by mail-yb1-xb29.google.com with SMTP id 3f1490d57ef6-bad0c4f6f50so7245312276.1 for ; Tue, 20 Jun 2023 10:17:31 -0700 (PDT) Received: from joel-Precision-7920-Tower.. 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Signed-off-by: Alexey Gerasimenko Signed-off-by: Joel Upham --- docs/man/xl.cfg.5.pod.in | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in index 24ac927182..be61227313 100644 --- a/docs/man/xl.cfg.5.pod.in +++ b/docs/man/xl.cfg.5.pod.in @@ -2838,6 +2838,33 @@ you have existing guests then, depending on the nature of the guest Operating System, you may wish to force them to use the device model which they were installed with. +=item B + +Selects which chipset the device model should emulate for this +guest. + +Valid options are: + +=over 4 + +=item B<"i440"> + +Use i440 emulation (a default setting) + +=item B<"q35"> + +Use Q35/ICH9 emulation. This enables additional features for +PCIe device passthrough + +=back + +Note that omitting device_model_machine parameter means i440 system +by default, so the default behavior doesn't change for old domain +config files. + +It is recommended to install the guest OS from scratch to avoid issues +due to the emulated platform change. + =item B Override the path to the binary to be used as the device-model running in From patchwork Tue Jun 20 17:15:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Upham X-Patchwork-Id: 13286244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2FD3AEB64DD for ; Tue, 20 Jun 2023 17:17:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.552002.861897 (Exim 4.92) (envelope-from ) id 1qBez3-0000Ye-2l; Tue, 20 Jun 2023 17:17:37 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 552002.861897; Tue, 20 Jun 2023 17:17:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBez2-0000Y9-TX; Tue, 20 Jun 2023 17:17:36 +0000 Received: by outflank-mailman (input) for mailman id 552002; Tue, 20 Jun 2023 17:17:35 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qBez1-0005QM-47 for xen-devel@lists.xenproject.org; Tue, 20 Jun 2023 17:17:35 +0000 Received: from mail-yb1-xb2b.google.com (mail-yb1-xb2b.google.com [2607:f8b0:4864:20::b2b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 5758b775-0f8e-11ee-8611-37d641c3527e; Tue, 20 Jun 2023 19:17:32 +0200 (CEST) Received: by mail-yb1-xb2b.google.com with SMTP id 3f1490d57ef6-bacf685150cso4920969276.3 for ; Tue, 20 Jun 2023 10:17:32 -0700 (PDT) Received: from joel-Precision-7920-Tower.. ([24.53.71.1]) by smtp.gmail.com with ESMTPSA id f81-20020a25cf54000000b00bcc0f2e4f05sm461938ybg.59.2023.06.20.10.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 10:17:30 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 5758b775-0f8e-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1687281451; x=1689873451; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p0+IH6WutOOhss8a6x2jgwcV2LXw+L6iCti+oajsAV0=; b=R12VZbvVmViVHNuFRP0d8ysgoYTijNG9Dm9PqMQpio4eNeBCvyuInefSHdIn+uUFhP Tu6svVi9RoLuhymnDHSTc5owwsIbgdM+oBmFZBD0S2UtEXX/vT3pPy0z31Zq6XoNWBlZ ohwyrSfng1ANBezTIJWtHbBWKXuO4RYqso5JnwdSdETgBSNpz/5rSgsJsAe36slFowgf xWuP1xJZDCIfkUzYHZm6zJ9wwsrfYiV5gOaYMGFUCKOvFEhBjK35WX9ICqDJ0X6Px8za sqZXT+QfOoIpTfoI451s3puwqycegEbJgKk7JfiiH1aA45BZy1KXJrgX6GxCnSfA/+H7 G/4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687281451; x=1689873451; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p0+IH6WutOOhss8a6x2jgwcV2LXw+L6iCti+oajsAV0=; b=StmgAjKkx6BJGyWY3Tg+9UN1f7bfVQpAqX13NJtUwnD7/oNgWfrWMSu3dHjEXUizrL n9eVManrMphtF90U9V73k0mzKlxTHLsDYA42RgNdXwP0tQoffbAuPjioqCVLHrDaHNg1 TZyRQsH4+BwGUMlkasSxSbOFbnXY1sZYKZgvgkNlPAdrx90UXqD9q/MK4aV6pvqtYi+/ HtH423i4IXDG00nFjiZXNyS5b4YHEGNrlZKuVjjmjSYW0HQwf36oR81TxkuMDFseMLxd t+Dh12Lg1/Brwqdy8BVFtknYk6LFTANK0GMqVtJWs6CGhBEFKT1OUMwX4XUZu8Mqhbwu cawA== X-Gm-Message-State: AC+VfDy6ojnJIUIrC27kkGvGRI6tRMdAW5w3zBiQrZPxVUujlOxdGd8b DsXGCd2C92Zcv6xwoKL16P0mCEOan/YGqA== X-Google-Smtp-Source: ACHHUZ4OcSi/v7pNBl5g5dWsqt/1R98rs9PycPxVdap3h+BGz0V8h3JwT18jdLRU6sUQkmVbTLNoXQ== X-Received: by 2002:a5b:88e:0:b0:bc9:e58c:bfea with SMTP id e14-20020a5b088e000000b00bc9e58cbfeamr10556234ybq.16.1687281451157; Tue, 20 Jun 2023 10:17:31 -0700 (PDT) From: Joel Upham To: xen-devel@lists.xenproject.org Cc: Joel Upham , Wei Liu , Anthony PERARD , Juergen Gross Subject: [PATCH v2 12/12] libxl_dm: handle the new 6 port ahci controller Date: Tue, 20 Jun 2023 13:15:52 -0400 Message-Id: <7556e5b5ae930a7f331293f1a87c1e7f68e8a214.1687215890.git.jupham125@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 This patch adds support to allow for 6 emulated devices on a controller, and handling cdrom drives properly. This is not from the original patch series. Signed-off-by: Joel Upham --- tools/libs/light/libxl_dm.c | 40 ++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c index 17bc2113e1..792dbc4383 100644 --- a/tools/libs/light/libxl_dm.c +++ b/tools/libs/light/libxl_dm.c @@ -1937,29 +1937,51 @@ static int libxl__build_device_model_args_new(libxl__gc *gc, if (disks[i].is_cdrom) { const char *drive_id; - if (disk > 4) { + if (disk > 4 && b_info->device_model_machine == LIBXL_DEVICE_MODEL_MACHINE_I440) { LOGD(WARN, guest_domid, "Emulated CDROM can be only one of the first 4 disks.\n" "Disk %s will be available via PV drivers but not as an " "emulated disk.", disks[i].vdev); continue; + } else if (disk > 6 && + b_info->device_model_machine == LIBXL_DEVICE_MODEL_MACHINE_Q35) { + LOGD(WARN, guest_domid, "Emulated CDROM can be only one of the first 6 disks.\n" + "Disk %s will be available via PV drivers but not as an " + "emulated disk.", + disks[i].vdev); + continue; } + if (b_info->device_model_machine == LIBXL_DEVICE_MODEL_MACHINE_I440) { + drive_id = GCSPRINTF("ide-%i", dev_number); + drive = GCSPRINTF("if=none,readonly=on,id=%s", drive_id); - drive_id = GCSPRINTF("ide-%i", dev_number); - drive = GCSPRINTF("if=none,readonly=on,id=%s", drive_id); - - if (target_path) - drive = libxl__sprintf(gc, "%s,file=%s,format=%s", - drive, target_path, format); + if (target_path) + drive = libxl__sprintf(gc, "%s,file=%s,format=%s", + drive, target_path, format); - flexarray_vappend(dm_args, + flexarray_vappend(dm_args, "-drive", drive, "-device", GCSPRINTF("ide-cd,id=%s,drive=%s,bus=ide.%u,unit=%u", drive_id, drive_id, disk / 2, disk % 2), NULL); - continue; + continue; + } else { + drive_id = GCSPRINTF("sata-0-%i", dev_number); + drive = GCSPRINTF("if=none,readonly=on,id=%s", drive_id); + if (target_path) + drive = libxl__sprintf(gc, "%s,file=%s,format=%s", + drive, target_path, format); + + flexarray_vappend(dm_args, + "-drive", drive, + "-device", + GCSPRINTF("ide-cd,id=%s,drive=%s,bus=ide.0", + drive_id, drive_id), + NULL); + continue; + } } else { /* * Explicit sd disks are passed through as is.