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Wed, 21 Jun 2023 05:41:46 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([2401:4900:5305:4d9b:7b:d038:88c8:7461]) by smtp.googlemail.com with ESMTPSA id jw10-20020a170903278a00b001b50b933febsm3400256plb.238.2023.06.21.05.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jun 2023 05:41:45 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Mayuresh Chitale , =Atish Patra , Anup Patel , linux-riscv@lists.infradead.org Subject: [PATCH v4 1/1] riscv: mm: use svinval instructions instead of sfence.vma Date: Wed, 21 Jun 2023 18:11:33 +0530 Message-Id: <20230621124133.779572-2-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230621124133.779572-1-mchitale@ventanamicro.com> References: <20230621124133.779572-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230621_054147_317263_D0340F90 X-CRM114-Status: GOOD ( 14.53 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When svinval is supported the local_flush_tlb_page* functions would prefer to use the following sequence to optimize the tlb flushes instead of a simple sfence.vma: sfence.w.inval svinval.vma . . svinval.vma sfence.inval.ir The maximum number of consecutive svinval.vma instructions that can be executed in local_flush_tlb_page* functions is limited to PTRS_PER_PTE. This is required to avoid soft lockups and the approach is similar to that used in arm64. Signed-off-by: Mayuresh Chitale --- arch/riscv/mm/tlbflush.c | 62 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 56 insertions(+), 6 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index 77be59aadc73..ade0b5cf8b47 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -5,6 +5,12 @@ #include #include #include +#include +#include + +#define has_svinval() riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL) + +static unsigned long tlb_flush_all_threshold __read_mostly = PTRS_PER_PTE; static inline void local_flush_tlb_all_asid(unsigned long asid) { @@ -26,19 +32,63 @@ static inline void local_flush_tlb_page_asid(unsigned long addr, static inline void local_flush_tlb_range(unsigned long start, unsigned long size, unsigned long stride) { - if (size <= stride) - local_flush_tlb_page(start); - else + if ((size / stride) <= tlb_flush_all_threshold) { + if (has_svinval()) { + asm volatile(SFENCE_W_INVAL() ::: "memory"); + while (size) { + asm volatile(SINVAL_VMA(%0, zero) + : : "r" (start) : "memory"); + start += stride; + if (size > stride) + size -= stride; + else + size = 0; + } + asm volatile(SFENCE_INVAL_IR() ::: "memory"); + } else { + while (size) { + local_flush_tlb_page(start); + start += stride; + if (size > stride) + size -= stride; + else + size = 0; + } + } + } else { local_flush_tlb_all(); + } } static inline void local_flush_tlb_range_asid(unsigned long start, unsigned long size, unsigned long stride, unsigned long asid) { - if (size <= stride) - local_flush_tlb_page_asid(start, asid); - else + if ((size / stride) <= tlb_flush_all_threshold) { + if (has_svinval()) { + asm volatile(SFENCE_W_INVAL() ::: "memory"); + while (size) { + asm volatile(SINVAL_VMA(%0, %1) : : "r" (start), + "r" (asid) : "memory"); + start += stride; + if (size > stride) + size -= stride; + else + size = 0; + } + asm volatile(SFENCE_INVAL_IR() ::: "memory"); + } else { + while (size) { + local_flush_tlb_page_asid(start, asid); + start += stride; + if (size > stride) + size -= stride; + else + size = 0; + } + } + } else { local_flush_tlb_all_asid(asid); + } } static void __ipi_flush_tlb_all(void *info)