From patchwork Wed Jun 21 18:59:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 13287894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44447EB64DD for ; Wed, 21 Jun 2023 19:01:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231663AbjFUTBK (ORCPT ); Wed, 21 Jun 2023 15:01:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231634AbjFUTBI (ORCPT ); Wed, 21 Jun 2023 15:01:08 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60015193; Wed, 21 Jun 2023 12:01:05 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35LHuCGj014414; Wed, 21 Jun 2023 19:00:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=sO2ZxVVfZ3zPNA/y3HOFoZoblai6aytQdi00nfSiPfk=; b=oDdLi/Lz+oXUD7qF7ephhqnfEkZKnHC13gD3ra99oFfLYHUTWb2Rzs612zr5Oxz1ioKD K/lK7kzS5FDMujDAklwHuyA5pUKr5ZhV/nEOSlSOfaJFPoEoEcGtNOO8QxeB49b3yOEB iwYbsiqNq0c6wiZqRkgxZS1+Cn7nPsb88AWvY5H8dwt0qSB9EFGn0yzbiTn2jKX2sOPB oHLJBXhHmzBIaKERIBZ2aR4Xb+8na+nfUONRD98/mwM5JPRDHeZWm298BGkb5IOT8Bgb LynwlWb/M8F321U9GfWxSawCmCP2u13B99W4YmiYbj0xB6U6k3COsqD1Amc95COlktFP Zw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rc0sk10gm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2023 19:00:56 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35LJ0tAT031292 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2023 19:00:55 GMT Received: from hu-amelende-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 21 Jun 2023 12:00:55 -0700 From: Anjelique Melendez To: , , , , , , , CC: , , , , , , , Anjelique Melendez Subject: [PATCH 1/7] dt-bindings: soc: qcom: Add qcom-pbs bindings Date: Wed, 21 Jun 2023 11:59:45 -0700 Message-ID: <20230621185949.2068-2-quic_amelende@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230621185949.2068-1-quic_amelende@quicinc.com> References: <20230621185949.2068-1-quic_amelende@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1Cp1etGDSHFBpEL8P1lGRhrSt7VPbeHN X-Proofpoint-ORIG-GUID: 1Cp1etGDSHFBpEL8P1lGRhrSt7VPbeHN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-21_11,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 phishscore=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306210158 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add binding for the Qualcomm Programmable Boot Sequencer device. Signed-off-by: Anjelique Melendez --- .../bindings/soc/qcom/qcom-pbs.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom-pbs.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom-pbs.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom-pbs.yaml new file mode 100644 index 000000000000..0a89c334f95c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom-pbs.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom-pbs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. PBS + +maintainers: + - Anjelique Melendez + +description: | + Qualcomm PBS (programmable boot sequencer) supports triggering sequences + for clients upon request. + +properties: + compatible: + const: qcom,pbs + + reg: + description: | + Base address of the PBS peripheral. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pbs@7400 { + compatible = "qcom,pbs"; + reg = <0x7400>; + }; + }; From patchwork Wed Jun 21 18:59:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 13287896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AC32EB64D8 for ; Wed, 21 Jun 2023 19:01:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231661AbjFUTBZ (ORCPT ); Wed, 21 Jun 2023 15:01:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231751AbjFUTBU (ORCPT ); Wed, 21 Jun 2023 15:01:20 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4044C1BC1; Wed, 21 Jun 2023 12:01:14 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35LIhN49016783; Wed, 21 Jun 2023 19:01:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=4R2bJlHYDEGr4/mjxRpMwCImvTQm2+G87251Ne6eFSo=; b=GSaSH/F1BOW5jLut88bxvDtuw3Ko+T4kRq1ePI2p+n6M75H2rDimHUNdR4GQ1ftyFt8z GcKtLPcf9wsDgzd1G9Wzz5Z6BTEm4gnUkt5lc0nrU3zIFPQYQ9CwQCKYJEGBRoIlnHN5 lxzt6bjBRYpoganZgSGdBpcOYY4icGS+GOB+I/1dAkriFdosnm/CJw2OzPQEEzVpb/5a NzI0f9marJ64JC9Hkp6ZEBWcyR2jWQsTUK8YfE1HmuwBEroGZneQFgNqNgQyv83eBJB4 S5oOIx2NbBKujW/otdbpc32bEuPNfXrbcUOukRy6tBv4WVZODxDP3VGAJz1jB/KC/DlN 5g== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rbqkh25s0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2023 19:01:02 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35LJ11nh026648 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2023 19:01:01 GMT Received: from hu-amelende-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 21 Jun 2023 12:01:00 -0700 From: Anjelique Melendez To: , , , , , , , CC: , , , , , , , Anjelique Melendez Subject: [PATCH 2/7] dt-bindings: leds: leds-qcom-lpg: Add support for LUT through NVMEM devices Date: Wed, 21 Jun 2023 11:59:46 -0700 Message-ID: <20230621185949.2068-3-quic_amelende@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230621185949.2068-1-quic_amelende@quicinc.com> References: <20230621185949.2068-1-quic_amelende@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: n3BcHyTMgfqA6mNZSHifdpjiySY_VBFg X-Proofpoint-GUID: n3BcHyTMgfqA6mNZSHifdpjiySY_VBFg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-21_11,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=860 priorityscore=1501 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306210159 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update leds-qcom-lpg bindings to support LUT patterns through NVMEM devices. Signed-off-by: Anjelique Melendez --- .../bindings/leds/leds-qcom-lpg.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml index e6f1999cb22f..c9d53820bf83 100644 --- a/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml +++ b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml @@ -63,6 +63,31 @@ properties: - description: dtest line to attach - description: flags for the attachment + nvmem: + description: > + Phandle(s) of the nvmem device(s) to access the LUT stored in the SDAM module(s). + This property is required only when LUT mode is supported and the LUT pattern is + stored in SDAM modules instead of a LUT module. + minItems: 1 + maxItems: 2 + + nvmem-names: + description: > + The nvmem device name(s) for the SDAM module(s) where the LUT pattern data is stored. + This property is required only when LUT mode is supported with SDAM module instead of + LUT module. + minItems: 1 + items: + - const: lpg_chan_sdam + - const: lut_sdam + + qcom,pbs-client: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + Phandle of the PBS client used for sending the PBS trigger. This property is + required when LUT mode is supported and the LUT pattern is stored in a single + SDAM module instead of a LUT module. + multi-led: type: object $ref: leds-class-multicolor.yaml# @@ -191,4 +216,64 @@ examples: compatible = "qcom,pm8916-pwm"; #pwm-cells = <2>; }; + - | + #include + + led-controller { + compatible = "qcom,pm8350c-pwm"; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + nvmem-names = "lpg_chan_sdam" , "lut_sdam"; + nvmem = <&pmk8550_sdam_21 &pmk8550_sdam_22>; + + led@1 { + reg = <1>; + color = ; + label = "red"; + }; + + led@2 { + reg = <2>; + color = ; + label = "green"; + }; + + led@3 { + reg = <3>; + color = ; + label = "blue"; + }; + }; + - | + #include + + led-controller { + compatible = "qcom,pmi632-lpg"; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + nvmem-names = "lpg_chan_sdam"; + nvmem = <&pmi632_sdam7>; + qcom,pbs-client = <&pmi632_pbs_client3>; + + led@1 { + reg = <1>; + color = ; + label = "red"; + }; + + led@2 { + reg = <2>; + color = ; + label = "green"; + }; + + led@3 { + reg = <3>; + color = ; + label = "blue"; + }; + }; + ... From patchwork Wed Jun 21 18:59:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 13287900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 456F7EB64D8 for ; Wed, 21 Jun 2023 19:01:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231964AbjFUTB4 (ORCPT ); Wed, 21 Jun 2023 15:01:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231898AbjFUTBd (ORCPT ); Wed, 21 Jun 2023 15:01:33 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D4BB1FC1; Wed, 21 Jun 2023 12:01:20 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35LIEjpg030314; Wed, 21 Jun 2023 19:01:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=tfGDLaw5MlfukRUklNVDA/uBgUG4dkg2ztlkdQWeBgw=; b=TFtgdlu14oS6np3wtHjln6QLluqnj6Nvw4TH9F74E9GUV9zO7oi8CNYTHZovDem/aN0H QcLfF7A8Dzr/Lc7al8vPQdb5ZJvJI1RqW0dF7jzxohao6SFRY4iCGwhtP9h06dudb7NN PUTJPVJ3mYPCZlX45k/cIdEy6TefM8l9pnG9d49Pl/pGwF5GhQzPdm3JDYRPCQR4DW9o 8NHJE+FnjwdFuywFPSMIz5KU6b2us7NQk4Q8v78x0NQwmluNS5RC3NvCYNbyx8xjsm+z l/MMThQ6tqrMK91MOoqZM+qLtos4jGQpG5KpI/ylyXF5BsL84ia76KI7ijHlsOmXN1D4 zQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rbqjba5f7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2023 19:01:12 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35LJ12NF007285 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2023 19:01:02 GMT Received: from hu-amelende-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 21 Jun 2023 12:01:01 -0700 From: Anjelique Melendez To: , , , , , , , CC: , , , , , , , Anjelique Melendez Subject: [PATCH 3/7] soc: qcom: add QCOM PBS driver Date: Wed, 21 Jun 2023 11:59:47 -0700 Message-ID: <20230621185949.2068-4-quic_amelende@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230621185949.2068-1-quic_amelende@quicinc.com> References: <20230621185949.2068-1-quic_amelende@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Qiv6XvFsXAH3cYoGEtRi-ZAeKpvzCpsm X-Proofpoint-GUID: Qiv6XvFsXAH3cYoGEtRi-ZAeKpvzCpsm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-21_11,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306210159 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the Qualcomm PBS (Programmable Boot Sequencer) driver. The QCOM PBS driver supports configuring software PBS trigger events through PBS RAM on Qualcomm Technologies, Inc (QTI) PMICs. Signed-off-by: Anjelique Melendez --- drivers/soc/qcom/Kconfig | 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom-pbs.c | 343 ++++++++++++++++++++++++++++++ include/linux/soc/qcom/qcom-pbs.h | 36 ++++ 4 files changed, 389 insertions(+) create mode 100644 drivers/soc/qcom/qcom-pbs.c create mode 100644 include/linux/soc/qcom/qcom-pbs.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a491718f8064..226b668f4690 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -260,6 +260,15 @@ config QCOM_APR used by audio driver to configure QDSP6 ASM, ADM and AFE modules. +config QCOM_PBS + tristate "PBS trigger support for Qualcomm PMIC" + depends on SPMI + help + This driver supports configuring software programmable boot sequencer (PBS) + trigger event through PBS RAM on Qualcomm Technologies, Inc. PMICs. + This module provides the APIs to the client drivers that wants to send the + PBS trigger event to the PBS RAM. + config QCOM_ICC_BWMON tristate "QCOM Interconnect Bandwidth Monitor driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 0f43a88b4894..4e154af3877a 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -31,5 +31,6 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o +obj-$(CONFIG_QCOM_PBS) += qcom-pbs.o obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += ice.o diff --git a/drivers/soc/qcom/qcom-pbs.c b/drivers/soc/qcom/qcom-pbs.c new file mode 100644 index 000000000000..4a2bb7ff8031 --- /dev/null +++ b/drivers/soc/qcom/qcom-pbs.c @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define pr_fmt(fmt) "PBS: %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PBS_CLIENT_TRIG_CTL 0x42 +#define PBS_CLIENT_SW_TRIG_BIT BIT(7) +#define PBS_CLIENT_SCRATCH1 0x50 +#define PBS_CLIENT_SCRATCH2 0x51 + +static LIST_HEAD(pbs_dev_list); +static DEFINE_MUTEX(pbs_list_lock); + +struct pbs_dev { + struct device *dev; + struct device_node *dev_node; + struct regmap *regmap; + struct mutex lock; + struct list_head link; + + u32 base; +}; + +static int qcom_pbs_read(struct pbs_dev *pbs, u32 address, u8 *val) +{ + int ret; + + address += pbs->base; + ret = regmap_bulk_read(pbs->regmap, address, val, 1); + if (ret) + pr_err("Failed to read address=%#x sid=%#x ret=%d\n", + address, to_spmi_device(pbs->dev->parent)->usid, ret); + + return ret; +} + +static int qcom_pbs_write(struct pbs_dev *pbs, u16 address, u8 val) +{ + int ret; + + address += pbs->base; + ret = regmap_bulk_write(pbs->regmap, address, &val, 1); + if (ret < 0) + pr_err("Failed to write address=%#x sid=%#x ret=%d\n", + address, to_spmi_device(pbs->dev->parent)->usid, ret); + else + pr_debug("Wrote %#x to addr %#x\n", val, address); + + return ret; +} + +static int qcom_pbs_masked_write(struct pbs_dev *pbs, u16 address, u8 mask, u8 val) +{ + int ret; + + address += pbs->base; + ret = regmap_update_bits(pbs->regmap, address, mask, val); + if (ret < 0) + pr_err("Failed to write address=%#x ret=%d\n", address, ret); + else + pr_debug("Wrote %#x to addr %#x\n", val, address); + + return ret; +} + +static int qcom_pbs_wait_for_ack(struct pbs_dev *pbs, u8 bit_pos) +{ + u16 retries = 2000, delay = 1000; + int ret; + u8 val; + + while (retries--) { + ret = qcom_pbs_read(pbs, PBS_CLIENT_SCRATCH2, &val); + if (ret < 0) + return ret; + + if (val == 0xFF) { + /* PBS error - clear SCRATCH2 register */ + ret = qcom_pbs_write(pbs, PBS_CLIENT_SCRATCH2, 0); + if (ret < 0) + return ret; + + pr_err("NACK from PBS for bit %u\n", bit_pos); + return -EINVAL; + } + + if (val & BIT(bit_pos)) { + pr_debug("PBS sequence for bit %u executed!\n", bit_pos); + break; + } + + usleep_range(delay, delay + 100); + } + + if (!retries) { + pr_err("Timeout for PBS ACK/NACK for bit %u\n", bit_pos); + return -ETIMEDOUT; + } + + return 0; +} + +/** + * qcom_pbs_trigger_single_event() - Trigger PBS sequence without using bitmap. + * @pbs: Pointer to PBS device + * + * This function is used to trigger the PBS that is hooked on the + * SW_TRIGGER directly in PBS client. + * + * Return: 0 on success, < 0 on failure + */ +int qcom_pbs_trigger_single_event(struct pbs_dev *pbs) +{ + int ret = 0; + + if (IS_ERR_OR_NULL(pbs)) + return -EINVAL; + + mutex_lock(&pbs->lock); + ret = qcom_pbs_masked_write(pbs, PBS_CLIENT_TRIG_CTL, PBS_CLIENT_SW_TRIG_BIT, + PBS_CLIENT_SW_TRIG_BIT); + if (ret < 0) + pr_err("Failed to write register %x ret=%d\n", PBS_CLIENT_TRIG_CTL, ret); + mutex_unlock(&pbs->lock); + + return ret; +} +EXPORT_SYMBOL(qcom_pbs_trigger_single_event); + +/** + * qcom_pbs_trigger_event() - Trigger the PBS RAM sequence + * @pbs: Pointer to PBS device + * @bitmap: bitmap + * + * This function is used to trigger the PBS RAM sequence to be + * executed by the client driver. + * + * The PBS trigger sequence involves + * 1. setting the PBS sequence bit in PBS_CLIENT_SCRATCH1 + * 2. Initiating the SW PBS trigger + * 3. Checking the equivalent bit in PBS_CLIENT_SCRATCH2 for the + * completion of the sequence. + * 4. If PBS_CLIENT_SCRATCH2 == 0xFF, the PBS sequence failed to execute + * + * Returns: 0 on success, < 0 on failure + */ +int qcom_pbs_trigger_event(struct pbs_dev *pbs, u8 bitmap) +{ + u8 val, mask; + u16 bit_pos; + int ret; + + if (!bitmap) { + pr_err("Invalid bitmap passed by client\n"); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(pbs)) + return -EINVAL; + + mutex_lock(&pbs->lock); + ret = qcom_pbs_read(pbs, PBS_CLIENT_SCRATCH2, &val); + if (ret < 0) + goto out; + + if (val == 0xFF) { + /* PBS error - clear SCRATCH2 register */ + ret = qcom_pbs_write(pbs, PBS_CLIENT_SCRATCH2, 0); + if (ret < 0) + goto out; + } + + for (bit_pos = 0; bit_pos < 8; bit_pos++) { + if (bitmap & BIT(bit_pos)) { + /* + * Clear the PBS sequence bit position in + * PBS_CLIENT_SCRATCH2 mask register. + */ + ret = qcom_pbs_masked_write(pbs, PBS_CLIENT_SCRATCH2, BIT(bit_pos), 0); + if (ret < 0) + goto error; + + /* + * Set the PBS sequence bit position in + * PBS_CLIENT_SCRATCH1 register. + */ + val = mask = BIT(bit_pos); + ret = qcom_pbs_masked_write(pbs, PBS_CLIENT_SCRATCH1, mask, val); + if (ret < 0) + goto error; + + /* Initiate the SW trigger */ + val = mask = PBS_CLIENT_SW_TRIG_BIT; + ret = qcom_pbs_masked_write(pbs, PBS_CLIENT_TRIG_CTL, mask, val); + if (ret < 0) + goto error; + + ret = qcom_pbs_wait_for_ack(pbs, bit_pos); + if (ret < 0) + goto error; + + /* + * Clear the PBS sequence bit position in + * PBS_CLIENT_SCRATCH1 register. + */ + ret = qcom_pbs_masked_write(pbs, PBS_CLIENT_SCRATCH1, BIT(bit_pos), 0); + if (ret < 0) + goto error; + + /* + * Clear the PBS sequence bit position in + * PBS_CLIENT_SCRATCH2 mask register. + */ + ret = qcom_pbs_masked_write(pbs, PBS_CLIENT_SCRATCH2, BIT(bit_pos), 0); + if (ret < 0) + goto error; + } + } + +error: + /* Clear all the requested bitmap */ + ret = qcom_pbs_masked_write(pbs, PBS_CLIENT_SCRATCH1, bitmap, 0); + +out: + mutex_unlock(&pbs->lock); + + return ret; +} +EXPORT_SYMBOL(qcom_pbs_trigger_event); + +/** + * get_pbs_client_device() - Get the PBS device used by client + * @dev: Client device + * + * This function is used to get the PBS device that is being + * used by the client. + * + * Returns: pbs_dev on success, ERR_PTR on failure + */ +struct pbs_dev *get_pbs_client_device(struct device *dev) +{ + struct device_node *pbs_dev_node; + struct pbs_dev *pbs; + + pbs_dev_node = of_parse_phandle(dev->of_node, "qcom,pbs-client", 0); + if (!pbs_dev_node) { + pr_err("Missing qcom,pbs-client property\n"); + return ERR_PTR(-ENODEV); + } + + mutex_lock(&pbs_list_lock); + list_for_each_entry(pbs, &pbs_dev_list, link) { + if (pbs_dev_node == pbs->dev_node) { + of_node_put(pbs_dev_node); + mutex_unlock(&pbs_list_lock); + return pbs; + } + } + mutex_unlock(&pbs_list_lock); + + pr_debug("Unable to find PBS dev_node\n"); + of_node_put(pbs_dev_node); + return ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL(get_pbs_client_device); + +static int qcom_pbs_probe(struct platform_device *pdev) +{ + struct pbs_dev *pbs; + u32 val; + int ret; + + pbs = devm_kzalloc(&pdev->dev, sizeof(*pbs), GFP_KERNEL); + if (!pbs) + return -ENOMEM; + + pbs->dev = &pdev->dev; + pbs->dev_node = pdev->dev.of_node; + pbs->regmap = dev_get_regmap(pbs->dev->parent, NULL); + if (!pbs->regmap) { + dev_err(pbs->dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + ret = device_property_read_u32(pbs->dev, "reg", &val); + if (ret < 0) { + dev_err(pbs->dev, "Couldn't find reg, ret = %d\n", ret); + return ret; + } + + pbs->base = val; + mutex_init(&pbs->lock); + + platform_set_drvdata(pdev, pbs); + + mutex_lock(&pbs_list_lock); + list_add(&pbs->link, &pbs_dev_list); + mutex_unlock(&pbs_list_lock); + + return 0; +} + +static int qcom_pbs_remove(struct platform_device *pdev) +{ + struct pbs_dev *pbs = platform_get_drvdata(pdev); + + mutex_lock(&pbs_list_lock); + list_del(&pbs->link); + mutex_unlock(&pbs_list_lock); + + return 0; +} + +static const struct of_device_id qcom_pbs_match_table[] = { + { .compatible = "qcom,pbs" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_pbs_match_table); + +static struct platform_driver qcom_pbs_driver = { + .driver = { + .name = "qcom-pbs", + .of_match_table = qcom_pbs_match_table, + }, + .probe = qcom_pbs_probe, + .remove = qcom_pbs_remove, +}; +module_platform_driver(qcom_pbs_driver) + +MODULE_DESCRIPTION("QCOM PBS DRIVER"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:qcom-pbs"); diff --git a/include/linux/soc/qcom/qcom-pbs.h b/include/linux/soc/qcom/qcom-pbs.h new file mode 100644 index 000000000000..4b065951686a --- /dev/null +++ b/include/linux/soc/qcom/qcom-pbs.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _QCOM_PBS_H +#define _QCOM_PBS_H + +#include +#include + +struct device_node; +struct pbs_dev; + +#if IS_ENABLED(CONFIG_QCOM_PBS) +int qcom_pbs_trigger_event(struct pbs_dev *pbs, u8 bitmap); +int qcom_pbs_trigger_single_event(struct pbs_dev *pbs); +struct pbs_dev *get_pbs_client_device(struct device *client_dev); +#else +static inline int qcom_pbs_trigger_event(struct pbs_dev *pbs, u8 bitmap) +{ + return -ENODEV; +} + +static inline int qcom_pbs_trigger_single_event(struct pbs_dev *pbs) +{ + return -ENODEV; +} + +static inline struct pbs_dev *get_pbs_client_device(struct device *client_dev) +{ + return ERR_PTR(-ENODEV); +} +#endif + +#endif From patchwork Wed Jun 21 18:59:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 13287897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7303C001B3 for ; Wed, 21 Jun 2023 19:01:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231760AbjFUTBZ (ORCPT ); Wed, 21 Jun 2023 15:01:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231770AbjFUTBW (ORCPT ); Wed, 21 Jun 2023 15:01:22 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 254EC19AE; Wed, 21 Jun 2023 12:01:14 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35LHtnZ9025332; Wed, 21 Jun 2023 19:01:05 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=JNDvHrJcBwSNYnhKgx/HUiz9vMf3BUzZE8R70/ojfEg=; b=fj4Nz2VaBZm4X/jc50WsHCjRw1JMOifSnzpocp7k5ya/j+GUpkcs8mx4IYmDzTGeip88 oP7GtpDLChBXUOkUr7Zmu8vrrjb9yLqEi7z3oM7bkZGfX6a3v8XcjrCw6dMvQk8Zz7yR uRj6sPqELMsL2KDhv8tn4o+OfhTJNGxvUBrGzQ7u3NqdcUMeTHrm0qMaMVjlFQbcrLKc RHfaQvOtk776OknnWytBtJ2ldwphqRG3dhk3KV1/hCihqf8tfVENPOcYO+1elPEwqxlX 9zec+sZNjNFm1BtVQhZ/uJM6evPlnVpKHGoqkFsg3aYpU3Hv9hT/uKr6WQBA7vEjL2vO QA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rbvr1hkh9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2023 19:01:05 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35LJ140S007329 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Jun 2023 19:01:04 GMT Received: from hu-amelende-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 21 Jun 2023 12:01:03 -0700 From: Anjelique Melendez To: , , , , , , , CC: , , , , , , , Anjelique Melendez Subject: [PATCH 4/7] leds: rgb: leds-qcom-lpg: Add support for LUT pattern through single SDAM Date: Wed, 21 Jun 2023 11:59:48 -0700 Message-ID: <20230621185949.2068-5-quic_amelende@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230621185949.2068-1-quic_amelende@quicinc.com> References: <20230621185949.2068-1-quic_amelende@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: g_MJgLpG-jDzrOBTMgLJJ4-nH1LOop3x X-Proofpoint-ORIG-GUID: g_MJgLpG-jDzrOBTMgLJJ4-nH1LOop3x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-21_11,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306210158 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In some PMICs like pmi632, the LUT pattern and LPG configuration can be stored in a single SDAM module instead of LUT peripheral. This feature is called PPG. Add support for configuring and using LUT pattern from SDAM. Signed-off-by: Anjelique Melendez --- drivers/leds/rgb/leds-qcom-lpg.c | 307 ++++++++++++++++++++++++++++--- 1 file changed, 282 insertions(+), 25 deletions(-) diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c index 20469200961f..b60d920c67c4 100644 --- a/drivers/leds/rgb/leds-qcom-lpg.c +++ b/drivers/leds/rgb/leds-qcom-lpg.c @@ -8,12 +8,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #define LPG_SUBTYPE_REG 0x05 #define LPG_SUBTYPE_LPG 0x2 @@ -49,9 +51,25 @@ #define LPG_RESOLUTION_9BIT BIT(9) #define LPG_RESOLUTION_15BIT BIT(15) +#define PPG_MAX_LED_BRIGHTNESS 255 + #define LPG_MAX_M 7 #define LPG_MAX_PREDIV 6 +#define DEFAULT_TICK_DURATION_US 7800 +#define RAMP_STEP_DURATION(x) (((x) * 1000 / DEFAULT_TICK_DURATION_US) & 0xff) + +/* LPG common config settings for PPG */ +#define SDAM_REG_RAMP_STEP_DURATION 0x47 +#define SDAM_LUT_COUNT_MAX 64 + +/* LPG per channel config settings for PPG */ +#define SDAM_LUT_EN_OFFSET 0x0 +#define SDAM_PATTERN_CONFIG_OFFSET 0x1 +#define SDAM_END_INDEX_OFFSET 0x3 +#define SDAM_START_INDEX_OFFSET 0x4 +#define SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET 0x6 + struct lpg_channel; struct lpg_data; @@ -65,7 +83,12 @@ struct lpg_data; * @lut_base: base address of the LUT block (optional) * @lut_size: number of entries in the LUT block * @lut_bitmap: allocation bitmap for LUT entries - * @triled_base: base address of the TRILED block (optional) + * @pbs_dev: PBS client device + * @lpg_chan_nvmem: LPG nvmem peripheral device + * @pbs_en_bitmap: bitmap for tracking PBS triggers + * @lut_sdam_base: offset where LUT pattern begins in nvmem + * @ppg_en: Flag indicating whether PPG is enabled/used + * @triled_base: base address of the TRILED block (optional) * @triled_src: power-source for the TRILED * @triled_has_atc_ctl: true if there is TRI_LED_ATC_CTL register * @triled_has_src_sel: true if there is TRI_LED_SRC_SEL register @@ -86,6 +109,12 @@ struct lpg { u32 lut_size; unsigned long *lut_bitmap; + struct pbs_dev *pbs_dev; + struct nvmem_device *lpg_chan_nvmem; + unsigned long pbs_en_bitmap; + u32 lut_sdam_base; + bool ppg_en; + u32 triled_base; u32 triled_src; bool triled_has_atc_ctl; @@ -102,6 +131,8 @@ struct lpg { * @triled_mask: mask in TRILED to enable this channel * @lut_mask: mask in LUT to start pattern generator for this channel * @subtype: PMIC hardware block subtype + * @sdam_offset: Channel offset in LPG nvmem + * @lpg_idx: index of the channel * @in_use: channel is exposed to LED framework * @color: color of the LED attached to this channel * @dtest_line: DTEST line for output, or 0 if disabled @@ -113,6 +144,7 @@ struct lpg { * @pre_div_sel: divider selector of the reference clock * @pre_div_exp: exponential divider of the reference clock * @pwm_resolution_sel: pwm resolution selector + * @pattern_set: true when setting pattern * @ramp_enabled: duty cycle is driven by iterating over lookup table * @ramp_ping_pong: reverse through pattern, rather than wrapping to start * @ramp_oneshot: perform only a single pass over the pattern @@ -130,6 +162,8 @@ struct lpg_channel { unsigned int triled_mask; unsigned int lut_mask; unsigned int subtype; + u32 sdam_offset; + u32 lpg_idx; bool in_use; @@ -147,6 +181,7 @@ struct lpg_channel { unsigned int pre_div_exp; unsigned int pwm_resolution_sel; + bool pattern_set; bool ramp_enabled; bool ramp_ping_pong; bool ramp_oneshot; @@ -181,10 +216,12 @@ struct lpg_led { * struct lpg_channel_data - per channel initialization data * @base: base address for PWM channel registers * @triled_mask: bitmask for controlling this channel in TRILED + * @sdam_offset: Channel offset in LPG nvmem */ struct lpg_channel_data { unsigned int base; u8 triled_mask; + unsigned int sdam_offset; }; /** @@ -192,21 +229,87 @@ struct lpg_channel_data { * @lut_base: base address of LUT block * @lut_size: number of entries in LUT * @triled_base: base address of TRILED + * @lut_sdam_base: base address where LUT pattern begins in nvmem device * @triled_has_atc_ctl: true if there is TRI_LED_ATC_CTL register * @triled_has_src_sel: true if there is TRI_LED_SRC_SEL register * @num_channels: number of channels in LPG + * @nvmem_count: number of nvmems used for LUT and PPG config * @channels: list of channel initialization data */ struct lpg_data { unsigned int lut_base; unsigned int lut_size; unsigned int triled_base; + unsigned int lut_sdam_base; bool triled_has_atc_ctl; bool triled_has_src_sel; int num_channels; + int nvmem_count; const struct lpg_channel_data *channels; }; +static int lpg_sdam_write(struct lpg *lpg, u16 addr, u8 val) +{ + int rc; + + rc = nvmem_device_write(lpg->lpg_chan_nvmem, addr, 1, &val); + if (rc < 0) + dev_err(lpg->dev, "writing %u to SDAM addr %#x failed, rc=%d\n", + val, addr, rc); + + return rc > 0 ? 0 : rc; +} + +#define SDAM_REG_PBS_SEQ_EN 0x42 +#define PBS_SW_TRIG_BIT BIT(0) + +static int lpg_clear_pbs_trigger(struct lpg_channel *chan) +{ + int rc; + + clear_bit(chan->lpg_idx, &chan->lpg->pbs_en_bitmap); + if (!chan->lpg->pbs_en_bitmap) { + rc = lpg_sdam_write(chan->lpg, SDAM_REG_PBS_SEQ_EN, 0); + if (rc < 0) + return rc; + } + + return 0; +} + +static int lpg_set_pbs_trigger(struct lpg_channel *chan) +{ + int rc; + + if (!chan->lpg->pbs_en_bitmap) { + rc = lpg_sdam_write(chan->lpg, SDAM_REG_PBS_SEQ_EN, PBS_SW_TRIG_BIT); + if (rc < 0) + return rc; + + rc = qcom_pbs_trigger_event(chan->lpg->pbs_dev, PBS_SW_TRIG_BIT); + if (rc < 0) + return rc; + } + set_bit(chan->lpg_idx, &chan->lpg->pbs_en_bitmap); + + return 0; +} + +static void lpg_sdam_configure_triggers(struct lpg_channel *chan) +{ + if (!chan->lpg->ppg_en) + return; + + if (chan->enabled && chan->pattern_set) { + lpg_sdam_write(chan->lpg, SDAM_LUT_EN_OFFSET + chan->sdam_offset, 1); + lpg_set_pbs_trigger(chan); + chan->pattern_set = false; + } else { + lpg_sdam_write(chan->lpg, SDAM_LUT_EN_OFFSET + chan->sdam_offset, 0); + lpg_clear_pbs_trigger(chan); + } +} + static int triled_set(struct lpg *lpg, unsigned int mask, unsigned int enable) { /* Skip if we don't have a triled block */ @@ -217,6 +320,41 @@ static int triled_set(struct lpg *lpg, unsigned int mask, unsigned int enable) mask, enable); } +static int lpg_lut_store_sdam(struct lpg *lpg, struct led_pattern *pattern, + size_t len, unsigned int *lo_idx, unsigned int *hi_idx) +{ + u8 brightness; + u16 addr; + unsigned int idx; + int i, rc; + + if (len > SDAM_LUT_COUNT_MAX) { + dev_err(lpg->dev, "Pattern length (%zu) exceeds maximum pattern length (%d)\n", + len, SDAM_LUT_COUNT_MAX); + return -EINVAL; + } + + idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size, + 0, len, 0); + if (idx >= lpg->lut_size) + return -ENOSPC; + + for (i = 0; i < len; i++) { + brightness = pattern[i].brightness; + addr = lpg->lut_sdam_base + i + idx; + rc = lpg_sdam_write(lpg, addr, brightness); + if (rc < 0) + return rc; + } + + bitmap_set(lpg->lut_bitmap, idx, len); + + *lo_idx = idx; + *hi_idx = idx + len - 1; + + return 0; +} + static int lpg_lut_store(struct lpg *lpg, struct led_pattern *pattern, size_t len, unsigned int *lo_idx, unsigned int *hi_idx) { @@ -463,6 +601,26 @@ static void lpg_apply_pwm_value(struct lpg_channel *chan) #define LPG_PATTERN_CONFIG_PAUSE_HI BIT(1) #define LPG_PATTERN_CONFIG_PAUSE_LO BIT(0) +static void lpg_sdam_apply_lut_control(struct lpg_channel *chan) +{ + u8 val, conf = 0; + struct lpg *lpg = chan->lpg; + + if (!chan->ramp_oneshot) + conf |= LPG_PATTERN_CONFIG_REPEAT; + + lpg_sdam_write(lpg, SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET + chan->sdam_offset, 0); + lpg_sdam_write(lpg, SDAM_PATTERN_CONFIG_OFFSET + chan->sdam_offset, conf); + + lpg_sdam_write(lpg, SDAM_END_INDEX_OFFSET + chan->sdam_offset, chan->pattern_hi_idx); + lpg_sdam_write(lpg, SDAM_START_INDEX_OFFSET + chan->sdam_offset, chan->pattern_lo_idx); + + val = RAMP_STEP_DURATION(chan->ramp_tick_ms); + if (val > 0) + val--; + lpg_sdam_write(lpg, SDAM_REG_RAMP_STEP_DURATION, val); +} + static void lpg_apply_lut_control(struct lpg_channel *chan) { struct lpg *lpg = chan->lpg; @@ -476,6 +634,9 @@ static void lpg_apply_lut_control(struct lpg_channel *chan) if (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx) return; + if (lpg->ppg_en) + return lpg_sdam_apply_lut_control(chan); + hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, step); lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, step); @@ -632,7 +793,7 @@ static void lpg_brightness_set(struct lpg_led *led, struct led_classdev *cdev, } else { lpg_calc_freq(chan, NSEC_PER_MSEC); - duty = div_u64(brightness * chan->period, cdev->max_brightness); + duty = div_u64(brightness * chan->period, LPG_RESOLUTION_9BIT); lpg_calc_duty(chan, duty); chan->enabled = true; chan->ramp_enabled = false; @@ -643,6 +804,7 @@ static void lpg_brightness_set(struct lpg_led *led, struct led_classdev *cdev, triled_mask |= chan->triled_mask; lpg_apply(chan); + lpg_sdam_configure_triggers(chan); } /* Toggle triled lines */ @@ -775,7 +937,7 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, unsigned int lo_idx; unsigned int hi_idx; unsigned int i; - bool ping_pong = true; + bool ping_pong = false; int ret = -EINVAL; /* Hardware only support oneshot or indefinite loops */ @@ -837,16 +999,22 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, * If the specified pattern is a palindrome the ping pong mode is * enabled. In this scenario the delta_t of the middle entry (i.e. the * last in the programmed pattern) determines the "high pause". + * + * NVMEM devices supporting LUT do not support "low pause", "high pause" + * or "ping pong" */ /* Detect palindromes and use "ping pong" to reduce LUT usage */ - for (i = 0; i < len / 2; i++) { - brightness_a = pattern[i].brightness; - brightness_b = pattern[len - i - 1].brightness; - - if (brightness_a != brightness_b) { - ping_pong = false; - break; + if (lpg->lut_base) { + ping_pong = true; + for (i = 0; i < len / 2; i++) { + brightness_a = pattern[i].brightness; + brightness_b = pattern[len - i - 1].brightness; + + if (brightness_a != brightness_b) { + ping_pong = false; + break; + } } } @@ -860,14 +1028,21 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, * Validate that all delta_t in the pattern are the same, with the * exception of the middle element in case of ping_pong. */ - delta_t = pattern[1].delta_t; - for (i = 2; i < len; i++) { + if (lpg->ppg_en) { + i = 1; + delta_t = pattern[0].delta_t; + } else { + i = 2; + delta_t = pattern[1].delta_t; + } + + for (; i < len; i++) { if (pattern[i].delta_t != delta_t) { /* * Allow last entry in the full or shortened pattern to * specify hi pause. Reject other variations. */ - if (i != actual_len - 1) + if (i != actual_len - 1 || lpg->ppg_en) goto out_free_pattern; } } @@ -876,12 +1051,19 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, if (delta_t >= BIT(9)) goto out_free_pattern; - /* Find "low pause" and "high pause" in the pattern */ - lo_pause = pattern[0].delta_t; - hi_pause = pattern[actual_len - 1].delta_t; + /* Find "low pause" and "high pause" in the pattern if not an NVMEM device*/ + if (!lpg->ppg_en) { + lo_pause = pattern[0].delta_t; + hi_pause = pattern[actual_len - 1].delta_t; + } mutex_lock(&lpg->lock); - ret = lpg_lut_store(lpg, pattern, actual_len, &lo_idx, &hi_idx); + + if (lpg->ppg_en) + ret = lpg_lut_store_sdam(lpg, pattern, actual_len, &lo_idx, &hi_idx); + else + ret = lpg_lut_store(lpg, pattern, actual_len, &lo_idx, &hi_idx); + if (ret < 0) goto out_unlock; @@ -897,6 +1079,8 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, chan->pattern_lo_idx = lo_idx; chan->pattern_hi_idx = hi_idx; + + chan->pattern_set = lpg->ppg_en; } out_unlock: @@ -1190,8 +1374,8 @@ static int lpg_add_led(struct lpg *lpg, struct device_node *np) cdev->brightness_set_blocking = lpg_brightness_mc_set; cdev->blink_set = lpg_blink_mc_set; - /* Register pattern accessors only if we have a LUT block */ - if (lpg->lut_base) { + /* Register pattern accessors if we have a LUT block or when using PPG */ + if (lpg->lut_base || lpg->ppg_en) { cdev->pattern_set = lpg_pattern_mc_set; cdev->pattern_clear = lpg_pattern_mc_clear; } @@ -1204,15 +1388,19 @@ static int lpg_add_led(struct lpg *lpg, struct device_node *np) cdev->brightness_set_blocking = lpg_brightness_single_set; cdev->blink_set = lpg_blink_single_set; - /* Register pattern accessors only if we have a LUT block */ - if (lpg->lut_base) { + /* Register pattern accessors if we have a LUT block or when using PPG */ + if (lpg->lut_base || lpg->ppg_en) { cdev->pattern_set = lpg_pattern_single_set; cdev->pattern_clear = lpg_pattern_single_clear; } } cdev->default_trigger = of_get_property(np, "linux,default-trigger", NULL); - cdev->max_brightness = LPG_RESOLUTION_9BIT - 1; + + if (lpg->ppg_en) + cdev->max_brightness = PPG_MAX_LED_BRIGHTNESS; + else + cdev->max_brightness = LPG_RESOLUTION_9BIT - 1; if (!of_property_read_string(np, "default-state", &state) && !strcmp(state, "on")) @@ -1253,6 +1441,8 @@ static int lpg_init_channels(struct lpg *lpg) chan->base = data->channels[i].base; chan->triled_mask = data->channels[i].triled_mask; chan->lut_mask = BIT(i); + chan->sdam_offset = data->channels[i].sdam_offset; + chan->lpg_idx = i; regmap_read(lpg->map, chan->base + LPG_SUBTYPE_REG, &chan->subtype); } @@ -1299,10 +1489,13 @@ static int lpg_init_lut(struct lpg *lpg) { const struct lpg_data *data = lpg->data; - if (!data->lut_base) + if (data->lut_base) + lpg->lut_base = data->lut_base; + else if (lpg->ppg_en) + lpg->lut_sdam_base = data->lut_sdam_base; + else return 0; - lpg->lut_base = data->lut_base; lpg->lut_size = data->lut_size; lpg->lut_bitmap = devm_bitmap_zalloc(lpg->dev, lpg->lut_size, GFP_KERNEL); @@ -1312,6 +1505,60 @@ static int lpg_init_lut(struct lpg *lpg) return 0; } +static int lpg_parse_sdam(struct lpg *lpg) +{ + int rc = 0; + + if (lpg->data->nvmem_count == 0) + return 0; + + /* get the nvmem device for LPG/LUT config */ + lpg->lpg_chan_nvmem = devm_nvmem_device_get(lpg->dev, "lpg_chan_sdam"); + if (IS_ERR(lpg->lpg_chan_nvmem)) { + rc = PTR_ERR(lpg->lpg_chan_nvmem); + if (rc != -EPROBE_DEFER) + dev_err(lpg->dev, "Failed to get nvmem device, rc=%d\n", rc); + return rc; + } + + lpg->pbs_dev = get_pbs_client_device(lpg->dev); + if (IS_ERR(lpg->pbs_dev)) { + rc = PTR_ERR(lpg->pbs_dev); + if (rc != -EPROBE_DEFER) + dev_err(lpg->dev, "Failed to get PBS client device, rc=%d\n", rc); + return rc; + } + + lpg->ppg_en = true; + + return rc; +} + +static int lpg_init_sdam(struct lpg *lpg) +{ + struct lpg_channel *chan; + int i, rc; + + if (!lpg->ppg_en) + return 0; + + for (i = 0; i < lpg->num_channels; i++) { + chan = &lpg->channels[i]; + if (chan->sdam_offset) { + rc = lpg_sdam_write(lpg, SDAM_LUT_EN_OFFSET + chan->sdam_offset, 0); + if (rc < 0) + break; + + rc = lpg_sdam_write(lpg, + SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET + chan->sdam_offset, 0); + if (rc < 0) + break; + } + } + + return rc; +} + static int lpg_probe(struct platform_device *pdev) { struct device_node *np; @@ -1348,6 +1595,14 @@ static int lpg_probe(struct platform_device *pdev) if (ret < 0) return ret; + ret = lpg_parse_sdam(lpg); + if (ret < 0) + return ret; + + ret = lpg_init_sdam(lpg); + if (ret < 0) + return ret; + ret = lpg_init_lut(lpg); if (ret < 0) return ret; @@ -1363,7 +1618,9 @@ static int lpg_probe(struct platform_device *pdev) for (i = 0; i < lpg->num_channels; i++) lpg_apply_dtest(&lpg->channels[i]); - return lpg_add_pwm(lpg); + ret = lpg_add_pwm(lpg); + + return ret; } static int lpg_remove(struct platform_device *pdev) From patchwork Wed Jun 21 18:59:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 13287899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58452C001B3 for ; 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Wed, 21 Jun 2023 12:01:04 -0700 From: Anjelique Melendez To: , , , , , , , CC: , , , , , , , Anjelique Melendez Subject: [PATCH 5/7] leds: rgb: leds-qcom-lpg: Update PMI632 lpg_data to support PPG Date: Wed, 21 Jun 2023 11:59:49 -0700 Message-ID: <20230621185949.2068-6-quic_amelende@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230621185949.2068-1-quic_amelende@quicinc.com> References: <20230621185949.2068-1-quic_amelende@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: R5d7VO1bbrF4Djl3Hf6Gqxy4lL-PSibR X-Proofpoint-GUID: R5d7VO1bbrF4Djl3Hf6Gqxy4lL-PSibR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-21_11,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 mlxlogscore=961 malwarescore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306210159 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update the pmi632 lpg_data struct so that pmi632 devices use PPG for LUT pattern. Signed-off-by: Anjelique Melendez --- drivers/leds/rgb/leds-qcom-lpg.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c index b60d920c67c4..ac814a509781 100644 --- a/drivers/leds/rgb/leds-qcom-lpg.c +++ b/drivers/leds/rgb/leds-qcom-lpg.c @@ -1679,11 +1679,15 @@ static const struct lpg_data pm8994_lpg_data = { static const struct lpg_data pmi632_lpg_data = { .triled_base = 0xd000, + .lut_size = 64, + .lut_sdam_base = 0x80, + .nvmem_count = 1, + .num_channels = 5, .channels = (const struct lpg_channel_data[]) { - { .base = 0xb300, .triled_mask = BIT(7) }, - { .base = 0xb400, .triled_mask = BIT(6) }, - { .base = 0xb500, .triled_mask = BIT(5) }, + { .base = 0xb300, .triled_mask = BIT(7), .sdam_offset = 0x48 }, + { .base = 0xb400, .triled_mask = BIT(6), .sdam_offset = 0x56 }, + { .base = 0xb500, .triled_mask = BIT(5), .sdam_offset = 0x64 }, { .base = 0xb600 }, { .base = 0xb700 }, }, From patchwork Wed Jun 21 18:59:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 13287898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CF2FEB64DC for ; Wed, 21 Jun 2023 19:01:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231867AbjFUTBa (ORCPT ); Wed, 21 Jun 2023 15:01:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231799AbjFUTBY (ORCPT ); Wed, 21 Jun 2023 15:01:24 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C3D019AF; Wed, 21 Jun 2023 12:01:15 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35LHtGD4024028; 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Wed, 21 Jun 2023 19:01:06 GMT Received: from hu-amelende-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 21 Jun 2023 12:01:05 -0700 From: Anjelique Melendez To: , , , , , , , CC: , , , , , , , Anjelique Melendez , Guru Das Srinagesh Subject: [PATCH 6/7] leds: rgb: leds-qcom-lpg: Support two-nvmem PPG Scheme Date: Wed, 21 Jun 2023 11:59:50 -0700 Message-ID: <20230621185949.2068-7-quic_amelende@quicinc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230621185949.2068-1-quic_amelende@quicinc.com> References: <20230621185949.2068-1-quic_amelende@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XEpbdcmkysnXx3maq5-r_Vxnn9cpv5GE X-Proofpoint-ORIG-GUID: XEpbdcmkysnXx3maq5-r_Vxnn9cpv5GE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-21_11,2023-06-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 mlxlogscore=999 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306210158 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On PMICs such as PM8350C, the lookup table containing the pattern data is stored in a separate nvmem device from the one where the per-channel data is stored. Add support for two separate nvmems to handle this case while maintaining backward compatibility for those targets that use only a single nvmem device. Signed-off-by: Guru Das Srinagesh Signed-off-by: Anjelique Melendez --- drivers/leds/rgb/leds-qcom-lpg.c | 112 ++++++++++++++++++++++++------- 1 file changed, 89 insertions(+), 23 deletions(-) diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c index ac814a509781..273cb81260e7 100644 --- a/drivers/leds/rgb/leds-qcom-lpg.c +++ b/drivers/leds/rgb/leds-qcom-lpg.c @@ -60,6 +60,7 @@ #define RAMP_STEP_DURATION(x) (((x) * 1000 / DEFAULT_TICK_DURATION_US) & 0xff) /* LPG common config settings for PPG */ +#define SDAM_START_BASE 0x40 #define SDAM_REG_RAMP_STEP_DURATION 0x47 #define SDAM_LUT_COUNT_MAX 64 @@ -69,6 +70,8 @@ #define SDAM_END_INDEX_OFFSET 0x3 #define SDAM_START_INDEX_OFFSET 0x4 #define SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET 0x6 +#define SDAM_PAUSE_HI_MULTIPLIER_OFFSET 0x8 +#define SDAM_PAUSE_LO_MULTIPLIER_OFFSET 0x9 struct lpg_channel; struct lpg_data; @@ -85,7 +88,9 @@ struct lpg_data; * @lut_bitmap: allocation bitmap for LUT entries * @pbs_dev: PBS client device * @lpg_chan_nvmem: LPG nvmem peripheral device + * @lut_nvmem: LUT nvmem peripheral device * @pbs_en_bitmap: bitmap for tracking PBS triggers + * @nvmem_count: number of nvmems used for LUT and PPG config * @lut_sdam_base: offset where LUT pattern begins in nvmem * @ppg_en: Flag indicating whether PPG is enabled/used * @triled_base: base address of the TRILED block (optional) @@ -111,7 +116,9 @@ struct lpg { struct pbs_dev *pbs_dev; struct nvmem_device *lpg_chan_nvmem; + struct nvmem_device *lut_nvmem; unsigned long pbs_en_bitmap; + unsigned int nvmem_count; u32 lut_sdam_base; bool ppg_en; @@ -261,6 +268,8 @@ static int lpg_sdam_write(struct lpg *lpg, u16 addr, u8 val) } #define SDAM_REG_PBS_SEQ_EN 0x42 +#define SDAM_PBS_TRIG_SET 0xe5 +#define SDAM_PBS_TRIG_CLR 0xe6 #define PBS_SW_TRIG_BIT BIT(0) static int lpg_clear_pbs_trigger(struct lpg_channel *chan) @@ -272,6 +281,12 @@ static int lpg_clear_pbs_trigger(struct lpg_channel *chan) rc = lpg_sdam_write(chan->lpg, SDAM_REG_PBS_SEQ_EN, 0); if (rc < 0) return rc; + + if (chan->lpg->nvmem_count == 2) { + rc = lpg_sdam_write(chan->lpg, SDAM_PBS_TRIG_CLR, PBS_SW_TRIG_BIT); + if (rc < 0) + return rc; + } } return 0; @@ -286,9 +301,15 @@ static int lpg_set_pbs_trigger(struct lpg_channel *chan) if (rc < 0) return rc; - rc = qcom_pbs_trigger_event(chan->lpg->pbs_dev, PBS_SW_TRIG_BIT); - if (rc < 0) - return rc; + if (chan->lpg->nvmem_count == 1) { + rc = qcom_pbs_trigger_event(chan->lpg->pbs_dev, PBS_SW_TRIG_BIT); + if (rc < 0) + return rc; + } else { + rc = lpg_sdam_write(chan->lpg, SDAM_PBS_TRIG_SET, PBS_SW_TRIG_BIT); + if (rc < 0) + return rc; + } } set_bit(chan->lpg_idx, &chan->lpg->pbs_en_bitmap); @@ -342,7 +363,12 @@ static int lpg_lut_store_sdam(struct lpg *lpg, struct led_pattern *pattern, for (i = 0; i < len; i++) { brightness = pattern[i].brightness; addr = lpg->lut_sdam_base + i + idx; - rc = lpg_sdam_write(lpg, addr, brightness); + + if (lpg->nvmem_count == 1) + rc = lpg_sdam_write(lpg, addr, brightness); + else + rc = nvmem_device_write(lpg->lut_nvmem, addr, 1, &brightness); + if (rc < 0) return rc; } @@ -601,24 +627,48 @@ static void lpg_apply_pwm_value(struct lpg_channel *chan) #define LPG_PATTERN_CONFIG_PAUSE_HI BIT(1) #define LPG_PATTERN_CONFIG_PAUSE_LO BIT(0) +static u8 lpg_get_sdam_lut_idx(struct lpg_channel *chan, u8 idx) +{ + if (chan->lpg->nvmem_count == 2) + return chan->lpg->lut_sdam_base - SDAM_START_BASE + idx; + return idx; +} + static void lpg_sdam_apply_lut_control(struct lpg_channel *chan) { u8 val, conf = 0; + unsigned int hi_pause, lo_pause; struct lpg *lpg = chan->lpg; + hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, chan->ramp_tick_ms); + lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, chan->ramp_tick_ms); + if (!chan->ramp_oneshot) conf |= LPG_PATTERN_CONFIG_REPEAT; + if (chan->ramp_hi_pause_ms && lpg->nvmem_count != 1) + conf |= LPG_PATTERN_CONFIG_PAUSE_HI; + if (chan->ramp_lo_pause_ms && lpg->nvmem_count != 1) + conf |= LPG_PATTERN_CONFIG_PAUSE_LO; lpg_sdam_write(lpg, SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET + chan->sdam_offset, 0); lpg_sdam_write(lpg, SDAM_PATTERN_CONFIG_OFFSET + chan->sdam_offset, conf); - lpg_sdam_write(lpg, SDAM_END_INDEX_OFFSET + chan->sdam_offset, chan->pattern_hi_idx); - lpg_sdam_write(lpg, SDAM_START_INDEX_OFFSET + chan->sdam_offset, chan->pattern_lo_idx); + val = lpg_get_sdam_lut_idx(chan, chan->pattern_hi_idx); + lpg_sdam_write(lpg, SDAM_END_INDEX_OFFSET + chan->sdam_offset, val); + + val = lpg_get_sdam_lut_idx(chan, chan->pattern_lo_idx); + lpg_sdam_write(lpg, SDAM_START_INDEX_OFFSET + chan->sdam_offset, val); val = RAMP_STEP_DURATION(chan->ramp_tick_ms); if (val > 0) val--; lpg_sdam_write(lpg, SDAM_REG_RAMP_STEP_DURATION, val); + + if (lpg->nvmem_count != 1) { + lpg_sdam_write(lpg, SDAM_PAUSE_HI_MULTIPLIER_OFFSET + chan->sdam_offset, hi_pause); + lpg_sdam_write(lpg, SDAM_PAUSE_LO_MULTIPLIER_OFFSET + chan->sdam_offset, lo_pause); + } + } static void lpg_apply_lut_control(struct lpg_channel *chan) @@ -1000,8 +1050,8 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, * enabled. In this scenario the delta_t of the middle entry (i.e. the * last in the programmed pattern) determines the "high pause". * - * NVMEM devices supporting LUT do not support "low pause", "high pause" - * or "ping pong" + * All NVMEM devices supporting LUT do not support "ping pong" + * Single NVMEM devices supporting LUT do not support "low pause" and "high pause" */ /* Detect palindromes and use "ping pong" to reduce LUT usage */ @@ -1028,7 +1078,7 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, * Validate that all delta_t in the pattern are the same, with the * exception of the middle element in case of ping_pong. */ - if (lpg->ppg_en) { + if (lpg->nvmem_count == 1) { i = 1; delta_t = pattern[0].delta_t; } else { @@ -1042,7 +1092,7 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, * Allow last entry in the full or shortened pattern to * specify hi pause. Reject other variations. */ - if (i != actual_len - 1 || lpg->ppg_en) + if (i != actual_len - 1 || lpg->nvmem_count == 1) goto out_free_pattern; } } @@ -1051,8 +1101,8 @@ static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern, if (delta_t >= BIT(9)) goto out_free_pattern; - /* Find "low pause" and "high pause" in the pattern if not an NVMEM device*/ - if (!lpg->ppg_en) { + /* Find "low pause" and "high pause" in the pattern if not a single NVMEM device*/ + if (lpg->nvmem_count != 1) { lo_pause = pattern[0].delta_t; hi_pause = pattern[actual_len - 1].delta_t; } @@ -1509,29 +1559,45 @@ static int lpg_parse_sdam(struct lpg *lpg) { int rc = 0; - if (lpg->data->nvmem_count == 0) + lpg->nvmem_count = lpg->data->nvmem_count; + if (lpg->nvmem_count == 0) return 0; - /* get the nvmem device for LPG/LUT config */ + if (lpg->nvmem_count > 2) + return -EINVAL; + + /* get the 1st nvmem device for LPG/LUT config */ lpg->lpg_chan_nvmem = devm_nvmem_device_get(lpg->dev, "lpg_chan_sdam"); if (IS_ERR(lpg->lpg_chan_nvmem)) { rc = PTR_ERR(lpg->lpg_chan_nvmem); - if (rc != -EPROBE_DEFER) - dev_err(lpg->dev, "Failed to get nvmem device, rc=%d\n", rc); - return rc; + goto err; } - lpg->pbs_dev = get_pbs_client_device(lpg->dev); - if (IS_ERR(lpg->pbs_dev)) { - rc = PTR_ERR(lpg->pbs_dev); - if (rc != -EPROBE_DEFER) - dev_err(lpg->dev, "Failed to get PBS client device, rc=%d\n", rc); - return rc; + if (lpg->nvmem_count == 1) { + /* get PBS device node if single NVMEM device */ + lpg->pbs_dev = get_pbs_client_device(lpg->dev); + if (IS_ERR(lpg->pbs_dev)) { + rc = PTR_ERR(lpg->pbs_dev); + if (rc != -EPROBE_DEFER) + dev_err(lpg->dev, "Failed to get PBS client device, rc=%d\n", rc); + return rc; + } + } else if (lpg->nvmem_count == 2) { + /* get the 2nd nvmem device for LUT pattern */ + lpg->lut_nvmem = devm_nvmem_device_get(lpg->dev, "lut_sdam"); + if (IS_ERR(lpg->lut_nvmem)) { + rc = PTR_ERR(lpg->lut_nvmem); + goto err; + } } lpg->ppg_en = true; return rc; +err: + if (rc != -EPROBE_DEFER) + dev_err(lpg->dev, "Failed to get nvmem device, rc=%d\n", rc); + return rc; } static int lpg_init_sdam(struct lpg *lpg) From patchwork Wed Jun 21 18:59:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 13287901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0682EB64D8 for ; Wed, 21 Jun 2023 19:02:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231878AbjFUTCZ (ORCPT ); Wed, 21 Jun 2023 15:02:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231703AbjFUTCM (ORCPT ); Wed, 21 Jun 2023 15:02:12 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF5EC2690; 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Signed-off-by: Anjelique Melendez --- drivers/leds/rgb/leds-qcom-lpg.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/leds/rgb/leds-qcom-lpg.c b/drivers/leds/rgb/leds-qcom-lpg.c index 273cb81260e7..6260e2c9fd94 100644 --- a/drivers/leds/rgb/leds-qcom-lpg.c +++ b/drivers/leds/rgb/leds-qcom-lpg.c @@ -1826,11 +1826,15 @@ static const struct lpg_data pm8150l_lpg_data = { static const struct lpg_data pm8350c_pwm_data = { .triled_base = 0xef00, + .lut_size = 122, + .lut_sdam_base = 0x45, + .nvmem_count = 2, + .num_channels = 4, .channels = (const struct lpg_channel_data[]) { - { .base = 0xe800, .triled_mask = BIT(7) }, - { .base = 0xe900, .triled_mask = BIT(6) }, - { .base = 0xea00, .triled_mask = BIT(5) }, + { .base = 0xe800, .triled_mask = BIT(7), .sdam_offset = 0x48 }, + { .base = 0xe900, .triled_mask = BIT(6), .sdam_offset = 0x56 }, + { .base = 0xea00, .triled_mask = BIT(5), .sdam_offset = 0x64 }, { .base = 0xeb00 }, }, };