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Thu, 22 Jun 2023 13:18:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF0000150A.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.17 via Frontend Transport; Thu, 22 Jun 2023 13:18:54 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 22 Jun 2023 08:18:53 -0500 From: Yazen Ghannam To: CC: , , , Yazen Ghannam Subject: [PATCH 1/2] x86/mce: Disable preemption for CPER decoding Date: Thu, 22 Jun 2023 08:18:40 -0500 Message-ID: <20230622131841.3153672-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622131841.3153672-1-yazen.ghannam@amd.com> References: <20230622131841.3153672-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|LV8PR12MB9081:EE_ X-MS-Office365-Filtering-Correlation-Id: e4939043-1299-49f5-0a02-08db73233a9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2023 13:18:54.6917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4939043-1299-49f5-0a02-08db73233a9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9081 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Scalable MCA systems may report errors found during boot-time polling through the ACPI Boot Error Record Table (BERT). The errors are logged in an "x86 Processor" Common Platform Error Record (CPER). The format of the x86 CPER does not include a logical CPU number, but it does provide the logical APIC ID for the logical CPU. Also, it does not explicitly provide MCA error information, but it can share this information using an "MSR Context" defined in the CPER format. The MCA error information is parsed by 1) Checking that the context matches the Scalable MCA register space. 2) Finding the logical CPU that matches the logical APIC ID from the CPER. 3) Filling in struct mce with the relevant data and logging it. All the above is done when the BERT is processed during late init. This can be scheduled on any CPU, and it may be preemptible. This results in two issues. 1) mce_setup() includes a call to smp_processor_id(). This will throw a warning if preemption is enabled. 2) mce_setup() will pull info from the executing CPU, so some info in struct mce may be incorrect for the CPU with the error. For example, in a dual-socket system, an error logged in socket 1 CPU but processed by a socket 0 CPU will save the PPIN of the socket 0 CPU. Fix the first issue by locally disabling preemption before calling mce_setup(). Fixes: 4a24d80b8c3e ("x86/mce, cper: Pass x86 CPER through the MCA handling chain") Signed-off-by: Yazen Ghannam Cc: stable@vger.kernel.org --- arch/x86/kernel/cpu/mce/apei.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 8ed341714686..2a7a51ca2995 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -97,7 +97,9 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) if (ctx_info->reg_arr_size < 48) return -EINVAL; + get_cpu(); mce_setup(&m); + put_cpu(); m.extcpu = -1; m.socketid = -1; From patchwork Thu Jun 22 13:18:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13289149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98B13EB64DA for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2023 13:18:55.2855 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abfb3bc5-c35d-4d96-a35b-08db73233af8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4446 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Scalable MCA systems may report errors found during boot-time polling through the ACPI Boot Error Record Table (BERT). The errors are logged in an "x86 Processor" Common Platform Error Record (CPER). The format of the x86 CPER does not include a logical CPU number, but it does provide the logical APIC ID for the logical CPU. Also, it does not explicitly provide MCA error information, but it can share this information using an "MSR Context" defined in the CPER format. The MCA error information is parsed by 1) Checking that the context matches the Scalable MCA register space. 2) Finding the logical CPU that matches the logical APIC ID from the CPER. 3) Filling in struct mce with the relevant data and logging it. All the above is done when the BERT is processed during late init. This can be scheduled on any CPU, and it may be preemptible. This results in two issues. 1) mce_setup() includes a call to smp_processor_id(). This will throw a warning if preemption is enabled. 2) mce_setup() will pull info from the executing CPU, so some info in struct mce may be incorrect for the CPU with the error. For example, in a dual-socket system, an error logged in socket 1 CPU but processed by a socket 0 CPU will save the PPIN of the socket 0 CPU. Fix the second issue by using the PPIN value cached during CPU init. Fixes: 4a24d80b8c3e ("x86/mce, cper: Pass x86 CPER through the MCA handling chain") Signed-off-by: Yazen Ghannam Cc: stable@vger.kernel.org --- arch/x86/kernel/cpu/mce/apei.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 2a7a51ca2995..db16dc3c7b03 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -103,11 +103,13 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) m.extcpu = -1; m.socketid = -1; + m.ppin = 0; for_each_possible_cpu(cpu) { if (cpu_data(cpu).initial_apicid == lapic_id) { m.extcpu = cpu; m.socketid = cpu_data(m.extcpu).phys_proc_id; + m.ppin = cpu_data(m.extcpu).ppin; break; } }