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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id i20-20020aa79094000000b0065a1b05193asm4604268pfa.185.2023.06.22.07.13.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 07:13:51 -0700 (PDT) From: Jacky Huang To: mturquette@baylibre.com, sboyd@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org List-Id: Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, soc@kernel.org, krzysztof.kozlowski+dt@linaro.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH v3 1/3] clk: nuvoton: Add clk-ma35d1.h for driver extern functions Date: Thu, 22 Jun 2023 14:13:41 +0000 Message-Id: <20230622141343.13595-2-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622141343.13595-1-ychuang570808@gmail.com> References: <20230622141343.13595-1-ychuang570808@gmail.com> MIME-Version: 1.0 From: Jacky Huang Moved the declaration of extern functions ma35d1_reg_clk_pll() and ma35d1_reg_adc_clkdiv() from the .c files to the newly created header file clk-ma35d1.h. Signed-off-by: Jacky Huang --- drivers/clk/nuvoton/clk-ma35d1-divider.c | 7 ++----- drivers/clk/nuvoton/clk-ma35d1-pll.c | 5 ++--- drivers/clk/nuvoton/clk-ma35d1.c | 10 ++-------- drivers/clk/nuvoton/clk-ma35d1.h | 18 ++++++++++++++++++ 4 files changed, 24 insertions(+), 16 deletions(-) create mode 100644 drivers/clk/nuvoton/clk-ma35d1.h diff --git a/drivers/clk/nuvoton/clk-ma35d1-divider.c b/drivers/clk/nuvoton/clk-ma35d1-divider.c index 0c2bed47909a..bb8c23d2b895 100644 --- a/drivers/clk/nuvoton/clk-ma35d1-divider.c +++ b/drivers/clk/nuvoton/clk-ma35d1-divider.c @@ -9,6 +9,8 @@ #include #include +#include "clk-ma35d1.h" + struct ma35d1_adc_clk_div { struct clk_hw hw; void __iomem *reg; @@ -20,11 +22,6 @@ struct ma35d1_adc_clk_div { spinlock_t *lock; }; -struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, - struct clk_hw *parent_hw, spinlock_t *lock, - unsigned long flags, void __iomem *reg, - u8 shift, u8 width, u32 mask_bit); - static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw) { return container_of(_hw, struct ma35d1_adc_clk_div, hw); diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c index e4c9f94e6796..ff3fb8b87c24 100644 --- a/drivers/clk/nuvoton/clk-ma35d1-pll.c +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c @@ -15,6 +15,8 @@ #include #include +#include "clk-ma35d1.h" + /* PLL frequency limits */ #define PLL_FREF_MAX_FREQ (200 * HZ_PER_MHZ) #define PLL_FREF_MIN_FREQ (1 * HZ_PER_MHZ) @@ -71,9 +73,6 @@ struct ma35d1_clk_pll { void __iomem *ctl2_base; }; -struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name, - struct clk_hw *parent_hw, void __iomem *base); - static inline struct ma35d1_clk_pll *to_ma35d1_clk_pll(struct clk_hw *_hw) { return container_of(_hw, struct ma35d1_clk_pll, hw); diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c index 297b11585f00..8dfa762494fe 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -12,6 +12,8 @@ #include #include +#include "clk-ma35d1.h" + static DEFINE_SPINLOCK(ma35d1_lock); #define PLL_MAX_NUM 5 @@ -60,14 +62,6 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define PLL_MODE_FRAC 1 #define PLL_MODE_SS 2 -struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, - const char *name, struct clk_hw *parent_hw, - void __iomem *base); -struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, - struct clk_hw *hw, spinlock_t *lock, - unsigned long flags, void __iomem *reg, - u8 shift, u8 width, u32 mask_bit); - static const struct clk_parent_data ca35clk_sel_clks[] = { { .index = 0 }, /* HXT */ { .index = 1 }, /* CAPLL */ diff --git a/drivers/clk/nuvoton/clk-ma35d1.h b/drivers/clk/nuvoton/clk-ma35d1.h new file mode 100644 index 000000000000..3adee440f60a --- /dev/null +++ b/drivers/clk/nuvoton/clk-ma35d1.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#ifndef __DRV_CLK_NUVOTON_MA35D1_H +#define __DRV_CLK_NUVOTON_MA35D1_H + +struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name, + struct clk_hw *parent_hw, void __iomem *base); + +struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, + struct clk_hw *parent_hw, spinlock_t *lock, + unsigned long flags, void __iomem *reg, + u8 shift, u8 width, u32 mask_bit); + +#endif /* __DRV_CLK_NUVOTON_MA35D1_H */ From patchwork Thu Jun 22 14:13:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 13289221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B123BEB64DA for ; Thu, 22 Jun 2023 14:13:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 787BBC433CA; Thu, 22 Jun 2023 14:13:55 +0000 (UTC) Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 8F7C9C433C9; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id i20-20020aa79094000000b0065a1b05193asm4604268pfa.185.2023.06.22.07.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 07:13:53 -0700 (PDT) From: Jacky Huang To: mturquette@baylibre.com, sboyd@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org List-Id: Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, soc@kernel.org, krzysztof.kozlowski+dt@linaro.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH v3 2/3] clk: nuvoton: Update all constant hex values to lowercase Date: Thu, 22 Jun 2023 14:13:42 +0000 Message-Id: <20230622141343.13595-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622141343.13595-1-ychuang570808@gmail.com> References: <20230622141343.13595-1-ychuang570808@gmail.com> MIME-Version: 1.0 From: Jacky Huang The constant hex values used to define register offsets were written in uppercase. This patch update all these constant hex values to be lowercase. Signed-off-by: Jacky Huang --- drivers/clk/nuvoton/clk-ma35d1.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c index 8dfa762494fe..733750dda0f4 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -22,19 +22,19 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define REG_CLK_PWRCTL 0x00 #define REG_CLK_SYSCLK0 0x04 #define REG_CLK_SYSCLK1 0x08 -#define REG_CLK_APBCLK0 0x0C +#define REG_CLK_APBCLK0 0x0c #define REG_CLK_APBCLK1 0x10 #define REG_CLK_APBCLK2 0x14 #define REG_CLK_CLKSEL0 0x18 -#define REG_CLK_CLKSEL1 0x1C +#define REG_CLK_CLKSEL1 0x1c #define REG_CLK_CLKSEL2 0x20 #define REG_CLK_CLKSEL3 0x24 #define REG_CLK_CLKSEL4 0x28 -#define REG_CLK_CLKDIV0 0x2C +#define REG_CLK_CLKDIV0 0x2c #define REG_CLK_CLKDIV1 0x30 #define REG_CLK_CLKDIV2 0x34 #define REG_CLK_CLKDIV3 0x38 -#define REG_CLK_CLKDIV4 0x3C +#define REG_CLK_CLKDIV4 0x3c #define REG_CLK_CLKOCTL 0x40 #define REG_CLK_STATUS 0x50 #define REG_CLK_PLL0CTL0 0x60 @@ -44,18 +44,18 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define REG_CLK_PLL3CTL0 0x90 #define REG_CLK_PLL3CTL1 0x94 #define REG_CLK_PLL3CTL2 0x98 -#define REG_CLK_PLL4CTL0 0xA0 -#define REG_CLK_PLL4CTL1 0xA4 -#define REG_CLK_PLL4CTL2 0xA8 -#define REG_CLK_PLL5CTL0 0xB0 -#define REG_CLK_PLL5CTL1 0xB4 -#define REG_CLK_PLL5CTL2 0xB8 -#define REG_CLK_CLKDCTL 0xC0 -#define REG_CLK_CLKDSTS 0xC4 -#define REG_CLK_CDUPB 0xC8 -#define REG_CLK_CDLOWB 0xCC -#define REG_CLK_CKFLTRCTL 0xD0 -#define REG_CLK_TESTCLK 0xF0 +#define REG_CLK_PLL4CTL0 0xa0 +#define REG_CLK_PLL4CTL1 0xa4 +#define REG_CLK_PLL4CTL2 0xa8 +#define REG_CLK_PLL5CTL0 0xb0 +#define REG_CLK_PLL5CTL1 0xb4 +#define REG_CLK_PLL5CTL2 0xb8 +#define REG_CLK_CLKDCTL 0xc0 +#define REG_CLK_CLKDSTS 0xc4 +#define REG_CLK_CDUPB 0xc8 +#define REG_CLK_CDLOWB 0xcc +#define REG_CLK_CKFLTRCTL 0xd0 +#define REG_CLK_TESTCLK 0xf0 #define REG_CLK_PLLCTL 0x40 #define PLL_MODE_INT 0 From patchwork Thu Jun 22 14:13:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 13289222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC727EB64DC for ; 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id i20-20020aa79094000000b0065a1b05193asm4604268pfa.185.2023.06.22.07.13.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 07:13:55 -0700 (PDT) From: Jacky Huang To: mturquette@baylibre.com, sboyd@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org List-Id: Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, soc@kernel.org, krzysztof.kozlowski+dt@linaro.org, schung@nuvoton.com, Jacky Huang Subject: [PATCH v3 3/3] clk: nuvoton: Use clk_parent_data instead of string for parent clock Date: Thu, 22 Jun 2023 14:13:43 +0000 Message-Id: <20230622141343.13595-4-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230622141343.13595-1-ychuang570808@gmail.com> References: <20230622141343.13595-1-ychuang570808@gmail.com> MIME-Version: 1.0 From: Jacky Huang For the declaration of parent clocks, use struct clk_parent_data instead of a string. Due to the change in the passed arguments, replace the usage of devm_clk_hw_register_mux() with clk_hw_register_mux_parent_data() for all cases. Signed-off-by: Jacky Huang --- drivers/clk/nuvoton/clk-ma35d1.c | 306 ++++++++++++++++++++++--------- 1 file changed, 219 insertions(+), 87 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c index 733750dda0f4..f1fe7edd21b5 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -63,167 +63,298 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define PLL_MODE_SS 2 static const struct clk_parent_data ca35clk_sel_clks[] = { - { .index = 0 }, /* HXT */ - { .index = 1 }, /* CAPLL */ - { .index = 2 } /* DDRPLL */ + { .fw_name = "hxt", }, + { .fw_name = "capll", }, + { .fw_name = "ddrpll", }, }; -static const char *const sysclk0_sel_clks[] = { - "epll_div2", "syspll" +static const struct clk_parent_data sysclk0_sel_clks[] = { + { .fw_name = "epll_div2", }, + { .fw_name = "syspll", }, }; -static const char *const sysclk1_sel_clks[] = { - "hxt", "syspll" +static const struct clk_parent_data sysclk1_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "syspll", }, }; -static const char *const axiclk_sel_clks[] = { - "capll_div2", "capll_div4" +static const struct clk_parent_data axiclk_sel_clks[] = { + { .fw_name = "capll_div2", }, + { .fw_name = "capll_div4", }, }; -static const char *const ccap_sel_clks[] = { - "hxt", "vpll", "apll", "syspll" +static const struct clk_parent_data ccap_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "vpll", }, + { .fw_name = "apll", }, + { .fw_name = "syspll", }, }; -static const char *const sdh_sel_clks[] = { - "syspll", "apll", "dummy", "dummy" +static const struct clk_parent_data sdh_sel_clks[] = { + { .fw_name = "syspll", }, + { .fw_name = "apll", }, }; -static const char *const dcu_sel_clks[] = { - "epll_div2", "syspll" +static const struct clk_parent_data dcu_sel_clks[] = { + { .fw_name = "epll_div2", }, + { .fw_name = "syspll", }, }; -static const char *const gfx_sel_clks[] = { - "epll", "syspll" +static const struct clk_parent_data gfx_sel_clks[] = { + { .fw_name = "epll", }, + { .fw_name = "syspll", }, }; -static const char *const dbg_sel_clks[] = { - "hirc", "syspll" +static const struct clk_parent_data dbg_sel_clks[] = { + { .fw_name = "hirc", }, + { .fw_name = "syspll", }, }; -static const char *const timer0_sel_clks[] = { - "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer0_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer1_sel_clks[] = { - "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer1_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer2_sel_clks[] = { - "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer2_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer3_sel_clks[] = { - "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer3_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer4_sel_clks[] = { - "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer4_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer5_sel_clks[] = { - "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer5_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer6_sel_clks[] = { - "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer6_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer7_sel_clks[] = { - "hxt", "lxt", "pclk0", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer7_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk0", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer8_sel_clks[] = { - "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer8_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer9_sel_clks[] = { - "hxt", "lxt", "pclk1", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer9_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk1", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer10_sel_clks[] = { - "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer10_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const timer11_sel_clks[] = { - "hxt", "lxt", "pclk2", "dummy", "dummy", "lirc", "dummy", "hirc" +static const struct clk_parent_data timer11_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "pclk2", }, + { .index = -1, }, + { .index = -1, }, + { .fw_name = "lirc", }, + { .index = -1, }, + { .fw_name = "hirc", }, }; -static const char *const uart_sel_clks[] = { - "hxt", "sysclk1_div2", "dummy", "dummy" +static const struct clk_parent_data uart_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "sysclk1_div2", }, }; -static const char *const wdt0_sel_clks[] = { - "dummy", "lxt", "pclk3_div4096", "lirc" +static const struct clk_parent_data wdt0_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wdt1_sel_clks[] = { - "dummy", "lxt", "pclk3_div4096", "lirc" +static const struct clk_parent_data wdt1_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wdt2_sel_clks[] = { - "dummy", "lxt", "pclk4_div4096", "lirc" +static const struct clk_parent_data wdt2_sel_clks[] = { + { .index = -1, }, + { .fw_name = "lxt", }, + { .fw_name = "pclk4_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wwdt0_sel_clks[] = { - "dummy", "dummy", "pclk3_div4096", "lirc" +static const struct clk_parent_data wwdt0_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wwdt1_sel_clks[] = { - "dummy", "dummy", "pclk3_div4096", "lirc" +static const struct clk_parent_data wwdt1_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk3_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const wwdt2_sel_clks[] = { - "dummy", "dummy", "pclk4_div4096", "lirc" +static const struct clk_parent_data wwdt2_sel_clks[] = { + { .index = -1, }, + { .index = -1, }, + { .fw_name = "pclk4_div4096", }, + { .fw_name = "lirc", }, }; -static const char *const spi0_sel_clks[] = { - "pclk1", "apll", "dummy", "dummy" +static const struct clk_parent_data spi0_sel_clks[] = { + { .fw_name = "pclk1", }, + { .fw_name = "apll", }, }; -static const char *const spi1_sel_clks[] = { - "pclk2", "apll", "dummy", "dummy" +static const struct clk_parent_data spi1_sel_clks[] = { + { .fw_name = "pclk2", }, + { .fw_name = "apll", }, }; -static const char *const spi2_sel_clks[] = { - "pclk1", "apll", "dummy", "dummy" +static const struct clk_parent_data spi2_sel_clks[] = { + { .fw_name = "pclk1", }, + { .fw_name = "apll", }, }; -static const char *const spi3_sel_clks[] = { - "pclk2", "apll", "dummy", "dummy" +static const struct clk_parent_data spi3_sel_clks[] = { + { .fw_name = "pclk2", }, + { .fw_name = "apll", }, }; -static const char *const qspi0_sel_clks[] = { - "pclk0", "apll", "dummy", "dummy" +static const struct clk_parent_data qspi0_sel_clks[] = { + { .fw_name = "pclk0", }, + { .fw_name = "apll", }, }; -static const char *const qspi1_sel_clks[] = { - "pclk0", "apll", "dummy", "dummy" +static const struct clk_parent_data qspi1_sel_clks[] = { + { .fw_name = "pclk0", }, + { .fw_name = "apll", }, }; -static const char *const i2s0_sel_clks[] = { - "apll", "sysclk1_div2", "dummy", "dummy" +static const struct clk_parent_data i2s0_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "sysclk1_div2", }, }; -static const char *const i2s1_sel_clks[] = { - "apll", "sysclk1_div2", "dummy", "dummy" +static const struct clk_parent_data i2s1_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "sysclk1_div2", }, }; -static const char *const can_sel_clks[] = { - "apll", "vpll" +static const struct clk_parent_data can_sel_clks[] = { + { .fw_name = "apll", }, + { .fw_name = "vpll", }, }; -static const char *const cko_sel_clks[] = { - "hxt", "lxt", "hirc", "lirc", "capll_div4", "syspll", - "ddrpll", "epll_div2", "apll", "vpll", "dummy", "dummy", - "dummy", "dummy", "dummy", "dummy" +static const struct clk_parent_data cko_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, + { .fw_name = "hirc", }, + { .fw_name = "lirc", }, + { .fw_name = "capll_div4", }, + { .fw_name = "syspll", }, + { .fw_name = "ddrpll", }, + { .fw_name = "epll_div2", }, + { .fw_name = "apll", }, + { .fw_name = "vpll", }, }; -static const char *const smc_sel_clks[] = { - "hxt", "pclk4" +static const struct clk_parent_data smc_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "pclk4", }, }; -static const char *const kpi_sel_clks[] = { - "hxt", "lxt" +static const struct clk_parent_data kpi_sel_clks[] = { + { .fw_name = "hxt", }, + { .fw_name = "lxt", }, }; static const struct clk_div_table ip_div_table[] = { @@ -255,11 +386,12 @@ static struct clk_hw *ma35d1_clk_mux_parent(struct device *dev, const char *name static struct clk_hw *ma35d1_clk_mux(struct device *dev, const char *name, void __iomem *reg, u8 shift, u8 width, - const char *const *parents, int num_parents) + const struct clk_parent_data *pdata, + int num_pdata) { - return devm_clk_hw_register_mux(dev, name, parents, num_parents, - CLK_SET_RATE_NO_REPARENT, reg, shift, - width, 0, &ma35d1_lock); + return clk_hw_register_mux_parent_data(dev, name, pdata, num_pdata, + CLK_SET_RATE_NO_REPARENT, reg, shift, + width, 0, &ma35d1_lock); } static struct clk_hw *ma35d1_clk_divider(struct device *dev, const char *name,